A7 B7 五、發明説明（ 發明領域： 本發明係有關於一種積體電路製程中的電容器結 種在銅金屬製程^形成金^極板的電容器 L構和其製程方法。 發明背景： 年來半導體製造工業之趨勢為將記憶胞之尺寸減 J ，增加積集度和记憶體晶片之記憶容量，當半導趙的線 寬從次微米持續往下發展時，記憶體之特性仍需加以維 持。例如動態隨機存取記憶體（DRAM)中的電容器所需之最 少的儲存電荷量仍然是不變的，如此方能維持記憶體之高 信賴度。 (請先聞讀背面之注意事項再填寫本頁) 系- 經濟部智慧財產局員工消費合作社印製 對於高度積集化之半導體元件來說，由 的面積減小，使得其電容量也減小了。如此 容易受到0：粒子輻射之影響而必需經常加以 因此現今之電容器型式有許多不同的變化。 國專利號碼第5457〇65號中，由Cheng 的 ” METHOD OF MANUFACTURING A CAPACITOR STRUCTURE HAVING CAPACITANCE” ’即為形成堆疊式電容器以 結構。而其它型式之電容器如溝渠電容器或 等等’其目的也都是為了增加電容器之面積 能。 於平面電容器 將使得電容器 再補充電荷， 例如描述於美 等人所揭露 NEW DRAM INCREASED 增加電容值的 皇冠型電容器 ，以增進其效 "- Γ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 4326 4 A7 B7 五、發明説明（） 儲存電容值之增加可藉由如上所述增加電容器之面 積’或將介電層做薄及利用高介電常數之介電層等方式來 達成。然而，由於會有電荷洩露（如F〇wler_N〇rdheim隧道 效應）和介電層品質的問題，因此要將電容器做薄會有一定 之限制，而可取代一氧化矽（Si〇2)之材料如Ta2〇5或BST 等則是現在經常加以利用的高介電常數材料（現在仍有許 多人在研究較高介電常數之材料）。 另外’傳統的電容器製作，無論是用於DRAM或者是 混合信號（mixed signal)電路（此電路一般可處理類比和數 位彳5號’且可能包含有類比/數位、數位/類比、和數位信號 處理器等元件）’通常都利用摻雜複晶矽做為電容器之上、 下電極板然而’當半導雜的積集度增加，元件.的操作速 度加快時，傳統的摻雜複晶矽/介電層/摻雜複晶矽的電容器 結構將無法滿足實際上的需求。同時，此類半導體材料會 因為施加電壓而產生介面的空乏模式（depletion mode)，因 而影響電容器的信賴度》 I- n ^nt HI ^^^1 I ^^^1 n -- I- I ^^^1^ (请先聞讀背而之法^^項，鼻填寫本茛〕 經濟部智慧財產局員工消費合作社印製 然而’近年來不斷有人針對金屬電極板之電容器加以 研究’如第一 A-— D圖中所示的，即為利用鋁金屬作為電 容器上、下電極板之截面示意圖。於内金屬介電層（1?^1))100 之上蝕刻鋁金屬層110之後，沉積介電層120和鋁金屬層 130而形成電容器結構，接著以介電層14〇沉積和鎢插塞 本纸張尺度適用中國圉家標準（CNS) A4規格（210x297公釐） Γ 14 32 Ρ Α7 __—___Β7 五、發明説明（) ~ ~ 將電容器連接到外部電路上。由於銘金屬較不易氧化，因 而可形成鋁金屬/介電層/銘金屬之電容器結構。雖缺現今之 積艘電路中最主要的導線材料為銘基材，而純铭的電阻係 數約為2.7微歐姆-厘米，同時並加入發、#而形成合金材 料。鋁合金的使用目的在提升純鋁基材的抗電遷移 (electromigration resistanee)能力。以免鋁、矽界面在融合 溫度時產生擴散的現象。然而，為有效降低阻抗率，銅金 屬方為最佳的選擇，因為銅材料的電阻係數約為17微歐 姆-厘米左右，要遠小於鋁材質。同時銅金屬本身的抗電遷 移能力也要優於铭材料’因此為可預期的一種導體材 雖然如此，由於銅金屬具容易氧化及不易蝕刻的缺 點’因而銅導線係利用雙層鑲嵌法（dual damascene)取代傳 統的電讓轴刻方式形成，因為在鋼金屬上直接沉.積氧化層 將消耗銅材料’並產生快速的擴散作用而造成漏電流，所 以上述鋁金屬電極板之電容器結構並不適合雙層鑲嵌結構 的銅金屬製程’是故，仍需要有一種有關銅金屬電極板的 電容器結構和製造方法，以因應下一世代的積體電路製程 需求。 (請先閲讀背面之注意事項.再填寫本頁) 經濟部智慧財產局員工涓費合作杜印製 電 號 信 合 混 或 體 憶 記 的 統 傳 中 景 背 明 :發 述之 概述 及上 的於 目鑒 明 發 矽 晶展 複發 雜向 摻方 成化 形集 常積 通度 器高 容朝 電路 的電 中體 路積 之 元 當快 但加 ，也 板度 極速 電 t 下ί h>的 件 本紙張尺度適用中國國家標牟（CNS ) A4規格（210X297公釐） Γ 14 32 6 4 1 A7 _ B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（） 時，金屬材料所形成的電容器電極板方為最佳的選擇。而 例如鋁'鎢等材料所形成的電極板結構並不適合銅製程， 因而本發明的主I目的t —，即為形成鋼製帛中的金属電 極板結構和製造方法，以做到具高信賴度的電容器。 本發明的另一目的，在利用過渡金屬材料以改善銅金 屬電極板的附著能力’增進電容器堆疊的穩定性^ 根據以上所述之目的，本發明將概述如下： 首先&供一具有主動元件和被動元件之半導體基 板’並可根據需求而形成多重金屬内連線，然後於此基板 最上層沉積低k值的介電材料層，以形成内金屬介電層 (Inter-Metal Dielectric，iMD)。接著，以傳統之微影和蝕 刻製程於此介電層上蝕刻形成鑲嵌區，再以電化學沉積法 (Electrochemical Deposition，ECD)或濺鍍法而沉積銅金 屬層。然後以化學機械研磨（CMP)將其平坦化，並以介電 層作為研磨之終點偵測。 之後’以減鍍法形成氮化组（TaN)阻障層，以避免銅 金屬和後續氧化鍍層之間的擴散作用，並增加其黏附性， 而此阻障層之厚度約在500- 1 500埃左右。同時亦可甴氮 化鈕/組（TaN/Ta)、氮化鈦（TiN)、氮化鈦/鈦（TiN/Ti)等過 渡金屬材料組成。然後再於介電層上沉積薄的介電層材 料，此介電材料的厚度約在40-100埃之間，且可由氧化 (請先閲讀背面之注意事項再填寫本頁) 策- 訂 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） « 1432641 五、發明説明（） ~ ~一~ 硬氮化WN)層、氡切氧切（卿）層或高 介電常數的材料如Ta2〇5或BaTi〇3所組成。接著再沉積 銘金屬層或第二層阻障層以作為電容器之上電極板，但若 只以阻障層來形成上電極板時，將不需額外的反應室來濺 鍍鋁金屬’而可節省製造成本。 當上述之阻障層/介電層/阻障層堆疊形成之後，接著 以非等向性之乾式蝕刻技術將此堆疊層蝕刻’並以銅金屬 作為蝕刻終止層。然後再沉積第一氮化矽層於此堆疊層和 基板之上，且厚度約在500·〗5〇〇埃左右。接著再沉積第 一低k值介電材料於氮化矽層之上，並可視需要以化學機 械研磨法加以平坦化。於低k介電層之後’則再沉積第二 氣化破層’並以圖案化光阻層將此氮化矽層蝕刻而形成和 底層導電層接觸對準之圖案區域，然後再以第二低k介電 層加以覆蓋。上述之低k介電層厚度大約在2000到8000 埃左右。 (請先閱讀背面之注意事項，再填寫本頁) 阻來 光幕 化罩 案刻 圖姓 個為 二作 第層 以阻 ，光 後此 之以 積並 沉， 層上 之 介層二電 第介 、二 1 第 第於 當成 形 層 經濟部智慧財產局員工消費合作社印製 第 刻 蝕 來 幕 罩 ΙΊ 亥 二钮J 第為刻 以作姓 且層為 ，化作 層氣層 電二矽 介第化 二化氮 第案一 刻囷第 蝕以以 止 終 刻 蝕 為 作 層 化 氣 電 介 一 再且 層層 雙而 當層 〇 屬 構金 完 點 終 結 録 層 雙 成 形 而 此 如 銅 成 形 法 方 積 沉 學 化 以 後。 之作 成製 形之 構器 结容 嵌電 鑲成 本紙張尺度適用中國國家標準（CNS > A4规格（210X297公釐） P4326 4 ] A7 B7 五、發明説明（） 當以本發明之銅製程形成電容器結構之後，由於氮化 鋁阻障層對銅具高黏附性，因而此阻障層的下電極板將可 改善介電層氧化物/氮化钽/銅金屬堆疊之黏附性，更可避 免銅金屬擴散。而以此結構所形成的電容器，亦能提高電 容器的信賴度。 圖式簡單說明： 本發明的較佳實施例將於往後之說明文字中輔以下 列圖形做更詳細的闡述： 第一 A-— D囷所示為依照傳統方法形成鋁金屬之電 經濟部智慧財產局員工消費合作社印製 截障 半層器 的阻 於雙容 層的 層成電 屬 '上 電 形 之 金之 介上板 銅 層：之 板 極 之 屬圖值 基 電 嵌 金意 K 體 屬 鑲 銅示& 導 金 成 成面5 半 成 形 形截形 於 形 明 明^月明明 :發 發堆發 ，發及發 圖本 本的本圖本；本 意照 照層8,3意照圖照 示依 依障依示依意依。 面為 為阻為面為示為圖 截示 示和示截示面示意 ： 的所 所、所之所截所示 明 板圖；圖層圖上圖之圖面 說 極二圖三化四板五構六截 細 電第意第氧第基第結第的 詳 器示 、 體 嵌構明 容 面層導 鑲結發 ^ili l I ^ϋ' VWJ (請先閲讀背面之注意事項、再填寫本頁〕 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 「,4 326 4 A7 B7 五、發明説明（ 電容器結構在積趙電路中的應用相當的廣泛，例如於 動態隨機^記憶體（DRAM)中儲存訊號之用的電容器， 或混合信號（mixed signal、接A7 B7 V. Description of the invention (Field of the invention: The present invention relates to a capacitor structure of a capacitor integrated in the process of integrated circuit manufacturing in a copper metal process ^ to form a gold electrode plate and its manufacturing method. BACKGROUND OF THE INVENTION: Semiconductor manufacturing The industry trend is to reduce the size of the memory cell by J, increase the degree of accumulation and the memory capacity of the memory chip. When the line width of the semiconducting Zhao continues to develop from sub-microns, the characteristics of the memory still need to be maintained. For example, the minimum amount of stored charge required by a capacitor in a dynamic random access memory (DRAM) is still constant, so that it can maintain the high reliability of the memory. (Please read the precautions on the back before filling out this Page) Department-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. For highly integrated semiconductor components, the area is reduced, so that their capacitance is also reduced. So easily affected by 0: particle radiation It must be added frequently, so today there are many different changes in the type of capacitors. In China Patent No. 5457〇65, "Method of MANUFACTURING A CAPACITOR" by Cheng STRUCTURE HAVING CAPACITANCE "" is to form a stacked capacitor structure. The other types of capacitors such as trench capacitors or the like "are also designed to increase the area energy of the capacitor. The planar capacitor will make the capacitor recharge, such as the description New DRAM INCREASED disclosed by Yu Mei et al. Increasing the value of the crown-type capacitor to increase its efficiency "-Γ This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 4326 4 A7 B7 V. Invention Explanation () The increase of the storage capacitance value can be achieved by increasing the capacitor area as described above or thinning the dielectric layer and using a dielectric layer with a high dielectric constant. However, due to charge leakage (such as Föwler_Nördheim tunnel effect) and the quality of the dielectric layer. Therefore, there are certain restrictions on thinning the capacitor. Materials that can replace silicon oxide (Si〇2) such as Ta205 or BST are High dielectric constant materials that are often used today (many people are still studying materials with higher dielectric constants). Also 'traditional Container production, whether for DRAM or mixed signal circuits (this circuit can generally handle analog and digital '# 5' and may include analog / digital, digital / analog, and digital signal processor components) 'Usually doped polycrystalline silicon is used as the upper and lower electrode plates of the capacitor. However, as the accumulation of semiconducting impurities increases and the operation speed of the device increases, the traditional doped polycrystalline silicon / dielectric layer / The capacitor structure doped with polycrystalline silicon will not be able to meet the actual needs. At the same time, such semiconductor materials will generate a depletion mode of the interface due to the application of voltage, thus affecting the reliability of the capacitor "I- n ^ nt HI ^^^ 1 I ^^^ 1 n-I- I ^^^ 1 ^ (Please read the method of ^^ first, fill in the buttercup by nose)] Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs In recent years, people have been studying capacitors for metal electrode plates. As shown in the first A-D diagram, it is a schematic cross-sectional view of the upper and lower electrode plates of aluminum capacitors. After the aluminum metal layer 110 is etched on the inner metal dielectric layer (1? ^ 1)) 100, a dielectric layer 120 and an aluminum metal layer 130 are deposited to form a capacitor structure, and then a dielectric layer 14 is deposited and a tungsten plug is formed. This paper size is in accordance with China National Standard (CNS) A4 specification (210x297 mm) Γ 14 32 Ρ Α7 __—___ Β7 V. Description of the invention () ~ ~ Connect the capacitor to the external circuit. Since Ming metal is less susceptible to oxidation, a capacitor structure of aluminum metal / dielectric layer / ming metal can be formed. Although the most important wire material in today's Jaeger-LeCoultre circuits is the base material, the resistance factor of pure Ming is about 2.7 micro-ohm-cm, and the alloy material is formed by adding hair and #. The purpose of the aluminum alloy is to improve the electromigration resistanee ability of the pure aluminum substrate. This prevents the aluminum and silicon interfaces from diffusing at the fusion temperature. However, in order to effectively reduce the resistivity, copper metal is the best choice because the resistivity of copper is about 17 micro-ohm-cm, which is much smaller than that of aluminum. At the same time, the copper metal itself has better resistance to electromigration than 'Ming material', so it is a predictable conductor material. However, because copper metal has the disadvantages of being easy to oxidize and not easy to etch ', the copper wire system uses the dual-layer inlay method (dual damascene) instead of the traditional electric let-off method, because the direct deposition on the steel metal. The accumulated oxide layer will consume the copper material and cause rapid diffusion and cause leakage current, so the capacitor structure of the above aluminum metal electrode plate is not suitable Therefore, there is still a need for a capacitor structure and manufacturing method for copper metal electrode plates in order to meet the needs of the next-generation integrated circuit manufacturing process. (Please read the notes on the back first and then fill out this page) The staff of the Intellectual Property Bureau of the Ministry of Economic Affairs has cooperated to print the electronic transmission of the letter or letter. Yu Mujian showed that the recurrence of the silicon crystals and the formation of the doped cubes and the formation of the set of constant integration protractors of the high-capacity circuit of the electric circuit body of the product should be fast but increase, but also the speed of the electric current t h> Paper size is applicable to China National Standards (CNS) A4 specification (210X297 mm) Γ 14 32 6 4 1 A7 _ B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Capacitors formed by metal materials The electrode plate is the best choice. The electrode plate structure formed by materials such as aluminum and tungsten is not suitable for the copper process. Therefore, the main purpose of the present invention is to form a metal electrode plate structure and a manufacturing method in a steel gallium to achieve high reliability. Degree capacitor. Another object of the present invention is to improve the adhesion of copper metal electrode plates by using transition metal materials to improve the stability of the capacitor stack. According to the above-mentioned purpose, the present invention will be summarized as follows: First, for an active device And passive component semiconductor substrates, and multiple metal interconnects can be formed as required, and then a low-k dielectric material layer is deposited on the top layer of the substrate to form an inter-metal dielectric (iMD) . Next, the dielectric layer is etched to form a damascene region by a conventional lithography and etching process, and then a copper metal layer is deposited by an electrochemical deposition method (ECD) or a sputtering method. It is then planarized by chemical mechanical polishing (CMP), and the dielectric layer is used as the end point of the polishing. Afterwards, a nitride group (TaN) barrier layer is formed by a subtractive plating method to avoid the diffusion effect between the copper metal and the subsequent oxide plating layer and increase its adhesion. The thickness of this barrier layer is about 500-1 500 Aye or so. At the same time, it can also be composed of transition metal materials such as nitride button / group (TaN / Ta), titanium nitride (TiN), titanium nitride / titanium (TiN / Ti). Then deposit a thin layer of dielectric material on the dielectric layer. The thickness of this dielectric material is about 40-100 angstroms, and it can be oxidized (please read the precautions on the back before filling this page). Paper size applies Chinese National Standard (CNS) A4 specification (210X297mm) «1432641 V. Description of the invention () ~ ~-~ Hard nitrided layer (WN) layer, tangent oxygen cut (Qing) layer or high dielectric constant materials Such as Ta205 or BaTi03. Next, a metal layer or a second barrier layer is deposited as the electrode plate on the capacitor, but if the upper electrode plate is formed only by the barrier layer, no additional reaction chamber is needed to sputter the aluminum metal. Save manufacturing costs. After the above barrier layer / dielectric layer / barrier layer stack is formed, the stack layer is then etched 'using an anisotropic dry etching technique and copper metal is used as an etching stop layer. Then, a first silicon nitride layer is deposited on the stacked layer and the substrate, and the thickness is about 500 · 500 angstroms. Then, a first low-k dielectric material is deposited on the silicon nitride layer, and it may be planarized by chemical mechanical polishing as required. After the low-k dielectric layer, 'then deposit a second vaporization layer' and etch this silicon nitride layer with a patterned photoresist layer to form a patterned area in contact with the underlying conductive layer, and then use a second The low-k dielectric layer is covered. The thickness of the low-k dielectric layer is about 2000 to 8000 Angstroms. (Please read the notes on the back first, and then fill out this page.) The block diagram of the light curtain cover is used as the second layer to block, and after the light, it is accumulated and settled.介 ， 第 1 号 Yudang formation printed by the consumer co-operatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the etched curtain cover Ί 二 Ⅱ button J is engraved with a surname and a layer, which is transformed into a layer of gas and a layer of silicon. Nitrogen and Nitrogen Dioxide The first moment of etch and the first etch is to stop the etching as the layered gas dielectric repeatedly and layer by layer, and when the layer 0 is a gold finish point, the layer is double-formed, and this is like the copper forming method. After the accumulation of academics. The shape of the structure and the embedded electric cost of the structure is applicable to the Chinese national standard (CNS > A4 specification (210X297 mm) P4326 4] A7 B7 V. Description of the invention () When the capacitor is formed by the copper process of the present invention After the structure, because the aluminum nitride barrier layer has high adhesion to copper, the lower electrode plate of the barrier layer can improve the adhesion of the dielectric layer oxide / tantalum nitride / copper metal stack and avoid copper. Metal diffusion. And the capacitor formed by this structure can also improve the reliability of the capacitor. Brief description of the drawings: The preferred embodiment of the present invention will be described in more detail in the following explanatory text with the following figures: The first A-—D 囷 shows the traditional method of forming aluminum metal. The Ministry of Economics, Intellectual Property Bureau, and the Employees ’Cooperatives of the Intellectual Property Bureau have printed a blocking half-layer device. The copper layer on the plate: The plate is of the figure, the base is gold-embedded, and the body is copper-plated. The gold guide is formed into a surface. 5 The semi-shaped shape is cut in the shape of the moon. And map Original copy of this book; Original plan according to layer 8,3 According to plan, according to the obstacle, according to the obstacle. The surface is the resistance, the surface is shown as the diagram, and the surface is shown: The cut-out diagram shown in the figure; the drawing on the layer diagram above shows the detailed diagram of the two poles, the three plates, the four plates, the five structures, and the six-piece fine electricity, the oxygen, the base, and the junction. Layered inlay hair ^ ili l I ^ ϋ 'VWJ (Please read the precautions on the back before filling in this page) This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) ", 4 326 4 A7 B7 V. Description of the invention (The capacitor structure is widely used in the product circuit, such as capacitors for storing signals in dynamic random memory (DRAM), or mixed signals.
Mai)積體電路之積分電路 (integmQ^的f容Μ ^傳統方法可能利用摻雜複晶 矽’甚至改用銘金屬來作為電容器的上、下電極板。然而， 對於銅薄料線的製程來說，傳統的電容器結構和製程卻 無法滿足其需求，因而本發明所揭露的係為一種銅製程中 的金屬電極板電容器結構和製程方法。同時本發明將以單 純的電容器製程加以詳細說明如不： 參閱第二圖’此圖中即為依照本發明形成鑲嵌之鋼 金屬層的截面示意圖。其中的基板200包括了半導體晶 圓，和形成於此半導體晶圓上的主動和被動元件等，並可 能根據需求再形成多重金屬内連線（multUevel interconnects)等，但於此囷中，只以基板2〇〇表示。而 為了隔離此多重金屬内連線’則必需於基板2〇〇最上層以 傳統的化學氣相沉積法（CVD)沉積低k值的介電材料層， 且可利用氧化梦（Si〇2)或適當摻雜的氧化砂等材料加以 形成’此介電隔離層亦稱之為内金屬介電層（IMD)。 經濟部智慧財產局員工消费合作社印製 HI' ^^^1 11^1- I ^^^1 -- - ·. - - *一^ (請先閲讀背面之注意事項_再填寫本頁) 接箸，以傳統之微影及蝕刻製程於内金屬介電層上 [ 姓刻出鎮喪區，然後以電化學沉積法（Electrochemical ιMai) Integrated circuits of integrated circuits (integmQ ^ f capacitance M ^ The traditional method may use doped polycrystalline silicon 'or even use Ming metal as the upper and lower electrode plates of the capacitor. However, for the process of copper thin wire For example, the traditional capacitor structure and manufacturing process cannot meet its requirements, so the present invention discloses a metal electrode plate capacitor structure and manufacturing method in a copper manufacturing process. At the same time, the present invention will be described in detail with a simple capacitor manufacturing process. No: Refer to the second figure, 'This figure is a schematic cross-sectional view of a steel metal layer formed in accordance with the present invention. The substrate 200 includes a semiconductor wafer, and active and passive components formed on the semiconductor wafer. Multiple metal interconnects (multUevel interconnects), etc. may be formed according to requirements, but in this case, it is only represented by the substrate 200. In order to isolate this multiple metal interconnects, it must be at the top of the substrate 200 A low-k dielectric material layer is deposited by conventional chemical vapor deposition (CVD), and materials such as oxide dream (SiO2) or appropriately doped oxide sand can be used. In order to form 'this dielectric isolation layer is also referred to as the inner metal dielectric layer (IMD). Printed HI by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ^^^ 1 11 ^ 1- I ^^^ 1--· .--* 一 ^ (Please read the notes on the back _ then fill out this page) Then, use the traditional lithography and etching process on the inner metal dielectric layer. 2. deposition method
Deposition, ECD)或DC磁控濺鍍法進行鋼金屬區210的沉 I 積。於此圖中，為了容易說明起見，並未顯示出铜金屬區 本紙張尺度適用中國國家標车（CNS > A4規格（2丨0X29?公釐） Γ »4326 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（） 210和底層之金屬層的連接插塞。當銅金屬填入鑲嵌區之 後’可利用化學機械研磨法（CMP)加以全面平坦化，並以氧 化梦之内金屬介電層作為研磨之終點。 參閲第三圖，此圖所顯示的係為依照本發明於基板 和銅金屬區之上形成堆疊層結構的截面示意圖。當上述之 鎮後銅金屬區210形成之後’接著以例如磁控直流濺鍍的 方式來沉積第一層氮化钽金屬層（TaN)22〇，此氮化钽金屬 層220為一種阻障層（barrier iayer)材料，為避免銅金屬和 後績氧化鑛層之間的作用’因而以阻障層加以隔離，並可 增加後續鍍層之黏附性，而此氮化鈕阻障層亦可由氮化鈕/ 组所組成。於本發明中，此阻障層220之厚度約在500-1500 埃左右’並可視需要而改變。至於其它適合形成阻障層之 過渡金屬材料如氮化鈦（TiN)等亦可加以利用，敗化鈦更常 和欽金屬一起搭配而以鈦/氮化鈦的形式出現。 然後，再於阻障層220之上沉積一層薄的介電層材 料230。此介電層230的厚度最好在4〇到ι〇〇埃之間，且 由南介電常數的材料所組成。例如，此介電層23〇可由氧 化妙-氤化矽（ON)層或氧化矽-氮化矽-氡化矽（Ονο)層所組 成°另外1具有高介電常數的材料如Ta2〇5或BaTi03亦可 作為此介電層材料。此較薄或高介電常數的介電層23〇將 可增加儲存的電容值。 9 本紙張AM财蘇^料（CNS ) A4· ( 21Gx297公着 - - - — ^^^1 ^in n^i I - I V&T I— ^^^1 m >1^ ^^^1 - 牙 、va (請先聞讀背面之注項_再填寫本頁) ΓΡ4326 41 si 經濟部智慧財產局員工消費合作社印製 五、發明説明（） 於介電層230形成之後，緊接著再沉積鋁金屬層或 第二層阻障層240，此鋁金屬或第二層阻障層240亦可由 磁控直流濺鍍法形成，厚度亦約在500-1500埃左右，並視 需求而調整。但若由阻障層作為上電極板之金屬層時，將 不需要額外的反應室來濺鍍沉積鋁金屬，因而將可節省製 造成本。同時此阻障層240亦可由氮化鈕（TaN)、氮化钽/ 钽（TaN/Ta)、氮化鈦（TiN)、或氮化鈦/鈦（TiN/Ti)等過渡金 屬其中之一所形成。由於後讀之電容器上電極板亦使用銅 金屬製程’此阻障層240亦可做為增加黏附性友隔離性的 金屬層材料。 參閱第四圖’此圖所示係依照本發明蝕刻堆疊層及 沉積介電層之截面示意圖。當上述之阻障層/介電層/阻障層 堆疊形成之後，接著以非等向性蝕刻技術例如反應性離子 蝕刻法（RIE)的乾蝕刻技術將此堆疊層蝕刻，且可利用含氣 或含氣之電漿來執行’並以底層之銅金屬作為蝕刻終止 層。然後再以例如電漿增強化學氣相沉積法（PECVD)沉積 一層氮化矽層250於基板200和堆疊層之上，且厚度維持 約5 00-15 00埃左右。之後，於此氮化矽層250之上沉積一 層低k值介電材料260，例如旋塗式玻璃（SOG)材料等。於 一實施例中，此低k值的介電材料層厚度約在2000到8000 埃左右，且為了避免後續的微影及蝕刻製程影響到底下的 元件，必需將此介電層加以固化以防止水份的侵入並可將 SOG薄膜上的醇類或酮類等有機溶劑移除。若是以化學氣 (請先閏讀背面之注意事項，再填寫本頁) 衣·Deposition (ECD) or DC magnetron sputtering is used to deposit the steel product 210. In this figure, for ease of illustration, it is not shown that the paper size of the copper metal area is applicable to the Chinese national standard car (CNS > A4 specification (2 丨 0X29? Mm) Γ »4326 A7 B7 Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the employee consumer cooperative. 5. Description of the invention () 210 and the plug of the underlying metal layer. After the copper metal is filled into the mosaic area, it can be fully flattened by chemical mechanical polishing (CMP) and oxidized by dreams. The inner metal dielectric layer is used as the end point of grinding. Referring to the third figure, this figure shows a schematic cross-sectional view of a stacked layer structure formed on a substrate and a copper metal region according to the present invention. After the above-mentioned copper metal region 210 After the formation ', the first tantalum nitride metal layer (TaN) 22 is deposited by, for example, magnetron DC sputtering. The tantalum nitride metal layer 220 is a barrier iayer material, in order to avoid copper The role between the metal and the later oxide ore layer is thus separated by a barrier layer, and the adhesion of subsequent plating can be increased, and this nitride button barrier layer can also be composed of a nitride button / group. In the present invention In this The thickness of the barrier layer 220 is about 500-1500 Angstroms' and can be changed as needed. As for other transition metal materials suitable for forming the barrier layer, such as titanium nitride (TiN), etc., it can be used. Metals come together in the form of titanium / titanium nitride. Then, a thin dielectric layer material 230 is deposited on the barrier layer 220. The thickness of the dielectric layer 230 is preferably 40 to ι〇〇 Between Angstroms and composed of a material having a dielectric constant of South. For example, the dielectric layer 23 may be formed by a silicon oxide-silicon nitride (ON) layer or a silicon oxide-silicon nitride-silicon nitride (0νο) layer. Composition ° In addition, a material with a high dielectric constant such as Ta205 or BaTi03 can also be used as the material of this dielectric layer. The thinner or high dielectric constant dielectric layer 23 will increase the storage capacitance value. 9 Paper AM Cai Su ^ material (CNS) A4 · (21Gx297)----^^^ 1 ^ in n ^ i I-I V & TI— ^^^ 1 m > 1 ^ ^^^ 1-Tooth , Va (please read the note on the back _ then fill out this page) ΓΡ4326 41 si Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () Formed on the dielectric layer 230 Then, an aluminum metal layer or a second barrier layer 240 is deposited next. The aluminum metal or the second barrier layer 240 can also be formed by a magnetron DC sputtering method, and the thickness is also about 500-1500 angstroms. Adjust according to requirements. However, if the barrier layer is used as the metal layer of the upper electrode plate, no additional reaction chamber is needed to deposit and deposit aluminum metal, so the manufacturing cost can be saved. At the same time, the barrier layer 240 can also be made of nitrogen. It is formed by one of transition metals such as chemical button (TaN), tantalum nitride / tantalum (TaN / Ta), titanium nitride (TiN), or titanium nitride / titanium (TiN / Ti). Since the upper electrode plate of the capacitor read later also uses a copper metal process, the barrier layer 240 can also be used as a metal layer material for increasing adhesion and isolation. Refer to the fourth figure ', which shows a schematic cross-sectional view of an etched stacked layer and a deposited dielectric layer according to the present invention. After the above barrier layer / dielectric layer / barrier layer stack is formed, the stack layer is then etched by an anisotropic etching technique such as a reactive ion etching (RIE) dry etching technique. Or a gas-containing plasma to perform the 'and use the underlying copper metal as an etch stop layer. A silicon nitride layer 250 is then deposited on the substrate 200 and the stacked layers by, for example, plasma enhanced chemical vapor deposition (PECVD), and the thickness is maintained at about 5 00-15 00 angstroms. Thereafter, a layer of low-k dielectric material 260, such as a spin-on-glass (SOG) material, is deposited on the silicon nitride layer 250. In one embodiment, the thickness of the low-k dielectric material layer is about 2000 to 8000 angstroms. In order to prevent subsequent lithography and etching processes from affecting the underlying components, the dielectric layer must be cured to prevent The intrusion of water can remove organic solvents such as alcohols and ketones on the SOG film. If it is chemical gas (Please read the precautions on the back before filling out this page)
、1T 本紙張尺度適用中國國家標準（CNS ) Α4规格（210Χ297公釐） ®432 6 4 7 1 A7 -—_____B7 五、發明説明（） 相沉積法（CVD)來沉積此介電材料時，可能要選擇性的加上 化學機械研磨（CMP)以便得到平坦化的外觀。 參閱第五圖’此圊為依照本發明形成雙層鑲嵌結構 之介電層的截面示意圖β當低k值介電層260形成之後， 接著可利用例如電漿增強化學氣相沉積法（PECVD)於其上 沉積一層氮化矽（Si 3>J4)層270。此氮化矽層270係做為底 層之介電層260的杜刻硬罩幕，且於一實施例中，將形成 約500到1 500埃左右的厚度。 接著，以傳統之微影和蝕刻技術於氮化矽層270之 上形成围案化之光阻層（未顯示於圖中）並曝露出和底層接 觸區對準的區域，再以此光阻層作為蝕刻罩幕，以非等向 性蝕刻法而形成氮化矽層270之接觸開口。 經濟部智慧財產局員工消費合作社印製 -I S·-1- - -1 -1^1 ^^1 I I—-I 1 S -- (請先閱讀背面之注再填寫本頁) 當氮化矽層270之開口形成之後，先以乾式及濕式兩 種方法將此圖案化光阻層剝離，再利用傳統的化學氣相沉 積法或旋塗式玻璃於氮化矽層270和其接觸開口之上形成 第二層的低k值介電材料層280。此介電層280的厚度也 約在2000到8000埃左右。 參閱第六圖，此圖係依照本發明完成銅金屬結構之電 容器的截面示意圖。當低k值的介電層260和280沉積之 後，接著於介電層280之上沉積第二個圖案化光阻層（未顯 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐} 經濟部智慧財痩局員工消費合作社印製 Γ 14326 4 1 Α7 __________Β7 五、發明説明（） 示於圖中），並曝露出底層之雙層鑲嵌區域。然後以此光阻 層作為蝕刻罩幕，進行雙層鑲嵌區的蝕刻。而要蝕刻底層 的氧化矽層或氮化矽層，可利用含有氟化碳之電漿如chF3 或C^6' CsFs等氣體，以提供碳原子和氟原子的反應氣體。 基本上由於氮化矽層之Si-N鍵結強度介於Si_〇和si_si之 間，因而以含氟氣體來蝕刻氮化矽層將遭遇蝕刻選擇性較 差的情形，然而藉著適當氣體組成的控制，亦可將其選擇 比提昇到可令人接受的程度。 於進行此雙層鑲嵌區的非等向性蝕刻時，介電層28〇 係以最上層的圖案化光阻層作為蝕刻罩幕，並以氮化矽層 270作為蝕刻終止層’而介電層26〇則以圖案化的氮化矽 層2 70作為蝕刻罩幕，並以底層之氮化矽層25〇作為蝕刻 終止層。 當雙層鑲嵌結構形成之後，以例如電化學沉積方法形 成鋼金屬而填入此雙層鑲嵌區中。而在此沉積程序令，下 電極板將由標號3 00之銅金屬雙層鑲嵌結構連接到最上層 並與其它的電路結構互相連接，而上電極板則由標號29〇 之銅金屬雙層鑲嵌結構連接到上層與其它電路連接而完成 本發明之電容器之製作。 經由本發明之銅製程中的電容器結構和製程方法將可 適用於記憶體中的電容器或混合信號中的電容器等。當以 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） n ^^^1 ^^^1 I ml nn n^i (锖先聞讀背面之注意事項，再填寫本頁) 經濟部智慧財產局員工消費合作社印製 r »4326 4 ^ β77五、發明説明（） 氮化鈕等阻陣層作為銅製程之界面層時，由於氮化鈕對於 銅金屬具高黏附性，且高介電材料的氧化物具極佳的熱穩 定性，因而以氮化鈕作為電容器之下電極板將可改善氧化 物/氮化钮/銅金屬堆疊之黏附性。而氮化组阻障層更可避免 銅金屬的擴散作用。 另外，電容器之上電極板亦可由氮化钽阻障層或鋁金 屬層加以形成，但若由和下電極板相同的阻障層材料時， 將可免除額外的反應室來沉積鋁金屬，以節省成本。 以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之申請專利範圍；凡其它未脫離本發明所揭示之 精神下所完成之等效改變或修飾，均應包含在下述之申請 專利範圍内。 —'.^^1· ^^1· _ _ - ^ i ^ϋ· ^^^1 I ^^^1 ml l^i 1. ^^^1J-6J (請先閲讀背面之注$項.再填寫本頁) 13 本紙張尺度適用中國國家梯準（CNS ) A4規格（210X297公釐）、 1T This paper size applies Chinese National Standard (CNS) A4 specification (210 × 297 mm) ®432 6 4 7 1 A7 -——_____ B7 V. Description of the invention () When depositing this dielectric material by phase deposition (CVD), it is possible Chemical mechanical polishing (CMP) is optionally added to obtain a flattened appearance. Refer to the fifth figure, 'This is a schematic cross-sectional view of a dielectric layer with a double-layered damascene structure formed according to the present invention. Β After the low-k dielectric layer 260 is formed, then, for example, plasma enhanced chemical vapor deposition (PECVD) can be used. A silicon nitride (Si 3> J4) layer 270 is deposited thereon. The silicon nitride layer 270 is a hard mask of the dielectric layer 260 as a bottom layer, and in one embodiment, a thickness of about 500 to about 1 500 angstroms will be formed. Next, a conventional photolithography and etching technique is used to form a masked photoresist layer (not shown) on the silicon nitride layer 270, and the area aligned with the underlying contact area is exposed, and then the photoresist is used. The layer is used as an etching mask, and a contact opening of the silicon nitride layer 270 is formed by an anisotropic etching method. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs-IS · -1---1 -1 ^ 1 ^^ 1 II—-I 1 S-(Please read the note on the back before filling this page) When silicon nitride After the opening of the layer 270 is formed, the patterned photoresist layer is peeled off by two methods, dry and wet, and then the conventional chemical vapor deposition method or spin-on glass is used to contact the silicon nitride layer 270 and the opening. A second layer of low-k dielectric material layer 280 is formed thereon. The thickness of this dielectric layer 280 is also about 2000 to 8000 angstroms. Refer to the sixth figure, which is a schematic cross-sectional view of a capacitor with a copper metal structure completed according to the present invention. After the low-k dielectric layers 260 and 280 are deposited, a second patterned photoresist layer is then deposited on the dielectric layer 280 (this paper size is not applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) } Printed by the Consumer Cooperatives of the Ministry of Economy ’s Smart Finance Bureau Γ 14326 4 1 Α7 __________ Β7 V. Description of the Invention () (shown in the figure), and expose the double-layered mosaic area on the bottom. Then use the photoresist layer as an etching mask To etch the double-layer damascene area. To etch the underlying silicon oxide layer or silicon nitride layer, a plasma containing carbon fluoride such as chF3 or C ^ 6 'CsFs and other gases can be used to provide carbon and fluorine atoms Since the Si-N bonding strength of the silicon nitride layer is between Si_0 and si_si, etching the silicon nitride layer with a fluorine-containing gas will encounter a situation of poor etching selectivity. With the control of proper gas composition, the selection ratio can also be increased to an acceptable level. During the anisotropic etching of this double-layer damascene region, the dielectric layer 28 is patterned with the uppermost patterned light. The resist acts as an etch mask and The silicon layer 270 is used as an etch stop layer, and the dielectric layer 26 is a patterned silicon nitride layer 2 70 as an etch mask, and the bottom silicon nitride layer 25 is used as an etch stop layer. When the double-layer mosaic structure After the formation, a steel metal is formed by, for example, an electrochemical deposition method to fill the double-layered mosaic area. In this deposition procedure, the lower electrode plate will be connected to the uppermost layer by a copper-metal double-layered mosaic structure numbered 3 00 and other layers. The circuit structures of the capacitors are connected to each other, and the upper electrode plate is connected to the upper layer with a copper metal double-layer mosaic structure numbered 29 and connected to other circuits to complete the production of the capacitor of the present invention. The capacitor structure and manufacturing process in the copper process of the present invention The method will be applicable to capacitors in memory or capacitors in mixed signals. When this paper is used, the Chinese National Standard (CNS) A4 specification (210X297 mm) is applicable. N ^^^ 1 ^^^ 1 I ml nn n ^ i (锖 First read the notes on the back, then fill out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs r »4326 4 ^ β77 V. Description of the invention () Nitriding buttons and other barrier layers are made of copper In the interface layer, because the nitride button has high adhesion to copper metal, and the oxide of the high dielectric material has excellent thermal stability, using the nitride button as the electrode plate under the capacitor will improve the oxide / The adhesion of the nitride button / copper metal stack. The nitride group barrier layer can avoid the diffusion of copper metal. In addition, the electrode plate on the capacitor can also be formed by a tantalum nitride barrier layer or an aluminum metal layer, but If the same barrier layer material as the lower electrode plate is used, it is possible to dispense with an additional reaction chamber to deposit aluminum metal to save costs. The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. The scope of patent application; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the scope of patent application described below. -'. ^^ 1 · ^^ 1 · _ _-^ i ^ ϋ · ^^^ 1 I ^^^ 1 ml l ^ i 1. ^^^ 1J-6J (Please read the note on the back first. (Fill in this page again) 13 This paper size is applicable to China National Standard (CNS) A4 (210X297 mm)