TW490746B - Formation method of ultra-shallow junction - Google Patents

Formation method of ultra-shallow junction Download PDF

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TW490746B
TW490746B TW090107850A TW90107850A TW490746B TW 490746 B TW490746 B TW 490746B TW 090107850 A TW090107850 A TW 090107850A TW 90107850 A TW90107850 A TW 90107850A TW 490746 B TW490746 B TW 490746B
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Jr-Shiang Jeng
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United Microelectronics Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2658Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Description

490746 7115twf.doc/〇〇6 A7 __B7 五 經濟邨智慧財產局員工消費合作杜印製 發明說明(I ) 本發明是有關一種半導體製程(Semiconductor Process) ’且特別是有關一種形成/超淺接面(Ultra-shallow Junction)的方法。 隨著半導體元件的尺寸日益減小,金氧半電晶體(MOS Transistor)的源/汲極接面(s/D Junction)的深度亦須持續減 少’以防止短通道效應(Short Channel Effect)之產生,並降 低擊穿電流(Punch-through Current)。另外,深度減少後源/ 汲極接面之表層的摻雜濃度則需持續增加,以免源/汲極接 面的電阻因深度減小而增加過多,以致影響元件的操作效 率。 爲解決上述問題,一般的方法係採用劑量較高的離子 植入製程。然而,由於以高劑量植入離子於結晶態之矽基 底表面時會破壞接面輪廓(Junction Profile),所以其接面漏 電流(Junction Leakage)會大幅增加。再者,由於先進製程 中源/汲極接面表層的摻雜濃度已逼進摻質在矽基底中的飽 和固態溶解度(Saturated Solid Solubility),故此法將不再可 行。 爲此,前人提出一種採用低溫固相磊晶重長原理(Low Temperature Solid Phase Epitaxial Regrowth,LTSPER)的超 淺接面製程以解決上述問題,此方法係先植入矽離子以非 晶化(Amorphize)矽基底的表層,然後再於非晶矽層中植入 摻質離子。接著進行一低溫固相磊晶重長製程以使非晶化 的部分再結晶,並活化植入之摻質離子,而得一超淺接面。 此種低溫固相磊晶重長方法可以得到較佳的接面輪廓,進 3 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 490746 7115twf.doc/006 A/ __B7______ 五、發明說明(2) 而減少超淺接面的漏電流;並可使超淺接面具有過飽合的 摻質,以降低其電阻。 雖然採用低溫固相磊晶重長原理所形成之超淺接面具 有上述優點,但對硼摻雜之超淺接面而言,其在某些700T 以上的中後段製程中卻會產生摻質去活性化(Deactivation) 的問題,使元件之品質大爲降低。 本發明提出一種形成超淺接面的方法以解上述問題, 其步驟如下:首先非晶化矽基底之表層以形成一非晶矽 層,再於非晶矽層中植入硼離子,然後於非晶矽層中植入 鍺(Germanium,Ge)離子。接著進行一低溫固相磊晶重長步 驟以使非晶矽層再結晶,並活化植入之硼離子,而在基底 表層形成一超淺接面。 本發明中的鍺離子植入步驟可將硼摻質的去活性化溫 度提高至700°C以上,故在進行7〇〇。(:的中後段製程時, 超淺接面中的硼摻質不會發生去活性化的現象。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂, 下文特舉一較佳實施例,並配合所附圖式,作詳細說明如 下: 圖式之簡單說明: 第lArlD圖所繪示爲本發明較佳實施例之形成超淺接 面的方法。 圖式之標號說明: 1〇〇 ··基底 110 :閘極 120 :矽離子 130 ··非晶矽層 4 ^紙張尺度適用中國國家標準(CNS)A‘l規^(2ΐ〇_χ 297公餐)' (請先閱讀背面之注意‘ · .1 n ϋ ϋ H ϋ 一-0*· I 1 ϋ I ϋ >1 I I » 事填办 ^寫本頁) S齊郢暂慧材查咼員X.消費合阼fi-印製 490746 7ll5twf.doc/006 A/ ___B7___ 五、發明說明(^) 140 :硼離子 150 :硼摻雜區 160 :鍺離子 170 :超淺接面 較佳實施例說明 請參照第1A圖,首先提供基底100,其上已形成有一 閘極110。接著以閘極110爲罩幕,在暴露出之基底100 表層中植入矽離子120,以形成非晶矽層130,其中矽離 子120的植入劑量例如是介於5xl014/cm2至2xl015/cm2之 間,且植入能量例如約爲30 Kev。另外,此步驟中非晶化 矽基底表層的方法不限於矽離子植入,氬離子(Ar+)植入亦 可用來非晶化矽基底的表層。 請參照第1B圖,接著在非晶矽層130中植入硼離子 140,以形成硼摻雜區150,其中硼離子140的植入劑量例 如是介於5xl014/cm2至8xl015/cm2之間,且硼離子140的 植入能量例如約爲5 Kev,而5 KeV之植入能量大約可以 得到深度200人〜400人的超淺接面。另外,此步驟中亦可改 植入二氟化硼離子(BF2+)以形成硼摻雜區150,不過二氟化 硼離子的植入能量需高於硼離子,以達到相同的植入深 度。 請參照第1C圖,接著於硼摻雜區15〇中植入鍺離子 160,其中鍺離子160的植入劑量例如是介於i〇H/cm2至 6xl014/cm2之間,且植入能量例如是介於〇.5Kev至2.0Kev 之間。此處鍺離子植入的目的係爲降低晶格結構中的應力 (Stress),以延緩硼摻質的去活性化反應。 請參照第1D圖’然後進行一低溫固相磊晶重長步驟 5 本紙張尺度適用中國國家標準(CNSM4規格(210 X 297公 (請先閱讀背面之注意事填寫本頁)
P
•裝--------訂--------I # 490746 7115twf.doc/006 A7 B7 五、發明說明(年) (LTSPER)以使非晶矽層130再結晶(再結晶後性質與基底 100相同,故圖式中不再繪出),並活化硼摻雜區150中的 硼摻質,而在基底100表層形成超淺接面170,此低溫固 相磊晶重長步驟的溫度例如是介於500°C至600。(:之間。 如上所述,由於本發明係先在硼摻雜區150中植入鍺 離子,再進行後續的低溫固相磊晶重長步驟(LTSPER)以形 成超淺接面,所以本發明不但具有減少超淺接面之漏電流 與電阻値的優點,還可以將硼摻質的去活性化溫度提高至 700T以上。因此,在進行700T以上的中後段製程時, 超淺接面中的硼摻質不會發生去活性化的現象,而能使元 件的品質保持穩定。 雖然本發明已以一較佳實施例揭露如上,然其並非用 以限定本發明,任何熟習此技藝者,在不脫離本發明之精 神和範圍內,當可.作各種之更動與潤飾,因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 請 先 閱 讀 背
I 再, 本 · 頁I I I I I I I 訂 6 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公餐)

Claims (1)

  1. 490746 7115twf.doc/006 A8 B8 C8 D8 經濟部智慧財產局員工消費合作社印剔衣 六、申請專利範圍 1. 一種形成超淺接面的方法,包括下列步驟: 提供一基底; 非晶化該基底之表層以形成一非晶砂層; 在該非晶矽層中植入硼離子; 於該非晶矽層中植入鍺離子;以及 進行一低溫固相磊晶重長步驟(LTSPER)以使該非晶砂 層再結晶,並活化植入之硼摻質,而在該基底表層形成一 超淺接面。 2. 如申請專利範圍第1項所述之方法,其中鍺離子的 植入劑量介於l〇14/cm2至6xl014/cm2之間。 3. 如申請專利範圍第1項所述之方法,其中鍺離子的 植入能量介於0.5 Kev至2.0 Kev之間。 4. 如申請專利範圍第1項所述之方法,其中硼離子的 植入劑量介於5xl014/cm2至8xl015/cm2之間。 5. 如申請專利範圍第1項所述之方法,其中硼離子的 植入能量約爲5 Kev。 6. 如申請專利範圍第5項所述之方法,其中該超淺接 面的深度介於200A至400A之間。 7. 如申請專利範圍第1項所述之方法,其中該低溫固 相磊晶重長步驟的溫度介於500。(:至600T之間。 8. 如申請專利範圍第1項所述之方法,其中非晶化該 基底之表層的方法包括植入矽離子。 9. 如申請專利範圍第8項所述之方法,其中矽離子的 植入劑量介於5xl014/cm2至2xl015/cm2之間。 (請先閱讀背面之注意事β填寫本頁) Ρ 裝 訂: 線! 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公t ) 490746 7115twf.doc/006 B8 經濟部智慧財產局員工消費合作社印制农 六、申請專利範圍 10·如申請專利範圍第8項所述之方法,其中矽離子的 植入能量約爲30 Kev。 11.如申請專利範圍第1項所述之方法,其中非晶化該 基底之表層的方法包括植入氬離子。 12·—種形成超淺接面的方法,包括下列步驟·· 提供一基底; 非晶化該基底之表層以形成一非晶矽層; 在該非晶矽層中植入二氟化硼離子(BF2+); 於該非晶矽層中植入鍺離子;以及 進行一低溫固相磊晶重長步驟(LTSPER)以使該非晶矽 層再結晶,並活化植入之二氟化硼摻質,而在該基底表層 形成一超淺接面。 13. 如申請專利範圍第12項所述之方法,其中鍺離子 的植入劑量介於1014/cm2至6xl014/cm2之間。 14. 如申請專利範圍第12項所述之方法,其中鍺離子 的植入能量介於0.5 Kev至2.0 Kev之間。 15. 如申請專利範圍第12項所述之方法,其中二氟化 硼離子的植入劑量介於5xl014/cm2至8xl〇15/cm2之間。 16. 如申請專利範圍第12項所述之方法’其中該低溫 固相磊晶霉長步驟的溫度介於500。(:至600°C之間。 17. 如申請專利範圍第12項所述之方法’其中非晶化 該基底之表層的方法包括植入矽離子。 18. 如申請專利範圍第17項所述之方法’其中砂離子 的植入劑量介於5xl014/cm2至2xl015/cm2之間。 8 本紙張尺度適用中國國家標準(CNS)A4規格(2]0 X 297公f ) (請先閱讀背面之注意事3填寫本頁) i裝 訂·. 線! 490746 7115twf.doc/006 A8 B8 C8 D8 六、申請專利範圍 19. 如申請專利範圍第17項所述之方法 的植入能量約爲30 Kev。 20. 如申請專利範圍第12項所述之方法 該基底之表層的方法包括植入氬離子。 其中矽離子 其中非晶化 (請先閱讀背面之注意事填寫本頁) P 裝 訂. 線! 經濟部智慧財產局員工消費合作社印^^ 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)
TW090107850A 2001-04-02 2001-04-02 Formation method of ultra-shallow junction TW490746B (en)

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JP3746246B2 (ja) * 2002-04-16 2006-02-15 株式会社東芝 半導体装置の製造方法
EP1697979A2 (en) * 2003-12-22 2006-09-06 Koninklijke Philips Electronics N.V. A semiconductor substrate with solid phase epitaxial regrowth with reduced depth of doping profile and method of producing same
CN1930663A (zh) * 2004-03-15 2007-03-14 皇家飞利浦电子股份有限公司 制造半导体器件的方法和用这种方法获得的半导体器件
US8648412B1 (en) 2012-06-04 2014-02-11 Semiconductor Components Industries, Llc Trench power field effect transistor device and method

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