486790 五、發明說明（1 【發明領域】 本發明係有關一種具晶片座之半導體封裝件，尤指 一種於晶片座底面設置導引溝之半導體封裝件。 【發明背景】 一般傳統半導體封裝件之結構，係包括一半導體晶 片，一具有晶片座以及多數導腳之導線架，一黏接該晶片 至晶片座之銀膠，多數金線以及包覆該半導體晶片與金線 之封裝膠體。其半導體晶片、導線架、銀膠以及形成封裝 膠體之封裝樹脂均係不同材料構成，故具有不同之熱膨脹 係數。 然而，在半導體元件之封裝製程中，上片（Die Attach)、模壓（Molding)以及長烤（p〇st M〇M CuHng) 經濟部智慧財產局員工消費合作社印製 等步驟須於150至175°C之高溫環境下進行，晶片 '導線 架、銀膠與封裝樹脂各具有不同之熱膨脹係數，因而於受 熱冷卻的過程中產生不等之熱應力變化，故而造成封裝件 成品製成後，晶片與銀膠、銀膠與晶片座接觸面之間產生 龜裂（Crack)或脫層（Delaminatl〇n)等現象進而降低 封裝件之品質可靠性。 另一方面，為因應目前電子產品高速化及多功能化 之發展潮流，半導體晶片無不朝向高度集積化、大記憶容 量之方向開發，為符合半導體晶片容量擴充之需要，晶片 須朝向大型化邁進，因此，隨著晶片尺寸的提昇，晶片座 亦隨之增大，且塗覆其上之銀膠量亦相對增加，其熱應力 效應之影響更鉅，遂使成型之半導體封裝件產品可靠性劣 16260 ------------------裝.！ (請先閱讀背面之注意事項I®寫本頁) 線· ‘紙張尺度適w τ關家標準（CNS)A4規格（2W x 297公着）- 486790 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（2 ) 4匕日益明顯。 上述問題解決之道之一，係改變晶片座之設計，冀 能降低晶片、銀膠以及晶片座間之熱應力效應。美國專利 第5,233,222號案即揭露一種具有梯形截面貫穿孔之晶片 座之半導體封裝件。如第1圖所示，該半導體封裝件丨之 晶片座11中央開設一截面呈梯形之矩形貫穿孔俾以構成 一晶片座内框17，冀藉此減少晶片座n與半導體晶片1〇 接觸面積並節省銀膠14使用量，故而降低晶片1〇與銀膠 14以及晶片座u間之熱應力。同時，配合參閱第2圖， 相較於習知窗型晶片座n，（ wind〇w Pad，意指晶片座中 央係開設有一貫穿孔俾使晶片座整體形似窗框）進行膠體 封裝時，晶片座内框17,係與樹脂模流19,流動方向形成 死角（如圖中虛線所示）而使封裝件產生氣洞（v〇ids)， 該項技術（如第1圖所示）揭示之封裝件其晶片座u具 有一梯形截面的晶片座内框17，藉由該晶片座内框17提 供之斜面1 7 1俾利順應模流方向減少氣洞形成。 惟此項技術内容揭露之晶片座係於導線架初形成 時，藉由沖壓（Stamping)或打洞（Punching)等方法擠 壓晶片座内框17俾以形成斜面171並推除多餘渣料172, 如第3圖所示。然而此一作業方式將導致渣料172殘留於 晶片座11表面俾使該晶片座n之平面度下降，嚴重阻礙 後續上片作業之進行。是以，晶片座内框17採用斜面設 計固然得以順應模流方向（如第4圖箭頭所示）減少氣洞 產生，但往往受模流流速阻滞等複雜因素影響使得流經晶 --------------裝--- (請先閱讀背面之注意事項寫本頁) . •線- 486790 A7 五、發明說明（3 ) 片座内框17角端位置170之封裝樹脂（未圖示）極易包 埋空氣（Air Trap )，導致封裝件進行後續製程之溫度循 環時發生信賴性脫層等問題。 【發明概述】 本發明之主要目的即在提供一種藉由窗型晶片座 (Window Pad)底面蝕刻有複數條導引溝，俾以減少模 壓製程中溶融封裝樹脂包覆晶片座内框時之模流阻力，進 而降低封裝製品產生氣洞可能性之半導體封裝件。 本發明之另一主要目的係提供一種利用簡易蝕刻製 法於自型片座底面開设複數條導引溝，俾以降低製程複 雜性並且縮減封裝成本之半導體封裝件。 本發明之再一目的係提供一種減少晶片座與銀膠及 半導體晶片間之接觸面積，藉以降低三者於後續製程之溫 度循環中不等之熱應力效應，故而減少封裝件發生脫層或 晶片受損等信賴性問題之半導體封裝件。 基於上述及其他目的，本發明半導體封裝件係包含： 一半導體晶片；一藉由流動性熔融封裝樹脂形成包覆該半 ，體晶片及多數金線之封裝膠體；_提供該半導體晶片黏 者其上之晶片座，該晶片座具有一頂面及一相對之底面， 並於晶片座中央處開設有一個以上之貫穿孔俾以形成一晶 片座内框，藉由該晶片座内框作為起始點，於該晶片座底 面/口著封裝樹脂模流流向向外延伸至晶片座外緣而開設成 至少一條具有適當寬度之導引溝；多數之導腳；以及，複 數條俾供該晶片與眾導腳導電連結之金線。 16260 --------------裝--- (請先閱讀背面之注意事項寫本頁) 入-a· -線· 經濟部智慧財產局員工消費合作社印製 五、發明說明（4 ) 相較於％知技術中半導體封裝件實施模壓作業時， 晶片座阻擋模流行進方向俾使擾流形成因而導致氣洞產 生本發明係於晶片座底面開設多條順應模流方向之導引 溝藉由該等導引溝提供樹脂模流一疏導路徑，降低炼融 封裝樹月日fr經晶片座時之模流阻力，、繼而減少擾流現象俾 避免氣洞發h同時，該等導引道係以技術成熟之㈣或 ’中切方式製传’無須形成斜面遂可避免擠壓作業造成逢料 殘存之疑慮，並且，該等導㈣係以晶片座内框作為起始 點開設，故可有效地改善傳統上封裝樹脂極易在晶片座内 框角端位置包埋空氣之問題。 【圖示簡單說明】 以下茲以較佳具體例配合所附圖示進一步詳述本發 明之特點及功效： 第1圖係習知具有梯形截面貫穿孔之晶片座之 體封裝件剖面示意圖； -第2圖係習知半導體封裝件實施膠體封裝之模流流486790 V. Description of the Invention (1) [Field of the Invention] The present invention relates to a semiconductor package with a wafer holder, especially a semiconductor package provided with a guide groove on the bottom surface of the wafer holder. [Background of the Invention] The general traditional semiconductor package The structure includes a semiconductor wafer, a lead frame having a wafer holder and a plurality of guide pins, a silver glue adhering the wafer to the wafer holder, most gold wires, and a packaging gel covering the semiconductor wafer and the gold wires. The chip, lead frame, silver glue, and packaging resin forming the packaging gel are all made of different materials, so they have different coefficients of thermal expansion. However, in the packaging process of semiconductor components, Die Attach, Molding, and Long Baking (p〇st M〇M CuHng) The steps of printing by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy must be performed at a high temperature of 150 to 175 ° C. The chip 'lead frame, silver glue and packaging resin each have different thermal expansions. Coefficient, resulting in unequal thermal stress changes in the process of heating and cooling, so that after the package is finished, the wafer The occurrence of cracks or delamination between the contact surface of the silver glue, the silver glue, and the wafer holder, and the like, thereby reducing the quality and reliability of the package. On the other hand, in response to the current high-speed electronic products and The development trend of multi-functions is that semiconductor wafers are all developed in the direction of high integration and large memory capacity. In order to meet the needs of semiconductor wafer capacity expansion, the wafers must move toward large-scale. Therefore, with the increase in wafer size, the wafer holder It has also increased, and the amount of silver glue applied on it has also increased. Its thermal stress effect has a greater impact, which makes the molded semiconductor package product less reliable. 16260 ---------- -------- Installation ... (Please read the precautions on the back I® first write this page) Thread · 'Paper size is suitable for τguan family standard (CNS) A4 specification (2W x 297)-486790 A7 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. The invention description (2) 4k is becoming more and more obvious. One of the solutions to the above problems is to change the design of the chip holder, in order to reduce the heat of the chip, silver glue and the chip holder. Stress effect. US patent No. 5,233,222 discloses a semiconductor package having a wafer holder with a trapezoidal cross-section through hole. As shown in FIG. 1, a rectangular through hole 俾 with a trapezoidal cross-section is formed in the center of the wafer holder 11 of the semiconductor package 丨 to form a The wafer holder inner frame 17 is intended to reduce the contact area between the wafer holder n and the semiconductor wafer 10 and save the use of the silver glue 14, so as to reduce the thermal stress between the wafer 10 and the silver glue 14 and the wafer holder u. At the same time, please refer to the cooperation Figure 2. Compared to the conventional window wafer holder n, (window pad, meaning that the center of the wafer holder is provided with a through hole (to make the wafer holder resemble a window frame as a whole) for gel packaging, the wafer holder inner frame 17 , It is the resin mold flow 19, forming a dead angle in the flow direction (as shown by the dashed line in the figure), and causing the package to generate air holes (vooids). The chip of the package disclosed by this technology (shown in Figure 1) The holder u has a wafer holder inner frame 17 with a trapezoidal cross-section, and the inclined surface 1 7 1 provided by the wafer holder inner frame 17 conforms to the direction of the mold flow to reduce the formation of air holes. However, the wafer holder disclosed in this technical content is when the lead frame is initially formed, and the inner frame 17 of the wafer holder is extruded by stamping or punching to form a slope 171 and remove excess residue 172. As shown in Figure 3. However, this method of operation will cause the residue 172 to remain on the surface of the wafer holder 11, thereby reducing the flatness of the wafer holder n, which seriously hinders the subsequent loading operation. Therefore, the slanted design of the inner frame 17 of the wafer holder can conform to the direction of the mold flow (as shown by the arrow in Figure 4) to reduce the generation of air holes, but it is often affected by complex factors such as the mold flow velocity blockage that causes the flow through the crystal --- ----------- Install --- (Please read the precautions on the back to write this page first). • Cable-486790 A7 V. Description of the invention (3) The 17 corners of the inner frame of the film holder are located at 170 The encapsulation resin (not shown) is easily entrapped with air (Air Trap), which causes problems such as reliability delamination during the temperature cycle of the subsequent process of the package. [Summary of the Invention] The main purpose of the present invention is to provide a mold with a plurality of guide grooves etched on the bottom surface of the window pad, so as to reduce the mold when the inner frame of the wafer holder is covered by the molten packaging resin during the molding process. Flow resistance, thereby reducing the possibility of air holes in the packaged semiconductor package. Another main object of the present invention is to provide a semiconductor package using a simple etching method to open a plurality of guide grooves on the bottom surface of a self-shaped chip holder to reduce process complexity and packaging cost. Another object of the present invention is to provide a method for reducing the contact area between the wafer holder, the silver glue and the semiconductor wafer, so as to reduce the thermal stress effect of the three during the temperature cycle of the subsequent process, thereby reducing the occurrence of delamination or chipping of the package. Semiconductor packages with reliability issues such as damage. Based on the above and other objectives, the semiconductor package of the present invention includes: a semiconductor wafer; a packaging gel that covers the half-body wafer and most of the gold wires by a fluid melt-encapsulating resin; The wafer holder has a top surface and an opposite bottom surface, and more than one through hole 俾 is formed at the center of the wafer holder to form a wafer holder inner frame. The wafer holder inner frame is used as a starting point. Point, at the bottom surface of the wafer holder, the resin resin mold flows outward to the outer edge of the wafer holder to form at least one guide groove with an appropriate width; the majority of the guide pins; and, a plurality of bars are provided for the wafer and Gold wires that are conductively connected to the guide pins. 16260 -------------- Installation --- (Please read the precautions on the back to write this page) Enter -a · -Line · Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Description of the Invention (4) Compared with the semiconductor package in the known technology, the wafer holder blocks the mold from advancing in the direction of the die, so that turbulence is formed, which results in the formation of air holes. The invention is to open multiple compliant mold flows on the bottom surface of the wafer holder. The guide grooves in the direction provide resin mold flow and a clearing path through these guide grooves, which reduces the mold flow resistance of the melting and packaging tree moon fr through the wafer holder, thereby reducing the phenomenon of turbulence and avoiding air holes. These guides are made by the mature technology or “cut in the middle” without the need to form an inclined surface to avoid the fear of residual material caused by the extrusion operation. Moreover, these guides are based on the inner frame of the wafer holder. The starting point is opened, so it can effectively improve the problem that the traditional sealing resin is very easy to embed air in the corner position of the inner frame of the wafer holder. [Brief description of the diagram] The following is a detailed description of the features and effects of the present invention with preferred specific examples and accompanying drawings: Figure 1 is a schematic cross-sectional view of a body package of a conventional wafer holder with a trapezoidal cross-section through hole;- Figure 2 shows the mold flow of a conventional semiconductor package for colloidal packaging.
員 工 消 費 合 作 社 印 製 第6圖係沿第5圖之剖面線6-6 本紙張尺度適財國國家標準（CNS)A4規格⑵〇 X 297公愛 之剖面示意圖； 第5圖係本發明第一實施例之半導體封襞件 16260 486790 A7 五、發明說明（5 ) 第7A至7D圖係本發明第一實施例之半導 中晶片座底面導引溝之製作流程示意圖； 第8A與8B圖係本發明第二實施例之半導體封 之仰視圖及其剖面示意圖；以及， 第9A與9B圖係本發明第眚 , β弟一實施例之半導體封裝侔 之仰視圖及其剖面示意圖。 【發明詳細說明】 本發明第-實施例之半導體封裝件係以第5圖及第6 圖表示之。該半導體封裝件2包括一表面設有多數銲墊_ 之半導體晶片20;提供該晶片2〇黏著其上之晶片座2卜 其中該晶片座21底面211係開設有複數條導引溝212; 多數俾與該晶片座21共同構成一導線架22之導腳23; 以及一黏接該半導體晶片20至晶片座21之銀膠Μ ;用 以導電連接晶片20與導腳23之複數條金線乃，以及包 覆該晶片20、晶片座21、金線25與導腳23之封裝缪體 26 〇 經濟部智慧財產局員工消費合作社印製 第5圖係顯示本發明半導體封裝件之導線架底面仰 視圖，該導線架22係包含一藉由多數繫條220 ( Tie Bar) 連设於導線架22上之晶片座21以及形成於該晶片座 外圍之多數導腳23，該晶片座21係為一窗型晶片座 (Window Pad )(意指該晶片座中央係開設有一貫穿孔俾 使晶片座整體形似窗框），其具有一頂面210與一相對之 底面211，該晶片座21中央具有一面積小於該半導體晶 片20之矩形貫穿孔俾以形成一晶片座内框27，在該晶片 16260 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 4-86796— A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（6 ) 座21底面211上以該晶片座内框27各角端位置270為起 始點’沿與形成封裝膠體之封裝樹脂模流流向平行之方向 向外延伸至該晶片座21外緣，預先定義出至少一條具有 適當寬度之溝槽形成區213俾供多條導引溝212開設。 第7A至7D圖係為晶片座底面導引溝之詳細製作流 程。如第7A及7B圖所示，藉由習知之半蝕（Half_Etching) 方法於該晶片座21上預設有該等溝槽形成區（未圖示） 之晶片座2 1底面2 11塗覆一光阻劑層28，經過選擇性曝 光（Exposure)、顯影等程序，於該晶片座Η底面211之 溝槽形成區213蝕刻形成有複數條自該晶片座内框27角 端位置270平行延伸至該晶片座21外緣之導引溝212。 惟明確表示具有該等導引溝212之晶片座21的立體型態， 另以第7C圖（上視立體圖）及第7D圖（第7C圖之縱向 剖面圖）表示之。 蝕刻完成於晶片座底面211開設有多條導引溝212 之導線架22，經過上片、金線銲接等步驟，最後進行模 壓製程。此等步驟係屬習知，故在此亦不另為文贅述。然 當該半導體封裝件夾固一封裝模具（未圖示）内用以形成 一模穴（未圖示）俾供一熔融封裝樹脂注入後，樹脂模流 流入模穴（未圖示）内，原本遭受晶片座21阻擋而變大 的模流阻力，會因該等導引溝212開設方向係順應模流流 向以提供樹脂模流一疏導路徑，致使模流阻力下降因而減 夕擾μ現象之發生，使得封裝件内形成氣洞之可能性大為 降低。 # 本紙張尺度適时_雜準（cns)A4規^------ (請先閱讀背面之注意事項i 裝—— π寫本頁) . 線· 486790 A7 經濟部智慧財產局員工消費合作社印制衣 五、發明說明（7 ) 第8圖所示者係為本發明第二實施例之半導體封裝 件中，晶片座之上視圖（第8A圖）及其剖面示意圖（第 8 B圖）。該第二實施例半導體封裝件之晶片座結構大致上 同於前述第一實施例，其不同點僅在菸該實施例之晶片座 31結構係以該晶片座内框37各侧邊373之中央部作為起 始點，向外平行延伸至晶片座31外緣，蝕刻製得複數條 截面呈一半圓形之導引溝312，如第8B圖所示。除以蝕 刻方式於晶片座底面3 i i開設該等導引溝3 12之外，亦得 使用習知之沖壓方式（Stamping)沖製該等導引溝312。 第9圖係顯示本發明第三實施例半導體封裝件之晶片座上 視圖（如第9A圖所示）及其剖視圖（如第9B圖所示）。 如圖所示，該等導引溝412係以晶片座41底面411上該 晶片座内框47各角端位置47〇作為起始點，平行向外延 伸至該晶片座41外緣之角端414上，藉以習用之沖壓製 程於該晶片座41底面411沖製形成多條具有v型截面之 導引溝412,該等導引溝412之開設提供樹脂模流（未圖 示）一疏導路徑，導致封裝樹月旨（未圖示）流經晶片座内 框47時之模流阻力減低，避免擾流形成而有效防止氣洞 產生。 上述之具體實施例僅係用以詳細說明本發明之特點 及功效，而非以之限定本發明之可實施範圍，在未脫離本 發明所揭不之技術範疇與精神下，任何運用本發明所完成 之等效變更與修飾，均應仍為本發明下揭之申請專利範圍 所涵蓋。 i氏張尺度適用中國國家標準（CNS)A4規格（210 X 297公董 16260 --------I-----· I I (請先閱讀背面之注意事項寫本頁) . 線· 486790 A7 _B7 五、發明說明（8 ) 【符號標號說明】 經濟部智慧財產局員工消費合作社印製 1，2 半導體封裝件 10,20,30,40 半導體晶片 200 晶片銲墊 11，21，31，41 晶片座 210 晶片座頂面 211,311,411 晶片座底面 212,312,412 導引溝 213 溝槽形成區 414 晶片座角端 22 . 導線架 220,320,420 繫條 13,23 導腳 14,24,34,44 銀膠 15,25 金線 26 封裝膠體 19,29 樹脂模流 17,27,37,47 晶片座内框 170,270,370 角端位置 171,271 斜面 172 渣料 373 内框側邊 28 光阻劑層 14 銀膠 ----------一----裝--- (請先閱讀背面之注意事項寫本頁) .. -線· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 8 16260The 6th figure printed by the employee consumer cooperative is along the section line of the 6th figure. 6-6 This paper is a cross-sectional schematic diagram of the national standard (CNS) A4 size ⑵ × 297 public love of the country of wealth; Figure 5 is the first of the invention. Semiconductor sealing member of the embodiment 16260 486790 A7 V. Description of the invention (5) Figures 7A to 7D are schematic diagrams of the manufacturing process of the guide groove on the bottom surface of the semiconductor substrate in the first embodiment of the present invention; Figures 8A and 8B are A bottom view and a schematic cross-sectional view of a semiconductor package according to a second embodiment of the present invention; and FIGS. 9A and 9B are a bottom view and a schematic cross-sectional view of a semiconductor package 一 of a second and third embodiment of the present invention. [Detailed description of the invention] The semiconductor package of the first embodiment of the present invention is shown in FIG. 5 and FIG. 6. The semiconductor package 2 includes a semiconductor wafer 20 provided with a plurality of pads on the surface; a wafer holder 2 provided with the wafer 20 adhered thereto; wherein the bottom surface 211 of the wafer holder 21 is provided with a plurality of guide grooves 212; most俾 and the wafer base 21 together form a guide leg 23 of a lead frame 22; and a silver glue M bonding the semiconductor wafer 20 to the wafer base 21; a plurality of gold wires for electrically connecting the wafer 20 and the guide leg 23 are , And the package 26 covering the chip 20, chip holder 21, gold wire 25 and guide pin 23 〇 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Figure 5 shows the bottom surface of the lead frame of the semiconductor package of the present invention looking up In the figure, the lead frame 22 includes a wafer holder 21 connected to the lead frame 22 by a plurality of tie bars 220 and a plurality of guide pins 23 formed on the periphery of the wafer holder. The wafer holder 21 is a The window pad (Window Pad) (meaning that the center of the wafer holder is provided with a through hole to make the wafer holder resemble a window frame as a whole), which has a top surface 210 and an opposite bottom surface 211. The center of the wafer holder 21 has a Rectangular area smaller than the semiconductor wafer 20 Perforated 俾 to form a wafer holder inner frame 27. At this wafer, the paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 4-86796— A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Description of the invention (6) The base 211 of the base 21 takes the positions 270 of the corner ends of the inner frame 27 of the wafer base as the starting point, and extends outward to the wafer base in a direction parallel to the flow direction of the encapsulating resin mold forming the encapsulating gel. At the outer edge of 21, at least one groove forming region 213 having an appropriate width is defined in advance for a plurality of guide grooves 212 to be opened. Figures 7A to 7D show the detailed manufacturing process of the guide groove on the bottom surface of the wafer holder. As shown in Figs. 7A and 7B, the wafer holder 21 with the groove forming regions (not shown) preset on the wafer holder 21 by the conventional Half_Etching method is coated with 1 The photoresist layer 28 is etched and formed in the groove formation area 213 of the bottom surface 211 of the wafer holder through selective exposure (exposure), development and other processes, and a plurality of strips are extended in parallel from the corner end position 270 of the inner frame 27 of the wafer holder to A guiding groove 212 on the outer edge of the wafer holder 21. However, the three-dimensional form of the wafer holder 21 having the guide grooves 212 is clearly indicated, and it is also shown in FIG. 7C (upper perspective view) and FIG. 7D (longitudinal sectional view in FIG. 7C). After the etching is completed, a lead frame 22 provided with a plurality of guide grooves 212 is formed on the bottom surface 211 of the wafer holder. After the steps such as wafer loading, gold wire welding and the like, the molding process is finally performed. These steps are known, so they are not described in detail here. However, when the semiconductor package is clamped in a packaging mold (not shown) to form a cavity (not shown). After a molten packaging resin is injected, the resin mold flow flows into the cavity (not shown). The mold flow resistance that was originally blocked by the wafer seat 21 will be caused by the opening direction of these guide grooves 212 in accordance with the mold flow direction to provide a resin mold flow to clear the path, which will reduce the mold flow resistance and reduce the disturbance μ phenomenon. Occurs, greatly reducing the possibility of forming air holes in the package. # This paper size is timely _ miscellaneous (cns) A4 rules ^ ------ (please read the precautions on the back of the paper-π write this page). Thread · 486790 A7 Employees of the Intellectual Property Bureau of the Ministry of Economy Consumption Cooperative printed clothing V. Description of the invention (7) The figure 8 is a top view (Figure 8A) and a schematic cross-sectional view (Figure 8B) of the wafer holder in the semiconductor package of the second embodiment of the present invention. ). The structure of the wafer holder of the semiconductor package of the second embodiment is substantially the same as that of the foregoing first embodiment, and the difference is only that the structure of the wafer holder 31 of this embodiment is centered on each side 373 of the inner frame 37 of the wafer holder. As a starting point, the part extends outward to the outer edge of the wafer holder 31 in parallel, and a plurality of guide grooves 312 having a semicircular cross section are etched, as shown in FIG. 8B. In addition to opening the guide grooves 3 12 on the bottom surface 3 i i of the wafer holder by etching, the guide grooves 312 may be stamped using a conventional stamping method. Fig. 9 is a top view (as shown in Fig. 9A) and a sectional view (as shown in Fig. 9B) of a wafer holder of a semiconductor package according to a third embodiment of the present invention. As shown in the figure, the guide grooves 412 start at the corner ends of the wafer holder inner frame 47 on the bottom surface 411 of the wafer holder 41 at 47 °, and extend parallel to the corner ends of the outer edge of the wafer holder 41. On 414, a plurality of guide grooves 412 having a v-shaped cross section are formed by punching on the bottom surface 411 of the wafer base 41 by a conventional stamping process. The opening of these guide grooves 412 provides a resin mold flow (not shown) and a guide path. As a result, the mold flow resistance of the package tree (not shown) when flowing through the inner frame 47 of the chip holder is reduced, the formation of turbulence is avoided, and the generation of air holes is effectively prevented. The specific embodiments described above are only used to describe the features and effects of the present invention in detail, but not to limit the implementable scope of the present invention. Any application of the present invention without departing from the technical scope and spirit of the present invention is not intended. Equivalent changes and modifications completed shall still be covered by the scope of the patent application disclosed under the present invention. The i-scale is applicable to China National Standard (CNS) A4 specifications (210 X 297 Public Manager 16260 -------- I ----- · II (Please read the precautions on the back to write this page). · 486790 A7 _B7 V. Description of the invention (8) [Symbol number description] Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy 1.2 Semiconductor packages 10, 20, 30, 40 Semiconductor wafers 200 Wafer pads 11, 21, 31 , 41 wafer holder 210 wafer holder top surface 211,311,411 wafer holder bottom surface 212,312,412 guide groove 213 groove formation area 414 wafer holder corner end 22. Lead frame 220,320,420 tie bar 13,23 guide pin 14,24,34,44 silver glue 15, 25 Gold wire 26 Encapsulation gel 19,29 Resin mold flow 17,27,37,47 Chip holder inner frame 170,270,370 Corner position 171,271 Bevel 172 Slag 373 Inner frame side 28 Photoresist layer 14 Silver glue ----- ----- 一 ---- Loading --- (Please read the notes on the back to write this page) ..--The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 8 16260