A7A7
483299 A7 B7 五、發明說明（2 ) (請先閱讀背面之注意事項再填寫本頁；> 具有一置晶墊12及一組導腳13 ; (ii)一半導體晶片14，其 係安置於置晶塾12之正面12a上，並藉由一組銲線15而 電性連接至導腳13之正面13a上；以及（Hi)一封裝膠體 1 6，其用以包覆半導體晶片14及導線架丨丨，但使得置晶 墊12之为面12b及導腳13之背面13b外露於封裝膠體16 的底部外面。 由於QFN封裝單元1〇之置晶塾12係外露於封裝膠體 16之底部外面，因此其亦習稱為”露墊型，,（exp〇sed-pad type)封裝單元；且由於QFN封裝單元1〇之導腳i3之實 體部分係整個包覆於封裝膠體16之中，僅其背面nb外露 於封裝膠體16之底部外面，因此其亦稱為”無導腳式 ’’（non-leaded，或 leadless)封裝單元。 經 濟 部 智 慧 財 產 局 員 工 消 費 合 社 印 製 印刷電路板20包括—基板21、—絕緣保護層“、一 接地面（ground p丨ane)23、以及複數個導電指⑷ectncaiiy_ conducive fingers)24。接地面23用以作為qfn封裝單元 1〇之外露置晶塾12的安置區域’且其面積大致等於外露 置晶塾12的面積；而導電指24則為印刷電路板2〇上的電 性連接點，其面積大致等於qFn封裝單元ι〇上的各個導 腳13之外露表面13b的面積。因此接地面23的黏銲面積 係遠大於各個導電指24的黏銲面積。 、 請接著參閱第1C圖，下一個步驟為進行一塗銲程序 ㈣der-pastlng process) ’藉以將一銲料塗佈於接地面U 和各個導電指24之表面上。由於接地面23的黏銲面積遠 A於各個導電指24的黏銲面積，因此會於接地面23上形 本紙張尺度顧巾關家，鮮（CNS)A4規格⑵Q χ巧公爱 2 16099 A7 B7483299 A7 B7 V. Description of the invention (2) (Please read the notes on the back before filling in this page; > Has a crystal pad 12 and a set of guide pins 13; (ii) A semiconductor wafer 14, which is placed on Place the front face 12a of the wafer 12 and electrically connect to the front face 13a of the guide pin 13 through a set of bonding wires 15; and (Hi) a packaging gel 16 that is used to cover the semiconductor wafer 14 and the wires丨 丨, but the crystal pad 12 is placed on the surface 12b and the rear surface 13b of the guide pin 13 is exposed outside the bottom of the packaging gel 16. Because the QFN package unit 10 is placed on the outside of the bottom of the packaging gel 16 is exposed outside the bottom of the packaging gel 16 Therefore, it is also commonly referred to as an "exposure-pad type" packaging unit; and because the solid part of the guide pin i3 of the QFN packaging unit 10 is entirely covered in the packaging gel 16, only The back side nb is exposed outside the bottom of the packaging colloid 16, so it is also known as a "non-leaded" or leadless packaging unit. Printed Circuit Board 20, Intellectual Property Bureau, Ministry of Economic Affairs, Employees Consumer Cooperative Including-substrate 21,-insulation protection layer ", a ground plane (gro und pane) 23, and a plurality of conductive fingers (ectncaiiy_ conducive fingers) 24. The ground plane 23 is used as a placement area of the exposed crystal wafer 12 outside the qfn packaging unit 10, and its area is approximately equal to that of the exposed crystal wafer 12 Area; and the conductive finger 24 is an electrical connection point on the printed circuit board 20, and its area is approximately equal to the area of the exposed surface 13b of each of the guide pins 13 on the qFn packaging unit ι0. Therefore, the bonding area of the ground plane 23 It is much larger than the bonding area of each conductive finger 24. Please refer to Figure 1C, the next step is to perform a coating process (der-pastlng process) 'to apply a solder to the ground plane U and each conductive finger 24 On the surface. Since the bonding area of the ground surface 23 is much larger than the bonding area of each conductive finger 24, the paper scale will be shaped on the ground surface 23, and the size of the paper (CNS) A4 ⑵Q χqiao Love 2 16099 A7 B7
五、發明說明（3 ) 經濟部智慧財產局員工消費合作社印製 成一大㈣之料31，而於各個導電指24上則形成一小 面積之杯塊32。此塗銲程疼+ # 序70成後，所形成之大面積銲塊 、面係、大致平齊於各個小面積銲塊32❸上表面。 請接著參閱第10圖，下一個步驟為進行一表面藕接 程序’其令首先將QFN封裝單元1〇安置於印刷電路板2〇 上，並使得外露置晶$12對齊至接地面23,並使得各個 導腳13刀別對齊至對應之導電指24(亦即將外露置晶塾η 安置於大面料塊31上，並將各個導腳13分別安置於各 個小面積銲塊3 2上）。 接著進行一迴銲程序（solder-refl〇wpr〇cess)，藉以將 大面積銲塊31迴銲於接地面23與外露置晶塾i2之間，並 同時將小面料塊32迴銲於各個導腳_對應之導電指 24之間。此即可將外露置晶塾12藉由迴銲後之大面積鲜 塊31而銲結至接地面23,並同時將各個導腳13藉由迴銲 後，小面積輝塊32而銲結至導電指24。此即完成QFN封 裝單元10至印刷電路板20的藕接程序。 J而由於迴銲程序中，熔化之銲料會向中心聚縮，因 此會使得迴銲後的銲塊的厚度會略為向上隆起；且面積愈 大之絆塊，其向上隆起的程度也就愈大。 因此如第1E圖所示，迴銲後之大面積銲塊31的隆起 高度會大於迴銲後之小面積銲塊32的隆起高度，致使qfn 封裝單元10中銲結於接地面23上的部分被向上推擠，產 生所明之浮銲現象。但由於迴銲後之小面積銲塊3 2的隆起 高度並不大，因此上述之浮銲現象將導致導 3被向上拉 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 16099 1 I I I---訂-------I I » ^e___wl (請先閱讀背面之注意事項再填寫本頁) 483299 A7 五、發明說明（4 升因而可月b致使導腳13未能有效地焊結至導電指μ上 的輝塊32,而形成虛鲜或斷輝狀態（如第1£圖中之標號 所指之部位即為成斷銲狀態之導腳），使得㈣封裝單元 與印刷電路板20所組合而成之電路模組具有不佳之鲜 結品質性及可靠度。 相關之專利技術例如包括有美國專利第5，i72,2i4號 HEADLESS SEMICONDUCTOR DEVICE ΑΝ〇 ΜΕΤΗ〇〇 順MAONG ΤΗΕ S纖，，。此專利技術揭露了一種無導聊 式之半導體封裝結構及製程。然而，此專利技術並無法用 來解決前述之浮銲問題。 [發明概述] 審於以上所述習知技術之缺點，本發明之主要目的便 是在於提供-種露塾型封裝單元至印刷電路板竊接方法， 其可防止前述之浮銲問題。 本發明之另一目的在於·蔣祉 ^ ^ ^ 刃隹於挺供一種露墊型封裝單元至 刷電路板藕接方法，其可使得露塾型 丁路ϋ封裝早兀與印刷 板所組合而成之電路模組具有更佳之品質性及可靠度。 根㈣上所述之目的，本發明即提供了 _種_ 墊型封裝單元至印刷電路板藕接方法。 、 2發明之露塾型封裝單元至印刷電路板藕接方法包含 以下步驟‘ (1)形成一銲料收納槽於該置晶墊之外露 ⑺將-銲料塗佈於該接地面上，藉此而形成—第 並亦塗佈於各個導電指之表面上， ’ 錯此而形成複數個笫- 匕錄塊；（3)將該露塾型圭1 元安置於該印刷電路板上: 尺度適用中關家標準（CNS)A4規格（210 X 297公爱)_ 4 16099 --------------Μ — (請先閱讀背面之注意事項再填寫本頁) 1 . 線- 經 濟 部 智 慧. 財 產 局 呈- 消 費 合 作 社 印 製 483299 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（5 ) 中使得該外露置晶墊對齊至該接地面，並使得各個 別對齊至各個導電指；以及⑷進行一迴辉程序，藉以將^ 弟-銲塊迴銲於該外露置晶墊與該接地面之間，並將 各個第二銲塊分別迴銲於各個導腳與對應之導電指之間； 其中該第-銲塊的迴銲隆起部分被收納於該外露置晶塾上 所形成之銲料收納槽之φ| + I , ^ 價之节精此而防止該露墊型封裝單开 浮銲於該印刷電路板上。 由於鮮料收納槽可收納塗佈於接地面上之鲜塊的 隆起部分，因此可防止露墊型封裝單元浮鲜於印刷電 上。此特點可使得露墊型封裝單元和印刷電路板所組 成之電路模組具有較佳之銲結品質性及可靠度。 [圖式簡述] 又 本發明之實質技術内容及 谷及其實施例已用圖解方式詳細 揭露繪製於本說明書所附之圖式 ' 述如下： τ此些圖式之内容簡 第1A至1E圖（習知技術）為結構 傅不思圖，其用以顯示 知之露塾型封裝單元至印刷電路板藕接方法； 第2A至2D圖為結構示意圖，其用以顯示本發明 塾型封裝單it至印刷電路板藕接方法的第_實施例； 第3A至3B圖為結構示意圖，其分別顯示本發明第一 實施例所採用之二種不同形態之銲料收納槽； 第4A至4B圖為結構示意圖，其用以‘示本發明之露 塾型封裝單元至印刷電路板藕接方法的第二實施例； 第从至5B圖為結構示意圖，其分別顯示本發明第二 私紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公复了 5 16099 -------裝--- (請先閱讀背面之注意事項再填寫本頁) 訂--- 曄 483299 A7 B7 五、發明說明（6 ) 實施例所採用之二種不同形態之銲料收納槽[圖式標號] 10 QFN封裝單元 置晶塾（die pad) 置晶墊12之背面 導腳13之正面 半導體晶片 經 濟 部 智 慧 財 產 局 員 工 消 費 合 社 印 製 12 12b 13a 14 16 21 23 31 40 111 112a 113 113b 115 117 121 123 131 210 212 封裝膠體 基板 接地面 大面積銲塊 斷銲部位 導線架（leadframe) 置晶墊112之正面 導腳 導腳11 3之背面 銲線 11 12a 13 13b 15 20 22 24 32 110 112 112b 113a 114 116 中央位置之銲料收納槽120 基板 接地面 大面積之第一銲塊 QFN封裝單元 置晶塾（die pad) 置晶墊2 1 2之背面 122 124 132 211 212a 213 導線架（leadframe) 置晶塾12之正面 導腳 導腳13之背面 銲線 印刷電路板 絕緣保護層 導電指 小面積銲塊 QFN封裝單元 置晶塾（die pad) 置晶墊112之背面 導腳113之正面 半導體晶片 封裝膠體 印刷電路板 絕緣保護層 導電指 小面積之第二銲塊 導線架（leadframe) 置晶墊2 1 2之正面 導腳 212bV. Description of the invention (3) The consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed a large amount of material 31, and a small area of cup 32 was formed on each conductive finger 24. This coating welding process is painful. After the sequence is 70%, the formed large-area solder bumps, the surface system, are approximately flush with the upper surface of each small-area solder bump 32❸. Please refer to FIG. 10. The next step is to perform a surface bonding process. “This command first places the QFN package unit 10 on the printed circuit board 20 and aligns the exposed die $ 12 to the ground plane 23 and makes Each guide pin 13 is aligned with the corresponding conductive finger 24 (that is, the exposed crystal 塾 η is placed on the large fabric block 31, and each guide pin 13 is placed on each small area solder block 32). Next, a solder-reflection process (solder-refl ow pr ocess) is performed to re-solder a large-area solder block 31 between the ground plane 23 and the exposed crystal i2, and simultaneously re-solder the small fabric block 32 to each guide. The pin _ corresponds to the conductive finger 24. At this time, the exposed crystal ridge 12 can be welded to the ground plane 23 through the large-area fresh block 31 after re-soldering, and each guide pin 13 can be welded to the small-area glow block 32 after re-soldering. Conductive finger 24. This completes the bonding process from the QFN packaging unit 10 to the printed circuit board 20. J. Because the reflowed solder will shrink to the center during the reflow process, the thickness of the solder bump after reflow will slightly bulge upward; and the larger the area of the stump, the greater the upward bulge. . Therefore, as shown in FIG. 1E, the bump height of the large-area solder bump 31 after reflow is greater than the bump height of the small-area solder bump 32 after reflow, resulting in the portion of the qfn package unit 10 that is soldered to the ground plane 23 It is pushed upwards, producing the phenomenon of floating welding that is known. However, since the bump height of the small-area solder bump 3 2 after re-soldering is not large, the above-mentioned floating soldering phenomenon will cause the guide 3 to be pulled upward. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). ) 16099 1 II I --- Order ------- II »^ e ___ wl (Please read the notes on the back before filling out this page) 483299 A7 V. Description of the invention (4 liters can lead to the guide pin 13 a month b) Failure to effectively bond to the luminous mass 32 on the conductive finger μ, resulting in a fresh or broken state (as indicated by the number in the figure in Figure 1 is the guide pin in the broken state), so that ㈣ The circuit module composed of the packaging unit and the printed circuit board 20 has poor quality and reliability. Related patent technologies include, for example, US Patent No. 5, i72, 2i4 HEADLESS SEMICONDUCTOR DEVICE ΑΝΜΜΤΤ〇〇 This patented technology discloses a non-conducting semiconductor packaging structure and manufacturing process. However, this patented technology cannot be used to solve the aforementioned floating soldering problem. [Summary of the Invention] Examined above Disadvantages of the conventional technology The main purpose is to provide a method of stealing a dew-type packaging unit to a printed circuit board, which can prevent the above-mentioned floating soldering problem. Another object of the present invention is: Jiang Zhi ^ ^ ^ The pad-type packaging unit-to-brush circuit board bonding method can make a circuit module formed by a combination of an open-type Dingluo package and a printed circuit board have better quality and reliability. The purpose of the present invention is to provide _species_ pad-type packaging units to printed circuit board bonding methods. 2 The invention's exposed-type packaging units to printed circuit board bonding methods include the following steps' (1) forming a solder storage slot Exposed on the crystal pad, the solder is coated on the ground surface, thereby forming—the first layer is also coated on the surface of each conductive finger, 'wrong to form a plurality of 笫 -dagger blocks; (3) Place the Lu Xun type 1 yuan on the printed circuit board: The standard applies to the Zhongguanjia Standard (CNS) A4 specification (210 X 297 public love) _ 4 16099 ---------- ---- Μ — (Please read the notes on the back before filling out this page) 1. Line-Ministry of Economy Wisdom. Presented by the Property Bureau-printed by the Consumer Cooperative 483299 printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 printed by the Consumer Cooperative Fifth, the description of the invention (5) aligns the exposed crystal pad to the ground plane and aligns each conductive finger; And ⑷ carry out a back glow program, so that ^ brother-solder bumps are re-soldered between the exposed crystal pad and the ground plane, and each second solder bump is re-soldered to each guide pin and the corresponding conductive finger Among them, the reflow bulge portion of the first soldering block is stored in the solder receiving groove φ | + I formed on the exposed wafer, and the price is reduced to prevent the open-pad type package from floating. Solder on the printed circuit board. Since the fresh material storage tank can hold the raised portion of the fresh block coated on the ground surface, the exposed pad type packaging unit can be prevented from floating on the printed circuit board. This feature can make the circuit module composed of the exposed pad package unit and the printed circuit board have better soldering quality and reliability. [Brief Description of the Drawings] The essential technical contents and valleys of the present invention and their embodiments have been disclosed in detail by diagrams. The drawings drawn in the description of the description are as follows: τ The contents of these drawings are briefly described in Sections 1A to 1E. Figure (known technique) is a structure Fu Fusi diagram, which is used to show the method of connecting known open-type packaging units to printed circuit boards; Figures 2A to 2D are schematic diagrams of structures, which are used to display the 塾 -type packaging sheet of the present invention The fourth embodiment of the method for connecting it to a printed circuit board; FIGS. 3A to 3B are schematic structural diagrams, which respectively show two different types of solder storage tanks used in the first embodiment of the present invention; Schematic diagram of the structure, which is used to show the second embodiment of the method for connecting the exposed packaging unit to the printed circuit board of the present invention; Figures 1 to 5B are schematic diagrams of structures, which respectively show that the second private paper scale of the present invention is applicable to China National Standard (CNS) A4 specifications (210 X 297 publicly replied 5 16099 ------- install --- (Please read the precautions on the back before filling this page) Order --- 晔 483299 A7 B7 V. Description of the Invention (6) Two different types used in the embodiments Solder storage slot [drawing number] 10 QFN package unit Die pad Place the back pad 13 of the die pad 12 On the front side of the semiconductor chip Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Employee Consumer Cooperative 12 12b 13a 14 16 21 23 31 40 111 112a 113 113b 115 117 121 123 131 210 212 Encapsulated colloidal substrate ground plane Large area solder block Broken part lead frame Lead pad on the front side of the die pad 112 3 Back side welding wire 11 12a 13 13b 15 20 22 24 32 110 112 112b 113a 114 116 Solder storage tank in the central position 120 The first pad of the substrate with a large area QFN package unit Die pad Place the back of the pad 2 1 2 122 124 132 211 212a 213 Leadframe Set the front guide pins and back pins of the chip 13 Backside of the printed circuit board Insulation protection layer Conductive finger Small area solder block QFN package unit Set the die pad 112 Back side guide pin 113 front side semiconductor chip package gel printed circuit board insulation protective layer conductive finger second area lead frame with small pad 2 1 2 front side guide pin 212b
^-------------------^ (請先閱讀背面之注意事項再填寫本頁) 483299^ ------------------- ^ (Please read the notes on the back before filling this page) 483299
213a 導腳213之正面 213b 導腳213之背面 214 半導體晶片 215 銲線 216 封裝膠體 217 周邊位置之銲料收納槽 218 對位用之肋狀結構 220 印刷電路板 221 基板 222 絕緣保護層 223 接地面 224 導電指 231 大面積之第一銲塊 [發明實施例] 232 小面積之第二銲塊 以下即配合所附圖式第 2A至 2D圖、第3A至3B圖、 (請先閱讀背面之注意事項再填寫本頁) 〜 ......紛5兀％ + 發明之露墊型封裝單元至印刷電路板藕接方法之不同之嘴 施例。 實圖及篱 3Α $ 3R Μ 第 以下配合所附圖式中之第2八至2D圖及第3八至3Β 圖’詳細揭露說明本發明之第一實施例。 經 濟 部 智 慧 財 產 局 員 工 消 費 合 社 印 製 請首先參閲第2Α圖和第2丑圖，本發明之露墊型封菜 單元至印刷電路板藕接方法的第-實施例得、用以將一 QFN封裝單元11〇藕接至一印刷電路板12〇。 封裝單元11G包含以下構件··⑴_導線架⑴， 其具有一置晶墊112及一組導腳u 3 ; (π)_半導體晶片 114，其係安置於置晶墊112之正面1123上，並藉：一組 銲線115而電性連接至導腳113之正面n3a;以^ 封裝膠體116,其用以包覆半導體a 復千导體曰曰片114及導線架111, 但使得置晶墊112之背面112b及導 等腳113之背面113b夕丨 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公爱） Α7 Α7 經濟部智慧財產局員工消費合作社印製 五、發明說明（8 ) 露於封裝膠體116之底部外面。 —印刷電路板120包括一基板121、一絕緣保護層122、 ~接地面123、以及複數個導電指124;其中接地面123 用以作為QFN封裝單元110之外露置晶墊112的安置區 域’而導電指124則作為印刷電路板12〇上的電性連接點。 本發明的主要特點即在於形成一銲料收納槽H 7於置 晶墊112之外露表面112b的中央位置上，且該銲料收納槽 U7之容積須大致等於塗佈於接地面123上之第一銲塊 131(顯示於後續之第2C圖）的迴銲隆起部分的體積。 外蝽之置sa.墊112上所形成之銲料收納槽丨丨7之底面 形狀可為任何製程上易於製作之形狀，例如為第3A圖所 示之圓形、或為第3B圖所示之正方形。但除此二種形狀 之外，其它之形狀亦為可行。 請接著參閱第2C圖，下一個步驟為進行一塗銲程序， 其中將一銲料塗佈於接地面123上，藉此而形成一大面積 之第一銲塊131於接地面123上；並同時亦塗佈於各個導 電指124之表面上，藉此而形成複數個小面積之第二銲塊 132於該些導電指124之表面上。 請接著參閱第2D圖，下一個步驟為進行一表面藕接 程序，其中首先將QFN封裝單元110安置於印刷電路板 1 20上，並使得外露置晶墊}丨2對齊至接地面1 23，並使得 各個導腳113分別對齊至各個導電指124(亦即將外露置2 塾112安置於第一銲塊131上，並同時將各個導腳u3分 別安置於各個第二銲塊1 32上）。 乃 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 16099 I *---— — II ^-----II — (請先閱讀背面之注意事項再填寫本頁) 483299 五、發明說明（9 ) 接著進行一迴銲程序，藉以將第一銲塊131迴銲於接 地面123與外路置晶墊112之間，並同時將各個第二鋒塊 132迴銲於各個導腳113與對應之導電指124之間。此即 可將外露置晶墊112藉由迴銲後之第—銲塊131而婷結至 接地面123，並同時將各個導腳113藉由迴銲後之第二銲 塊而分別銲結至對應之導電指124。此即完成封 裝單元110至印刷電路板12〇的藕接程序。 於上述之迴銲程序中，由於迴銲後之第一銲塊的 隆起部分會被收納於外露置晶塾112上所形成之輝料收納 槽117之中，因此不會如習知技術般地產生浮銲現象。此 特點可使# QFN封裝單元！ ！ 〇和印刷電路板！ 2〇所組合而 成之電路模組具有更佳之銲結品質性及可靠度。 差一士實施例丄至5B圖、 以下配合所附圖式第4A至4β圖及第5a至5B圖， 詳細揭露說明本發明之第二實施例。 # 凊首先參閱第4A圖，本發明之露塾型封裝單 刷電路㈣接方法的第一實施例係用以將一二早:裝至二 元210藕接至一印刷電路板22〇。 QFN封裝單元21〇包含以下構件：⑴一導線架2ιι， 其具有一置晶塾212及一組導腳213 ; (11)一半導體晶片 214，其係安置於置晶墊212之正面212&上，並藉由一組 銲線215而電性連接至導腳213之正面213a;以及（ιιι)一 封裝膠體216,其用以包覆半導體晶片214及導線架2ιι， 但使得置晶墊212之背面212b及導腳213之背面213b外 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公釐） 9 16〇99 A7 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明（10 / 路於封裝膠體2 1 6之底部外面。 印刷電路板220包括一基板221、一絕緣保護層222、 接地面223、以及複數個導電指224 ;其中接地面223 用以作為QFN封裝單元21〇之外露置晶墊212的安置區 域而^導電指224則作為印刷電路板22〇上的電性連接點。 ^第一實施例的特點即在於形成一銲料收納槽2丨7於外 路置曰日墊2 1 2的周邊位置上（第一實施例中係形成於中央 位置上）。此銲料收納槽217之容積亦須大致等於塗佈於接 地面223之第一銲塊231(顯示於後續之第4b圖）的迴銲隆 起部分的體積。 冬此周邊位置之銲料收納槽217之底面形狀可為任何適 當之形狀；例如為第5A圖及第5B圖即顯示二種可行之實 方式第5A圖所示之銲料收納槽217的實施方式為一 正方形環狀；而第5B圖所示之實施方式則為進一步增設 複數個對位用之肋狀結構218於外露置晶墊212的周邊 上，藉以協助增加QFN封裝單力21〇藕接至印刷電路板 220之對位準度。但除此二種實施方式之外，其它之形狀 亦為可行。 +睛接著參閱第4B圖，下一個步驟為進行一塗銲程序， 藉此而形成一大面積之第一銲塊231於接地面223上，並 同時形成複數個小面積之第二銲塊232於該些導電指… 之二面上。接著進行-表面藕接程序，其中首先將qFn封 裝單元210安置於印刷電路板22〇上，並使得外露置晶塾 212對齊至接地面223，並使得各個導腳分別對齊至各 ^尺度適格(21。X 297 公髮} ιυ — 16099 -------------裝--------訂—--------線 (請先閱讀背面之注意事項再填寫本頁) 483299 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（11 ) 個導電指以。再接著進行—迴銲程序，藉以將第一鋒塊 1迴鲜於接地面223與外露置晶塾2U之間，並同時將 各個第二銲塊232迴録於各個導腳213與對應之導電指 224之間。此即可將外露置晶塾212藉由迴銲後之第—銲 塊⑶而録結至接地面223,並同時將各個導腳213藉由 迴銲後之第二鲜塊232而分別鮮結至對應之導電指以。 此即完成QFN封裝單元210至印刷電路板22〇的藕接程 序。 於上述之迴銲程序中，由於迴銲後之第一銲塊231的 隆起部分會被收納於銲料收納槽217之中，因此不會如習 知技術般地產生浮銲現象。此特點可使得qfn封裝單元 2 1 0和印刷電路板22〇所組合而成之電路模組具有更佳之 銲結品質性及可靠度。 [結論] 练而g之’ ’、本發明提供了 一種新穎之露墊型封裝單元 至印刷電路板藕接方法，其特點在於形成一銲料收納槽於 外露之置晶墊上；於迴銲過程中，此銲料收納槽即可收納 塗佈於接地面上之銲塊的迴銲隆起部分，因此可防止露墊 型封裝單元浮銲於印刷電路板上。此特點可使得Qfn封裝 單元和印刷電路板所組合而成之電路模組具有更佳之婷結 品質性及可靠度。 以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之實質技術内容的範圍。本發明之實質技術内容 係廣義地定義於下述之申請專利範圍中。任何他人所完成 -I * I I I I I I I 一-0’ — ! — — — - (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 11 16099 483299 A7 _B7_ 五、發明說明（12 ) 之技術實體或方法，若是與下述之申請專利範圍所定義者 為完全相同、或是為一種等效之變更，均將被視為涵蓋於 中之 圍範利 專此 --------------裝--- (請先閱讀背面之注意事項再填寫本頁) 訂： -丨線· 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 12 16099213a Front surface of guide pin 213 213b Back surface of guide pin 213 214 Semiconductor wafer 215 Welding wire 216 Encapsulation gel 217 Solder storage groove at the peripheral position 218 Rib structure for alignment 220 Printed circuit board 221 Substrate 222 Insulating protective layer 223 Ground plane 224 Conductive finger 231 Large area of the first soldering block [Invention Example] 232 Small area of the second soldering block The following is to match the drawings 2A to 2D, 3A to 3B, (Please read the precautions on the back first (Fill in this page again) ~ ...... 55% + Different embodiments of the invention of the exposed pad-type packaging unit to the printed circuit board bonding method. Real pictures and fences 3Α $ 3R Μ The following describes in detail the first embodiment of the present invention in conjunction with the 28th to 2D drawings and the 38th to 3B drawings' in the drawings. Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economics. Please refer to FIG. 2A and FIG. 2 first. A QFN package unit 110 is connected to a printed circuit board 120. The packaging unit 11G includes the following components: ⑴_ lead frame 具有, which has a crystal pad 112 and a set of guide pins u 3; (π) _ a semiconductor wafer 114, which is disposed on the front surface 1123 of the crystal pad 112, And by: a set of bonding wires 115 to be electrically connected to the front side n3a of the lead 113; encapsulation gel 116 is used to cover the semiconductor a complex conductor chip 114 and the lead frame 111, but makes the crystal The back 112b of the pad 112 and the back 113b of the guide leg 113 丨 This paper size applies to China National Standard (CNS) A4 (21 × 297 public love) Α7 Α7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Note (8) is exposed outside the bottom of the encapsulant 116. -The printed circuit board 120 includes a substrate 121, an insulating protection layer 122, a ground plane 123, and a plurality of conductive fingers 124; the ground plane 123 is used as a placement area for the exposed crystal pad 112 outside the QFN packaging unit 110. The conductive fingers 124 serve as electrical connection points on the printed circuit board 120. The main feature of the present invention is that a solder receiving groove H 7 is formed at the center of the exposed surface 112 b of the crystal pad 112, and the volume of the solder receiving groove U 7 must be approximately equal to the first solder coated on the ground plane 123. The volume of the reflow bump of block 131 (shown in Figure 2C below). The shape of the bottom surface of the solder storage groove formed on the outer pad sa. Pad 112 can be any shape that is easy to make in any process, such as the circle shown in FIG. 3A or the shape shown in FIG. square. But in addition to these two shapes, other shapes are also feasible. Please refer to FIG. 2C. The next step is to perform a coating process, in which a solder is applied on the ground plane 123, thereby forming a large area of the first solder bump 131 on the ground plane 123; and at the same time, It is also coated on the surfaces of the conductive fingers 124, thereby forming a plurality of small solder bumps 132 on the surfaces of the conductive fingers 124. Please refer to FIG. 2D. The next step is to perform a surface bonding process. First, the QFN package unit 110 is placed on the printed circuit board 120, and the exposed crystal pad} 2 is aligned to the ground plane 1 23. And each guide pin 113 is aligned to each of the conductive fingers 124 (that is, the exposed 2 塾 112 is placed on the first pad 131, and each guide pin u3 is placed on each of the second pads 132). This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public love) 16099 I * ---- — II ^ ----- II — (Please read the precautions on the back before filling this page) 483299 V. Description of the invention (9) Next, a reflow process is performed to re-solder the first solder bump 131 between the ground plane 123 and the external crystal pad 112, and simultaneously re-solder each of the second front bumps 132 to Between each guide pin 113 and the corresponding conductive finger 124. At this time, the exposed crystal pad 112 is connected to the ground plane 123 through the first solder bump 131 after re-soldering, and each lead pin 113 is simultaneously soldered to the second solder bump after re-soldering to Corresponding conductive fingers 124. This completes the connection process from the packaging unit 110 to the printed circuit board 120. In the reflow process described above, since the raised portion of the first solder bump after reflow is stored in the glow material storage groove 117 formed on the exposed crystal cymbal 112, it will not be as conventional technology. Floating phenomenon occurs. This feature enables # QFN package units! !! 〇 and printed circuit board! The combined circuit module has better soldering quality and reliability. The difference between the first embodiment and the second embodiment is shown in Figs. 5B. The following describes the second embodiment of the present invention in detail with reference to the drawings 4A to 4β and 5a to 5B. # 凊 Firstly, referring to FIG. 4A, the first embodiment of the open-type packaged single-brush circuit connection method of the present invention is used to connect a 210 to a binary circuit 210 to a printed circuit board 22o. The QFN package unit 21 includes the following components: a lead frame 2 ι, which has a chip 212 and a set of guide pins 213; (11) a semiconductor wafer 214, which is arranged on the front surface 212 & And is electrically connected to the front surface 213a of the guide pin 213 through a set of bonding wires 215; and a packaging gel 216, which is used to cover the semiconductor wafer 214 and the lead frame 2m, but the crystal pad 212 is placed The back side 212b and the back side 213b of the guide leg 213. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (21 × 297 mm) 9 16099 A7 A7 Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs (10 / way outside the bottom of the packaging gel 2 16. The printed circuit board 220 includes a substrate 221, an insulating protection layer 222, a ground plane 223, and a plurality of conductive fingers 224; the ground plane 223 is used as a QFN package unit The placement area of the crystal pad 212 is exposed outside 21 °, and the conductive fingers 224 are used as electrical connection points on the printed circuit board 22 °. ^ The first embodiment is characterized by forming a solder receiving groove 2 丨 7 on the outside. At the periphery of the sun pad 2 1 2 ( In one embodiment, it is formed at the central position.) The volume of the solder receiving groove 217 must also be approximately equal to that of the reflow bulge portion of the first solder bump 231 (shown in the subsequent figure 4b) coated on the ground plane 223. Volume. The shape of the bottom surface of the solder accommodating groove 217 at the peripheral position in winter can be any suitable shape; for example, Figures 5A and 5B show two possible practical implementations of the solder accommodating groove 217 shown in Figure 5A. The method is a square ring; the embodiment shown in FIG. 5B is to further add a plurality of alignment rib structures 218 on the periphery of the exposed crystal pad 212 to help increase the single force of the QFN package 21〇 藕It is connected to the alignment degree of the printed circuit board 220. However, in addition to these two embodiments, other shapes are also feasible. + Next, referring to FIG. 4B, the next step is to perform a coating process, thereby A large-area first solder bump 231 is formed on the ground plane 223, and a plurality of small-area second solder bumps 232 are simultaneously formed on the two surfaces of the conductive fingers. Then, a surface-to-surface bonding process is performed, where first Package qFn 210 Place it on the printed circuit board 22, and align the exposed chip 212 to the ground plane 223, and align each guide pin to the appropriate size (21. X 297 public hair) ιυ — 16099 ----- -------- Equipment -------- Order --------- line (please read the precautions on the back before filling this page) 483299 Employee Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs A7 is printed. 5. Description of the invention (11) Conductive fingers. Then proceed with the re-soldering procedure, so that the first front block 1 is freshly placed between the ground plane 223 and the exposed crystal ridge 2U, and each second solder block 232 is recorded back to each guide leg 213 and the corresponding conductive Between 224. At this time, the exposed crystal 塾 212 can be recorded to the ground plane 223 by the first soldering block ⑶ after re-soldering, and each guide pin 213 can be freshly knotted at the same time by the second fresh block 232 after re-soldering. To the corresponding conductive fingers. This completes the connection process from the QFN package unit 210 to the printed circuit board 22. In the reflow process described above, since the raised portion of the first solder bump 231 after reflow is stored in the solder storage groove 217, the floating soldering phenomenon does not occur as in the conventional technology. This feature can make the circuit module formed by combining the qfn packaging unit 210 and the printed circuit board 22 with better soldering quality and reliability. [Conclusion] The present invention provides a novel method for bonding exposed pad-type packaging units to printed circuit boards, which is characterized by forming a solder receiving groove on the exposed crystal pad; during the reflow process This solder storage tank can accommodate the reflow bulge portion of the solder block coated on the ground surface, so that the exposed pad-type packaging unit can be prevented from floating to the printed circuit board. This feature can make the circuit module composed of Qfn packaging unit and printed circuit board have better quality and reliability. The above descriptions are merely preferred embodiments of the present invention, and are not intended to limit the scope of the essential technical content of the present invention. The essential technical content of the present invention is broadly defined in the scope of the following patent applications. Completed by anyone else -I * IIIIIII a -0 '—! — — —-(Please read the notes on the back before filling out this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 11 16099 483299 A7 _B7_ V. The technical entity or method of the invention description (12), if it is exactly the same as the one defined in the patent application scope below, or an equivalent change, will be deemed to be included in the Fan Li special here -------------- install --- (Please read the precautions on the back before filling this page) Order: The paper size printed by the cooperative applies the Chinese National Standard (CNS) A4 (210 X 297 mm) 12 16099