Λ529^ 9 Α7 經濟部智慧財產局員工消费合作社印製 _____Β7_ 五、發明說明（1 ) [發明領域] 本發明係有關於一種覆晶式半導趙製程技術’特別是 有關於一種半導體晶圓上之電鍍式覆晶銲塊製造方法’其 可用以於半導體晶圓上’以電鍍方式形成銲塊底部金屬化 结構層（Under Bump Metallization，UBM)和鋅塊（solder bump) β [發明背景] 覆晶式（Flip Chip)半導體封裝技術為一種先進之半導 體封裝技術，其與一般習知之非覆晶式封裝技術的最主要 之不同點在於其所封裝之半導體晶片係以正面朝下之倒置 方式安置於基板上’並藉由複數個銲塊（solder bumP)而銲 結及電性連接至基板3由於覆晶式封裝結構體中不需要使 用較佔空間之鲜線（bonding wires)來將半導體晶片電性連 接至基板，因此可使得整體尺寸作得更為輕薄短小。 欲將銲塊銲結於晶片上’首先須在半導體晶片上形成 所謂之銲塊底部金屬化（Under Bump Metallization，UBM) 結構層，以作為銲塊之底部銲墊。 目前已有許多不同的專利技術可以用來製作UBM銲 墊，例如包括以下所列之美國專利： •美國專利第 5,904,859 號"FLIP CHIP METALLIZATION” ； •美國專利第 5,902,686 號"METHODS FOR FORMING AN INTERMETALLIC REGION BETWEEN A SOLDER BUMP AND AN UNDER BUMP METALLURGY LAYER AND RELATED STRUCTURES"； (請先閱tt背面之注意事項再填寫本頁) 裝 訂---------線 本紙張尺度適用令國國家標準（CNS)A4規格（210 X 297公釐） 1 16068 絰濟部智慧財產局員二消費合作让印絜 A7 ___B7_ 五、發明說明（2 ) •美國專利第 6,0 1 5,652 號”MANUFACTURE OF FLIP-CHIP DEVICE ” ； •美國專利第 5,1 37,845 號”METHOD OF FORMING METAL CONTACT PADS AND TERMINALS ON SEMICONDUCTOR CHIPS "； •美國專利第 5,773,3 59 號"INTERCONNECTION SYSTEM AND METHOD OF FABRICATION "： •美國專利第 5S736,456 號”METHOD OF FORMING CONDUCTIVE BUMPS ON DIE FOR FLIP CHIP APPLICATIONS"； •美國專利第 4,927,50 5 號”METALLIZATION SCHEME PROVIDING ADHESION AND BARRIER PROPERTIES"； •美國專利第 5,903,058 號"CONDUCTIVE BUMPS ON DIE FOR FLIP CHIP APPLICATION”。 UBM製程一般常採用的技術方法包括濺鍍方法 (sputtering)、蒸鍍方法（evaporation)、及無電解式電錢方 法（electroless ρ丨ating)。但由於激鍵設備和蒸錢設備之採 購成本頗為昂貴且所需之程序步驟較為繁雜，因此採用無 電解式電鍍方法較為符合成本效益。 然而無電解式電鍍方法的一項缺點在於其後續之銲塊 製程僅能採用網印方法丨:screen pr 1 nt.丨n g)來實施；而網印方 法之程序步驟亦較為繁雜。此外1無電解式電鍍方法之另 --項缺點在於其目前仍無法用來電鍍金i A u )、錫鉛合金 基紙張適用办國國家襟单a:\S)A4規格（:Π0 y 297公釐 \e(m ---------------------訂·--------線 (請先W讀背面之注意事項再填寫本頁) 經 濟 部 智 慧 財 產 局 員 X 消 費 合 作 社 印 製 45294 9 A7 ___ B7___ 五、發明說明（3 ) (Sn/Pb)、及銅（Cu)，因此在製程應用上仍有限制。 [發明概述] 鑒於以上所述習知技術之缺點，本發明之主要目的便 是在於提供一種新穎之電鍍式覆晶銲塊製造方法，其可讓 UBM製程和銲塊製程均透過電鍍方式來實施。 本發明之另一目的在於提供一種新穎之電鍍式復晶銲 塊製造方法’其在實施上可較習知技術更為具有成本效 益β 根據以上所述之目的’本發明即提供了一種新穎之電 鑛式覆晶輝洗製造方法。 本發明之電鍍式覆晶銲塊製造方法適用於一半導逋晶 圓上’該半導體晶圓以預定之切割道劃分出複數個積體電 路晶片’且每一個積體電路晶片上形成有複數個辉墊。 本發明之電鏡式覆晶輝塊製造方法包含以下步驟 形成一電鑛匯流排於該切割道上，且電性相連至各個鋒 墊；（2)進行一 UBM製程，其中係採用電鍍方式，透過該 電鍍匯流排將一第一電鍍電流施加至該半導體晶圓上的各 個銲墊上，以將適用之導電性材料電鍍至各個銲墊上，藉 此而於各個銲墊上形成一 UBM結構層：以及（3)進行一銲 塊製程，其中係採用電鍍方式’透過該電鍍匯流排將一第 二電鍍電流施加至該半導體晶圓上的各個銲墊上，以將一 銲料電鍍至各個銲墊上的UBM结接® L , 王丄列u m释褥層上，藉此而於各個 b整上的UBM結構層上形成一鲜塊。 -述之電鑛式覆晶銲塊製造方法之特於报占 ^ $紙狀度適__準（CNS)A_⑽ ----^點声於$成一電 16068 (請先閱讀背面之注意事項再填寫本頁) --------訂·--------*5^ 經濟部智慧財產局員工消費合作社印f A7 —______B7___ 五、發明說明（4 ) 鍍匯流排於半導體晶圓之切割道上，且其電性相連至每一 個銲墊；藉此而讓UBM製程和銲塊製程均可透過電鍍方 式來實施。由於電鍍製程較習知技術所採用之濺鍍製程、 蒸鍍製程、及網印製程均更為簡易且更具有成本效益，因 此本發明較習知技術具有更進步之實用性。 [圖式簡述] 本發明之實質技術内容及其實施例已用圖解方式詳細 揭露繪製於本說明書所附之圖式之中。此些圖式之内容簡 述如下： 第1圖顯示一覆晶式半導體晶圓之上視示意圖； 第2圖顯示第1圖所示之半導體晶圓之一特定部分之 放大示意圖； 第3A至3C圖為剖面結構示意圖，其用以顯示本發明 之電鍍式覆晶銲塊製造方法中之UBM製程及銲塊製程； 第4圖為一立體結構示意圊，其用以顯示從半導體晶 圓切割下來之積體電路晶片上的電鍍匯流排殘留部分； 第5A圖為一剖面結構示意圖，其用以顯示覆晶底部 填膠製程如何可附帶地對電鍍匯流排殘留部分提供—絕緣 性覆蓋作用： 第5B圖為一剖面結構示意圖，其用以顯示封裝膠體 製程如何可附帶地對電鍍匯流排殘留部分提供—絕緣，陡覆 蓋作用。 [圖式標號j 丨！ 丰導體晶圓 艮紙張.p、度適國家標蕈（CNS)A‘i規格（？1「| < ..)97公爱: --- -------------裝--------訂----------線 (請先閱讀背面之泫意事項再填寫本頁> Λ529Α9 a7 _ B7 五、發明說明（5 ) 11 積體電路晶片 20 切割道 30 銲墊 31 UBM結構層 32 鋒塊（solder bump) 40 電鍍匯流排 40a 電鍍匯流排殘留部分 50 基板 60 覆晶底部填躍層（flip-chip underfill) 61 覆晶底部填膠層60之突出部分 70 封裝膠體 [發明實施例] 以下即配合所附圖式，詳細揭露說明本發明之電鍍式 覆晶銲堍製造方法之一實施例。 第1圖顯示一覆晶式半導體晶圓10之上視示意圖。如 圖所示，此半導體晶圓10係預先以複數條直向及橫向切割 道20劃分成複數個晶片區域11 ;其中每一個晶片區域11 用以製作單一個積體電路晶片。 每一個積體電路晶片11上形成有複數個銲墊（bond pads)3 0，作為積體電路晶片11之内部電路的輸出入連接 點》此些銲墊30可為以鋁製程所製造之鋁墊，亦可為以較 先進之銅製程所製造之銅墊。 第2圈顯示第1圖所示之半導體晶圓10之一特定部分 之放大示意圖。如圖所示，本發明之電鍍式復晶銲塊製造 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (諳先閱讀背面之注意事項再填寫本頁) · ! — 1 I 訂 ------- 經濟部智慧財產局員工消費合作社印製 16068 A7 B7 五、發明說明（6 ) 方法之主要技術特點即在於形成一電鍍匯流排40於半導 艘晶圓1 〇上的切割道20上；此電鍍匯流排40之寬度小於 (請先閱讀背面之注t事項再填寫本頁) 切割道20之寬度，並沿著切割道2〇延伸而連接至積體電 路晶片11中的各個銲墊30。此電鍍匯流排40之製作方法 可為採用習知之金屬化製程，透過罩幕定義而形成於切割 道20上。 第3 A至3C圖為剖面結構示意圖，其用以顯示本發明 之電鍍式覆晶銲塊製造方法中之UBM製程及銲塊製程（註： 此處之第3A至3C圖為簡化之圖式，其僅顯示與本發明有 關之構件.實際之半導體晶圓上之元件數目及結構形態可 能更為複雜）。 第3A圖顯示第2圖所示之各個銲墊3〇及其相連之電 鍍匯流排40的剖面結構示意圖。此電鍍匯流排4〇係配置 於切割道20之表面上，Α電性相連至辉塾3〇，可用以在 電鍍製程中’將電鍍電流匯送至銲塾30。 請接著參閱第3B圖，藉由雷相：雄+ , ® 稽田電鍍匯流排40即可採用電 鍍方式來進行一 UBM製程；其φ姐山& 經濟部智慧財產局員工消費合作钍印裂 共5f經由電鍍匯流排4〇將一 第一電鍍電流匯送至銲墊3〇 ^ ( 上’错此而將適用於作為 UBM之導電性材料，例如為銅（c 、鎳（Ni)、金（Au)，電 鍍至銲墊30上。藉此電鍍方式， 、即可於銲墊30上形成一 UBM結構層3 I α 請接著參閱苐3C圖’下一個步 7驟為進行一銲塊製程， 其中亦經由該電鍍匯流棑40將— 弟二電鍍電流/Ρ2匯送至 銲墊30上；藉此而將一適用之銲料 . 「紙張Φ國國家標聿i〇is>.,vn络Τήί) * 297公着〜—^鍍至鲜墊上，用 16068 45294 9 A7 B7 經濟部智慧財產局員工消费合作社印製 五、發明說明（7 ) 以於銲墊3〇上形成一銲塊32。適用之銲料 金(Sn/Pb)e 銲料例如為錫船合 當半導體晶圓10之製程完成之後’接著將進行一切利 程序，用以沿著切割道20進行切割’藉此而將 路晶片11切割開來。 ％ 如第4圈所示’當各個積體電路晶片u剛從第！圖所 不之半導體晶圖10切離開後，其邊緣和側壁上會殘留有部 分之電鍍匯流排（如第4圖中標號40a所指之部分）。若不 將此電鍍匯流排殘留部分40a作絕緣性覆蓋，則有可能易 於導致積體電路晶片11之内部電路形成短路現象或是易 於使其本身受到侵蝕而導致銲墊3〇受到損壞。然而，於後 續之封裝製程中，卻可附帶地對此些電鍍匯流排殘留部分 40a提供絕緣性覆蓋作用，而不須於整體製程中多增加一 個絕緣覆蓋步驟。 如第5A圈所示，於後續之封裝製程中，係將各個切 割後之積體電路晶片Π以倒置方式（即覆晶方式）安置於一 基板（substrate)5 0上，並藉由銲塊32而銲結及電性相連至 基板50。接著須進行一覆晶底部填膠製程（fUp chip underfill)，用以將一膠質填料填入至積體電路晶片丨丨底 部與基板50上表面之間所存在的間陈中，藉此而形成一覆 晶底部填膠層60。一般而言，此覆晶底部填膠層6〇會包 括一突出部分61於積體電路晶片Η之側邊的外部β由於 此覆晶底部填膠製程為習知技術，因此以下將不對其中之 步驟作進一步詳細之說明。由第5Α圖可看出，覆晶底部 k紙張尺度適用中國國家標準<CNS)A4規格（210 X 297公爱) " ~ ^---I ----訂·-------線 (請先閱讀背面之注意事項再填寫本頁) 16068 7 經濟部智慧財產局員工消費合作社印製 A7 __B7_ 五、發明說明（8 ) 填膠層60的突出部分61即可附帶地蓋覆住積體電路晶片 11上的電鍍匯流排殘留部分40a，因而對其提供了 一絕緣 性覆蓋作用’使得電鍍匯流排殘留部分4 0 a不會接觸到外 部環境。 接著如第5B圖所示’下一個步驟為進行一封裝膠體 製程（encapsulation) ’用以形成一封裝膠體70來包覆整個 的積艘電路晶片11。由第5B圖可看出，此封裝膠體70亦 可附帶地對電錄匯流排殘留部分4 0 a提供一絕緣性覆蓋作 用，使得電鍵匯流排殘留部分4Oa不會接觸到外部環境。 因此本發明之電鍍式覆晶銲塊製造方法雖會造成電鍍 匯流排殘留部分4 0 a於積體電路晶片11之邊緣和側壁上， 但於後續之封裝製程令即可附帶地對此些電鍍匯流排殘留 部分40a提供絕緣性覆蓋作用，而不須於整體製程中多增 加一絕緣覆蓋步驟。 綜而言之，本發明提供了 一種新穎之電鍍式覆晶銲塊 製造方法’其特點在於形成一電艘匯流排於半導體晶圓之 切割道上’並將此電鍍匯流排電性相連至每一個銲墊；藉 此而讓UBM製程和銲堍製程均可透過電鍍方式來實施。 由於電鑛製程較習知技術所採用之濺鍍製程、蒸鍍製程、 及網印製程均更為簡易且更具有成本效益，因此本發明較 習知技術具有更進步之實用性。 以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之實質技術内容的範圍。本發明之實質技術内容 係、廣義地> 定義於下述之申請專利範圍中，任何他人所完成 張义度適用f國國家揲蝴格m γ 、 ----- ^ S 16068 ---------------------訂--------- (請先閱讀背面之注意事項再填寫本頁) 1529" A7 _B7_ 五、發明說明（9 ) 之技術實體或方法，若是與下述之申請專利範圍所定義者 為完全相同、或是為一種等效之變更，均將被視為涵蓋於 此專利範圍之中。 <請先閲讀背面之注意事項再填寫本頁)Λ529 ^ 9 Α7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs _____ Β7_ V. Description of the Invention (1) [Field of Invention] The present invention relates to a flip-chip semiconductor process technology, particularly to a semiconductor wafer The above-mentioned method for manufacturing an electroplated flip-chip solder bump, which can be used on a semiconductor wafer, forms an under-bump metallization structure (UBM) and a zinc bump (solder bump) on the bottom of the solder bump by electroplating [Background of the Invention] Flip Chip semiconductor packaging technology is an advanced semiconductor packaging technology. The main difference between it and the conventional non-Flip-chip packaging technology is that the semiconductor chip it is packaged in is an upside-down method. Placed on the substrate 'and soldered and electrically connected to the substrate by a plurality of solder bumP 3 Because the flip-chip package structure does not need to use bonding wires that occupy more space to connect the semiconductor The chip is electrically connected to the substrate, so that the overall size can be made thinner and shorter. To bond a solder bump to a wafer ', firstly, a so-called Under Bump Metallization (UBM) structure layer must be formed on a semiconductor wafer as a bottom pad of the solder bump. There are many different patented technologies that can be used to make UBM pads, including the following US patents: • US Patent No. 5,904,859 " FLIP CHIP METALLIZATION "; • US Patent No. 5,902,686 " METHODS FOR FORMING AN INTERMETALLIC REGION BETWEEN A SOLDER BUMP AND AN UNDER BUMP METALLURGY LAYER AND RELATED STRUCTURES "; (Please read the precautions on the back of tt before filling out this page) Binding --------- The standard of the paper size of the thread is applicable to national standards (CNS) A4 specification (210 X 297 mm) 1 16068 Member of the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumption Agreement A7 ___B7_ V. Description of the invention (2) • US Patent No. 6,0 1 5,652 "MANUFACTURE OF FLIP- CHIP DEVICE ”; • US Patent No. 5,1 37,845“ METHOD OF FORMING METAL CONTACT PADS AND TERMINALS ON SEMICONDUCTOR CHIPS "; • US Patent No. 5,773, 3 59 " INTERCONNECTION SYSTEM AND METHOD OF FABRICATION ": • United States Patent No. 5S736,456 "METHOD OF FORMING CONDUCTIVE BUMPS ON DIE FOR FLIP CHIP APPLICATIONS " • U.S. Patent No. 4,927,50 5 "METALLIZATION SCHEME PROVIDING ADHESION AND BARRIER PROPERTIES"; U.S. Patent No. 5,903,058 " CONDUCTIVE BUMPS ON DIE FOR FLIP CHIP APPLICATION ". The technology commonly used in UBM processes includes sputtering ( (sputtering), evaporation, and electroless ρ 丨 ating. However, because the purchase cost of the key equipment and the steaming equipment is quite expensive and the required process steps are more complicated, it is adopted The electroless plating method is more cost-effective. However, one disadvantage of the electroless plating method is that the subsequent soldering process can only be implemented by screen printing method: screen pr 1 nt. 丨 n g); and the screen printing method is also complicated. In addition, one of the other disadvantages of the electroless plating method is that it cannot be used for electroplating gold (Au), tin-lead alloy-based paper is applicable to the country's national bill a: \ S) A4 size (: Π0 y 297 public ^ \ E (m --------------------- order · -------- line (please read the precautions on the back before filling in this page) ) Member of the Intellectual Property Bureau of the Ministry of Economy X Printed by Consumer Cooperatives 45294 9 A7 ___ B7___ V. Invention Description (3) (Sn / Pb) and Copper (Cu), so there are still restrictions on the application of the process. [Overview of the Invention] In view of the above Disadvantages of the known technology, the main purpose of the present invention is to provide a novel method for manufacturing electroplated flip-chip solder bumps, which allows both the UBM process and the solder bump process to be implemented by electroplating. Another aspect of the present invention The purpose is to provide a novel method for manufacturing electroplated multiple crystal solder bumps, which can be implemented more cost-effectively than conventional technologies. According to the above-mentioned purpose, the present invention provides a novel electro-mineralized clad crystal. Wash manufacturing method. The method for manufacturing a plated flip-chip solder bump of the present invention is applicable to a half-conducting wafer. The semiconductor wafer is divided into a plurality of integrated circuit wafers by a predetermined dicing path, and each of the integrated circuit wafers is formed with a plurality of glow pads. The manufacturing method of the electron mirror type clad glow block of the present invention includes the following steps to form a power ore bus It is arranged on the dicing path and is electrically connected to each front pad. (2) A UBM process is performed, in which a plating method is used to apply a first plating current to each solder on the semiconductor wafer through the plating bus. Pads to electroplat the applicable conductive material to each pad, thereby forming a UBM structure layer on each pad: and (3) performing a solder bump process, which uses an electroplating method 'through the electroplating busbar A second plating current is applied to each pad on the semiconductor wafer to electroplat a solder to the UBM Junction® L, Wang Xi column um release mattress on each pad, thereby finishing on each b A fresh piece is formed on the UBM structure layer. -The manufacturing method of the electro-mineralized flip-chip soldering block described above is specifically reported ^ $ 纸 状 度 度 __ 准 （CNS) A_⑽ ---- ^ Sounds in $ 成 一Call 16068 (Please read the back first Please note this page before filling in this page) -------- Order · -------- * 5 ^ Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs f A7 —______ B7___ V. Description of Invention (4) Plating The bus is on the dicing path of the semiconductor wafer, and it is electrically connected to each pad; this allows the UBM process and the solder bump process to be implemented by electroplating. Because the electroplating process is more spattered than the conventional technology, The plating process, the evaporation process, and the screen printing process are all simpler and more cost-effective. Therefore, the present invention has more advanced practicability than the conventional technology. [Brief Description of the Drawings] The essential technical contents of the present invention and its embodiments have been disclosed in detail in the drawings in the drawings attached to this specification. The contents of these drawings are briefly described as follows: FIG. 1 shows a schematic top view of a flip-chip semiconductor wafer; FIG. 2 shows an enlarged schematic view of a specific part of the semiconductor wafer shown in FIG. 1; Figure 3C is a schematic cross-sectional structure diagram, which is used to show the UBM process and the solder bump process in the method for manufacturing electroplated flip-chip solder bumps of the present invention; Figure 4 is a schematic diagram of a three-dimensional structure, which is used to show cutting from a semiconductor wafer The remaining portion of the electroplated busbar on the integrated circuit wafer; Figure 5A is a schematic cross-sectional structure diagram, which shows how the flip-chip underfilling process can additionally provide the electroplated busbar residual portion with an insulating covering effect: FIG. 5B is a schematic cross-sectional structure diagram, which is used to show how the encapsulation system can additionally provide insulation to the remaining portion of the plating busbar—insulation and steep coverage. [Schema number j 丨! Rich Conductor Wafer Paper.p, Degree of National Standard (CNS) A'i Specification (? 1 "| < ..) 97 Public Love: --- ------------ -Install -------- order ---------- line (please read the intention on the back before filling this page> Λ529Α9 a7 _ B7 V. Description of the invention (5) 11 Bulk circuit wafer 20 Cutting line 30 Solder pad 31 UBM structure layer 32 Solder bump 40 Plating bus bar 40a Plating bus residual part 50 Substrate 60 Flip-chip underfill 61 Flip-chip underfill The protruding portion 70 of the adhesive layer 60. The encapsulating gel. [Inventive Embodiment] The following is a detailed description of an embodiment of a method for manufacturing an electroplated flip-chip soldering pad according to the accompanying drawings. FIG. 1 shows a flip-chip semiconductor. A schematic top view of wafer 10. As shown in the figure, this semiconductor wafer 10 is divided into a plurality of wafer regions 11 in advance by a plurality of vertical and horizontal scribe lines 20; each wafer region 11 is used to make a single wafer. Each of the integrated circuit wafers 11 has a plurality of bond pads 30 formed thereon, which are used as internal circuits of the integrated circuit wafers 11. I / O connection points> These solder pads 30 can be aluminum pads manufactured by the aluminum process, or copper pads manufactured by the more advanced copper process. The second circle shows the semiconductor wafer shown in FIG. 1 An enlarged schematic view of a specific part of 10. As shown in the figure, the electroplating type compound crystal soldering block of the present invention is manufactured in accordance with the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (谙 Please read the note on the back first) Please fill in this page again for matters) ·! — 1 I order ------- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 16068 A7 B7 V. Description of the invention (6) The main technical feature of the method is to form an electroplating confluence The row 40 is on the scribe line 20 on the semi-conductor wafer 10; the width of this electroplated bus bar 40 is less than (please read the note on the back before filling this page) and the width of the scribe line 20 is along the scribe line. 20 is extended and connected to each solder pad 30 in the integrated circuit wafer 11. The manufacturing method of the electroplated bus bar 40 can be formed on the cutting line 20 through the definition of a mask using a conventional metallization process. Section 3 A Figures 3 to 3C are schematic diagrams of cross-sectional structures, which are used to display The UBM process and the bump process in the method of manufacturing the electroplated flip-chip solder bumps of the present invention (Note: Figures 3A to 3C here are simplified diagrams, which only show the components related to the present invention. Actual semiconductor crystals The number of components on the circle and the structure may be more complicated.) Figure 3A shows a schematic cross-sectional structure of each pad 30 and its associated plating bus bar 40 shown in Figure 2. The electroplating bus bar 40 is arranged on the surface of the cutting track 20, and A is electrically connected to the fluorene 30, which can be used to send the electroplating current to the welding bar 30 in the electroplating process. Please refer to FIG. 3B. With Thunder Phase: Xiong +, ® Jitian Plating Bus 40 can use a plating method for a UBM process; its sister-in-law & A total of 5f sends a first plating current to the bonding pads 3 through the plating bus bar 40 (the above is wrong and will be suitable as a conductive material for UBM, such as copper (c, nickel (Ni), gold ( (Au), electroplated to the pad 30. In this way, a UBM structure layer 3 I α can be formed on the pad 30. Please refer to 苐 3C 'next step 7 for a solder bump process. Among them, the second plating current / P2 is sent to the bonding pad 30 via the plating bus 40; thereby, a suitable solder is used. "Paper Φ National Standard 聿 ois >., VnnΤήί) * 297 public works ~-^ plated on fresh pads, printed with 16068 45294 9 A7 B7 Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Cooperatives V. Description of the invention (7) to form a solder bump 32 on the solder pad 30. Applicable welding The material gold (Sn / Pb) e solder is, for example, a tin boat when the semiconductor wafer 10 process is completed. Perform all profitable procedures for cutting along the dicing path 20 'to thereby cut the wafer 11 off.% As shown in the fourth circle,' When each integrated circuit chip u has just passed from the first! After the crystal picture 10 is cut off, there will be a part of the electroplated busbars on the edges and the sidewalls (such as the portion designated by the reference numeral 40a in FIG. 4). If the residual portion of the electroplated busbar 40a is not covered with insulation, then It may be easy to cause a short-circuit phenomenon in the internal circuit of the integrated circuit chip 11 or it may easily cause its own erosion to cause damage to the pads 30. However, in the subsequent packaging process, these plating buses can be incidentally added The residual portion 40a provides an insulating covering effect without adding an additional insulating covering step to the overall process. As shown in circle 5A, in the subsequent packaging process, each of the cut integrated circuit chips Π is The inverted method (ie, flip-chip method) is placed on a substrate 50, and is soldered and electrically connected to the substrate 50 through the solder bump 32. Next, a flip-chip underfill process (fUp chip und) erfill) is used to fill a gel filler into the gap between the bottom of the integrated circuit wafer and the upper surface of the substrate 50, thereby forming a flip-chip underfill layer 60. Generally, The flip-chip underfill layer 60 will include a protruding portion 61 on the side of the integrated circuit wafer Η. Since this flip-chip underfill process is a conventional technique, the steps will not be described in further detail below. It can be seen from Figure 5A that the paper size on the bottom of the flip chip is applicable to the Chinese National Standard < CNS) A4 Specification (210 X 297 Public Love) " ~ ^ --- I ---- order ----- line (please read the notes on the back before filling this page) 16068 7 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 __B7_ V. Description of the invention (8) The protruding portion 61 of the adhesive layer 60 is sufficient Incidentally, the remaining portion 40a of the plated bus bar on the integrated circuit wafer 11 is covered, so that it provides an insulating covering effect so that the remaining portion 40a of the plated bus bar does not contact the external environment. Next, as shown in FIG. 5B, 'the next step is to perform an encapsulation process' to form an encapsulation gel 70 to cover the entire building block circuit chip 11. It can be seen from FIG. 5B that the encapsulant 70 can also provide an insulating covering effect on the remaining portion of the recorded bus bar 40a, so that the remaining portion of the key bus bar 40a will not contact the external environment. Therefore, although the method for manufacturing the electroplated flip-chip soldering pad of the present invention may cause the remaining portion of the electroplated bus bar 40 a on the edge and the side wall of the integrated circuit wafer 11, it can be additionally plated in the subsequent packaging process order. The remaining portion of the bus bar 40a provides an insulating covering effect without adding an additional insulating covering step in the overall process. In summary, the present invention provides a novel method for manufacturing electroplated flip-chip solder bumps, which is characterized by forming an electric bus on a dicing path of a semiconductor wafer, and electrically connecting the electroplated bus to each one. Welding pads; this allows both UBM and soldering processes to be implemented by electroplating. Since the electric ore process is simpler and more cost-effective than the sputtering process, evaporation process, and screen printing process used in the conventional technology, the present invention has more advanced practicability than the conventional technology. The above descriptions are merely preferred embodiments of the present invention, and are not intended to limit the scope of the essential technical content of the present invention. The essential technical content of the present invention is broadly defined in the scope of the following patent applications. Anyone who has completed the Zhang Yidu application applies to the country's national standard m γ, ----- ^ S 16068 ----- ---------------- Order --------- (Please read the notes on the back before filling out this page) 1529 " A7 _B7_ V. Description of the invention (9) If the technical entity or method is completely the same as defined in the scope of patent application described below, or an equivalent change, it will be considered to be covered by this patent scope. < Please read the notes on the back before filling this page)
裝------I 訂---------線 經濟部智慧財產局員工消費合作杜印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 9 16068Packing ------ I order --------- Consumer cooperation with employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Du printed paper size applicable to China National Standard (CNS) A4 (210 X 297 mm) 9 16068