經濟部智慧財產局員工消費合作杜印製 483131 A7 -------- B7 : ----—-_ 五、發明說明（1 ) [發明領域] 本發明係有關於一種半導體封裝技術，特別是有關於 一種露墊型半導體裝置至印刷電路板藕接方法，其可用以 將一具有外露置晶墊的半導體裝置，例如為四方形平面無 導腳式（Quad Flat Non-leaded，QFN)半導體裝置，藉由表面 藕接技術（Surface-Mount Technology, SMT)而藕接至印刷 電路板（printed circuit board, PCB)上，但不會使得鲜結於 印刷電路板上的半導體裝置產生浮銲現象。 [發明背景]Consumer Cooperation of Intellectual Property Bureau of the Ministry of Economic Affairs Du printed 483131 A7 -------- B7: ---------_ V. Description of Invention (1) [Field of Invention] The present invention relates to a semiconductor packaging technology In particular, it relates to a method for connecting an exposed pad semiconductor device to a printed circuit board, which can be used to connect a semiconductor device with an exposed crystal pad, such as a quad flat non-leaded (QFN) ) The semiconductor device is connected to a printed circuit board (PCB) by Surface-Mount Technology (SMT), but it will not cause the floating of the semiconductor device on the printed circuit board. Welding phenomenon. [Background of the Invention]
露墊型半導體裝置為一種以露墊方式封裝的半導體封 裝單元，其特點在於其中所採用之導線架（leadframe)的置 晶墊（die pad)的背面係外露於封裝膠體的底部外面。於採 用表面藕接技術來將露墊型半導體裝置藕接至印刷電路板 上時，其即可將外露之置晶墊直接銲結至印刷電路板上的 一接地面（ground Plane)上，藉以使得其中所包覆之半導體 晶片具有更佳之接地效果。以下即配合所附圖式之第jA 至1E圖，以圖解方式簡述一種習知之露墊型半導體裝置 至印刷電路板藕接方法。 請首先參閱第1A圖和第1B圖，此習知之露墊型半導 體裝置至印刷電路板藕接方法係用以將一露墊型半導體裝 置1 0，例如為一 QFN式半導體裝置，藕接至一印刷電路 板20 〇 此露墊型半導體裝置10的内部結構包含：⑴一導線 架丨1，其具有一置晶墊12及一組導腳13; (ii)一半導體晶 —-----------^---- (請先閱讀背面之注意事項寫本頁)The exposed pad type semiconductor device is a semiconductor packaging unit packaged in an exposed pad manner, which is characterized in that the back surface of the die pad of the lead frame used therein is exposed outside the bottom of the packaging gel. When surface-bonding technology is used to connect exposed pad-type semiconductor devices to a printed circuit board, the exposed pad can be directly soldered to a ground plane on the printed circuit board. This makes the semiconductor wafers covered therein have better grounding effect. The following is a schematic description of a conventional open pad type semiconductor device to printed circuit board bonding method in conjunction with the jA to 1E diagrams of the attached drawings. Please refer to FIG. 1A and FIG. 1B first. The conventional method for connecting an exposed pad type semiconductor device to a printed circuit board is to connect an exposed pad type semiconductor device 10, such as a QFN type semiconductor device, to A printed circuit board 20. The internal structure of this exposed pad type semiconductor device 10 includes: a lead frame 1 having a crystal pad 12 and a set of guide pins 13; (ii) a semiconductor crystal —---- ------- ^ ---- (Please read the notes on the back to write this page)
--訂i------線J 本紙張尺度· t^iii^NS)A4規格（21〇 X 297公釐了 1 16261 483131 A7 —_B7 五、發明說明（2 片14 ’其係安置於置晶塾12之正自m上並藉由—組 鲜線15❿電性連接至導腳13之正* i3a上；以及㈣— 封裝膠體16，其用以包覆半導體晶片14及導線架U，但 使得置晶塾12之背面12b及導腳13之背面⑶外露於 裝膠體16的底部外面。 由於此露塾型半導體裝置1〇之置晶塾12係外露於封 ^膠體16之底部外面，因此其亦f稱為，，露墊型，，㈣_ 节d _封裝單元；且由於露塾型半導體裝置i。之導腳 13之實體部分係整個包覆於封裝膠體16之中，僅其背面 b外路於封裝膝體16之底部外面，因此其亦稱為”無導 腳式（non-leaded，或 ieacjless)封裝單元。 P刷電路板20包括—基板21、_絕緣保護層、— 接地面（ground Plane)23、以及複數料電指（士心叫_ condiumve flngers)24。接地面23用以作為露墊型半導體 =置1〇之外露置晶| 12的安置區域，且其面積大致等於 魯露置晶塾12的面積；而導電指24則為印刷電路板2〇 上的電性連接點，其面積大致等於露塾型半導體裝置“ 上的各個導腳13之外露表面13b的面積。因此接地面2 的黏銲面積係遠大於各個導電指24的黏鲜面積。 清接著參閱第1C圖，下一個步驟為進行一塗焊程序 (solde卜pasting process)，藉以將—銲料塗佈於接地面u #各個導電和24之表面上。由於接地面23的黏鲜面積缝 大於各個導電指24的黏銲面積，因此會於接地面23上形 _成=面積之焊塊3!，^各個導電指24上則形成一小 本^^尺度適财關家標準（CNSM4規格（210T297公£ ’ 2 16261--Order i ------ line J Paper size t ^ iii ^ NS) A4 size (21〇X 297mm 1 16261 483131 A7 —_B7 V. Description of the invention (2 pieces 14 'It is placed It is placed on the positive electrode m of the crystal chip 12 and is electrically connected to the positive pin * i3a of the guide pin 13 through a set of fresh wires 15; and ㈣— a packaging gel 16 for covering the semiconductor wafer 14 and the lead frame U However, the back surface 12b of the crystal chip 12 and the back surface ⑶ of the guide pin 13 are exposed outside the bottom of the mounting body 16. Because of the exposure of the semiconductor device 10, the position of the crystal unit 12 is exposed outside the bottom of the sealing body 16. Therefore, it is also called f, exposed pad type, ㈣_ section d _ packaging unit; and due to exposed type semiconductor device i. The solid part of the lead 13 is entirely enclosed in the encapsulation gel 16, only The back side b is external to the bottom of the package knee 16, so it is also referred to as a "non-leaded, or ieacjless" packaging unit. The P brush circuit board 20 includes-a substrate 21, an insulation protection layer,- Ground plane (ground plane) 23, as well as multiple electric fingers (student heart call _ condiumve flngers) 24. Ground plane 23 is used as an exposed pad type semiconductor = Setting area other than 10; and the area of the placement area is approximately equal to the area of Lulu placement area 12; and the conductive finger 24 is the electrical connection point on the printed circuit board 20, and the area is approximately equal to The area of the exposed surface 13b of each of the guide pins 13 on the exposed semiconductor device ". Therefore, the bonding area of the ground plane 2 is much larger than that of each conductive finger 24. Next, refer to FIG. 1C, the next step is A soldering process is performed to apply solder to the surfaces of the conductive surfaces 24 and 24. Since the sticky area of the ground surface 23 is larger than the bonding area of each conductive finger 24, Therefore, a solder bump 3 of area = area will be formed on the ground plane 23, and a small volume will be formed on each conductive finger 24. ^ Dimensions are suitable for financial standards (CNSM4 specification (210T297 KRW '2 16261)
^-------- C請先閱讀背面之注意事項再填寫本頁) t-— 線----- -^1 ϋ - A7 B7 五、發明說明（ 經濟部智慧財產局員工消費合泎fi印製 面積之銲塊32。此塗銲程戽+ 序疋成後斤形成之大面積銲塊 、 糸大致平齊於各個小面積銲塊32的上表面。 :接著參閱第1DW，下一個步驟為進行一表面竊接 〆、百先將露塾型半導體裝置10安置於印刷電路板 上，並使得外露置晶塾12對齊至接地面23，並使得各 個^腳13分別對齊至對應之導電指24(亦即將外露置晶塾 12安置於大面積銲塊31上，並將各個導腳η分別安置於 各個小面積銲塊3 2上）。 接著進行一迴銲程序（solder_reflow pr〇cess)，藉以將 大面積鮮塊3 1迴銲於接地面23與外露置晶塾之間，並 同時將小面積銲塊32迴銲於各個導腳13與對應之導電指 24之間。此即可將外露置晶塾12藉由迴料之大面積録 塊31而銲結至接地面23,並同時將各個導腳^藉由迴銲 後之小面積録塊32而銲結至導電指24。此即完成露塾型 半導體裝置10至印刷電路板20的藕接程序。 然而由於迴銲程序中，熔化之銲料會向中心聚縮，因 此會使得迴銲後的銲塊的厚度會略為向上隆起；且面積愈 大之銲塊’其向上隆起的程度也就愈大。 因此如第1E圖所示，迴銲後之大面積銲塊31的隆起 南度會大於迴靜後之小面積銲塊32的隆起高度，致使露塾 型半導體裝置10中銲結於接地面23上的部分被向上推 擠，產生所謂之浮銲現象。但由於迴銲後之小面積銲塊32 的隆起高度並不大，因此上述之浮銲現象將導致導腳13 被向上拉升，因而可能致使導腳13未能有效地銲結至導電 事 t 訂 線 16261 A7 B7 五、發明說明（4 ) 才曰24上的銲塊32，而形成虛銲或斷鲜狀態（如第κ圖中 之標號4 0所指之部位βΛ磁 型半導體裝置Π):Γ 態之導腳)，使得露墊 =導體裝置Π)與印刷電路板2G所組合而成之電路模組 /、有不佳之銲結品質性及可靠度。 相關之專利技術例如包括彳日本專利了削 ”flat PACKAGE LSI，，。此 A2 ^ ^ 此專利技術揭露了一種無導腳式 、，Ό構，其特點在於形成定位插梢（positional I)於封裝單元之底部，藉此而使得封裝單元可牢固地安 置於印刷電路板的定位上。然而，此專利技術的一項缺點 在於定位插梢的製作輕為雜 、' 乍1乂為困難，使得整體製程較為不便且 不符合成本效益。 [發明概述] a鐾於以上所述習知技術之缺點，本發明之主要目的便 =於：：一種新的露墊型半導體裝置至印刷電路板藕接 ^法，其可防止前述之浮銲問題。 罟“之另目的在於提供一種新的露墊型半導體裝 露塾型半導體裝置牢可不必使用定位插梢來使得 牛口地文置於印刷電路板的定位上。 X 另目的在於提供一種新的露墊型半導體裝 置至印刷電路板藕拄古 方法’其可使得露墊型半導體裝置盘 印刷電路板之間的藕接且 幾，、有更隹之品質性及可靠度。 根據以上所述之日 ^ ^ W 2, 、，本發明即提供了 一種新的露墊 “導體裝置：印刷電路板藕接方法。 本發日月之稿1方法的特點在於形成禕數個黏鋥,HMi π 本紙張尺度賴巾關家辟 4 16261 裝 A7 五、發明說明（5 ) 於印刷電路板的置墊區中，以藉由此些黏鲜性通孔而將輝 料從印刷電路板的下表面垂直向上迴鲜至印刷電路板的上 表面，藉此而將露墊型半導體裝置的外露置晶塾鲜結至印 刷電路板上。由於本發明之藕接方法所採用之鲜塊並非如 習知技術般所使用之大面積銲塊，因此即不會使得録結於 印刷電路板上的露墊型半導體裝置產生浮銲現象。本發明 之藕接方法因此可使得露墊型半導體裝置牢固地竊接於印 刷電路板的定位上。 [圖式簡述] 本發明之實質技術内|及其實施 <列已用圖解方式詳細 揭露繪製於本說明書所附之圖式之中。此些圖；式之内容簡 述如下： 第1A至1E圖（先前技術）為剖面結構示意圖，其中顯 示一習知之露墊型半導體裝置至印刷電路板藕接方法中的 各個程序步驟； 第2 A至2E圖為剖面結構示意圖，其中顯示本發明之 露墊型半導體裝置至印刷電路板藕接方法中的各個程序步 驟。 [圖式標號說明] (請先閱讀背面之注意事 丨裝 項寫丄 寫本頁) I. 10 露墊型半導體裝置 11 導線架（leadframe) 12 置晶墊（die pad) 12a 置晶塾12之正面 12b 置晶墊12之背面 13 導腳 13a 導腳13之正面 13b 導腳13之背面 14 半導體晶片 15 銲線 本紙張尺度適用中國國家標準（CNS)A4規格⑵Q x 297公爱γ 16261 483131 A7 五、發明說明（6 ) 16 封裝膠體 基板 接地面 大面積銲塊 斷銲部位 110 置晶墊 110b置晶墊100之 免〇半導體晶片 150 封裝膠體 經濟部智慧財產局員工消費合作钍印製 20 22 24 32100 印刷電路板 絕緣保護層 導電指 +面積銲塊 露墊型半導體裝置 110a置晶塾1〇〇之正面 120 外導腳 140 銲線 200印刷電路板 200a印刷電路板200的卜矣& 亡 叼上表面200b印刷電路板2〇〇的下表面 201 頂部銲料罩幕 A ^ 202底部銲料罩幕 210 置墊區 m 4 211黏銲性通孔 · 211a黏銲性通孔211的頂端2nb黏銲性通孔2ιι的底端 212黏銲層 231第一銲塊 232 第二銲塊务明實施例] 以下即配合所附圖式之第2A至2E圖，詳細揭露說, 本發明之詩型半導體裝置至印刷電路板藕接方法之1 施例。須百先注意的-點是，第2A至2E圖均為簡化之3 意圖式，其僅顯示與本發明有關之元件，且所顯示之元令 並非以實際之數目及尺寸比财製；其具體實施時之元利 佈局形態可能更為複雜。 請首先參閱第2A圖，本發明之藕接方法係用以將一 露墊型半導體裝置1〇〇，例如為一 qfn式半導體裝置 ‘紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱 21 23 31 40 背面 16261 -1------------壯衣·---------訂------I I I (請先閱讀背面之注意事項再填寫本頁) 483131 A7^ -------- C Please read the notes on the back before filling in this page) t --- line ------^ 1 ϋ-A7 B7 V. Description of Invention (Consumer Consumption of Intellectual Property Bureau, Ministry of Economic Affairs) Combined with the printed area of the solder block 32. This coating welding process 戽 + sequence after the formation of the large-area solder block, 糸 is approximately flush with the upper surface of each small-area solder block 32 .: Then refer to Section 1DW, The next step is to perform a surface tapping, place the exposed semiconductor device 10 on the printed circuit board, and align the exposed crystal chip 12 to the ground plane 23, and align each foot 13 to the corresponding one. The conductive fingers 24 (that is, the exposed crystal chip 12 is placed on the large-area solder bump 31, and each guide pin η is placed on each of the small-area solder pad 32). Then, a reflow process (solder_reflow pr) is performed. cess), so that large-area fresh blocks 31 are re-soldered between the ground plane 23 and the exposed crystal cymbal, and at the same time, small-area solder blocks 32 are re-soldered between each guide pin 13 and the corresponding conductive finger 24. This Then, the exposed crystal chip 12 is welded to the ground surface 23 by the large-area recording block 31 of the return material, and each guide pin is simultaneously ^ Bonded to the conductive fingers 24 through the small-area recording block 32 after reflow. This completes the welding process of the exposed semiconductor device 10 to the printed circuit board 20. However, due to the reflow process, the molten solder will Condensing to the center, so that the thickness of the solder bump after reflow will rise slightly; and the larger the area of the solder bump, the greater the degree of upward bump. Therefore, as shown in Figure 1E, after reflow The bulge south of the large-area solder bump 31 will be greater than the bulge height of the small-area solder bump 32 after re-quieting, so that the portion of the exposed semiconductor device 10 welded to the ground plane 23 will be pushed upward, resulting in the so-called Floating welding phenomenon. However, since the bump height of the small-area solder bump 32 after reflow is not large, the above-mentioned floating welding phenomenon will cause the guide pin 13 to be pulled upward, which may cause the guide pin 13 to fail to be effectively welded. To the conductive matter t, order line 16261 A7 B7 V. Description of the invention (4) Welding block 32 on 24 only, and it is in the state of false welding or broken (as indicated by the number 40 in the figure κ βΛ magnetic type) Semiconductor device Π): Γ state guide pin), so that exposed pad = conductor device Π ) Combined with printed circuit board 2G circuit module / / Poor solder joint quality and reliability. Relevant patented technologies include, for example, the Japanese patent "flat pack LSI". This A2 ^ ^ This patented technology discloses a non-lead-type, self-contained structure, which is characterized by the formation of positional pins (packages) in the package. The bottom of the unit, so that the packaging unit can be firmly positioned on the positioning of the printed circuit board. However, one disadvantage of this patented technology is that the fabrication of the positioning pins is light and complicated, and it is difficult to make the whole. The manufacturing process is inconvenient and not cost-effective. [Summary of the Invention] a. In view of the shortcomings of the conventional technology described above, the main purpose of the present invention is to :: a new open-pad semiconductor device to the printed circuit board ^ This method can prevent the above-mentioned floating soldering problem. Another purpose is to provide a new exposed pad type semiconductor mounted exposed type semiconductor device, which can eliminate the need to use positioning pins to make the tongue and mouth on the printed circuit board. Positioning. Another purpose of X is to provide a new method of exposing pad-type semiconductor devices to printed circuit boards, which can make the connection between exposed pad-type semiconductor device disks and printed circuit boards more reliable, Reliability. According to the above-mentioned dates ^ ^ W 2,, the present invention provides a new exposed pad "conductor device: a printed circuit board bonding method. The feature of this method is to form several adhesives. H, HMi π This paper size Lai Jiaguan Guan Jiapi 4 16261 Install A7 V. Description of the invention (5) In the pad area of the printed circuit board to remove the bright material from the printed circuit through these sticky through holes The lower surface of the board is refreshed vertically upward to the upper surface of the printed circuit board, thereby exposing the exposed crystals of the exposed pad type semiconductor device to the printed circuit board. Because of the fresh block used in the bonding method of the present invention, It is not a large-area soldering pad like the conventional technology, so it does not cause the floating pad semiconductor device recorded on the printed circuit board to have a floating solder phenomenon. The bonding method of the present invention can therefore make the exposed pad semiconductor The device is securely stolen on the positioning of the printed circuit board. [Brief Description of the Drawings] Within the essential technology of the present invention and its implementation, the columns have been disclosed in detail in the drawings attached to this specification. These pictures; It is as follows: Figures 1A to 1E (prior art) are schematic cross-sectional structure diagrams, which show each program step in a conventional method of bonding exposed semiconductor devices to printed circuit boards; Figures 2A to 2E are schematic diagrams of cross-sectional structures. The steps of the method for connecting the exposed pad type semiconductor device to the printed circuit board according to the present invention are shown in the figure. [Illustration of Symbols] (Please read the precautions on the back 丨 write this item and write this page) I. 10 露Pad type semiconductor device 11 leadframe 12 die pad 12a front face 12b front face 12b backside 13 guide pin 13a front side 13 guide 13b back side 14 semiconductor wafer 15 Welding wire This paper size is in accordance with Chinese National Standard (CNS) A4 specification⑵Q x 297 public love 16261 483131 A7 V. Description of the invention (6) 16 Large area of solder bumps on the ground surface of the encapsulation substrate Free of die pad 100. Semiconductor wafer 150 Package colloid Ministry of Intellectual Property Bureau Employees' consumer cooperation 钍 Printed 20 22 24 32 100 Printed circuit board insulation protection layer Conductive finger + area solder bump exposed Type semiconductor device 110a with front surface of wafer 100, outer guide pin 140, bonding wire 200, printed circuit board 200a, printed circuit board 200, & upper surface 200b, lower surface of printed circuit board 200, top solder Mask A ^ 202 Bottom solder mask 210 Pad area m 4 211 Adhesive vias 211a Top of 211a Adhesive vias 211 2nb Adhesive vias 2m Bottom end 212 Adhesive layer 231 First solder bump 232 Second soldering block embodiment] The following is a detailed description of the first embodiment of the method for bonding a poetic semiconductor device to a printed circuit board according to the drawings 2A to 2E. The first thing to note is that Figures 2A to 2E are simplified 3 intent formulas, which only show elements related to the present invention, and the displayed order is not based on the actual number and size than the financial system; The implementation of the Yuanli layout may be more complicated. Please refer to FIG. 2A first. The coupling method of the present invention is used to convert an exposed pad type semiconductor device 100, such as a qfn type semiconductor device. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297). Gongai 21 23 31 40 back 16261 -1 ------------ strong clothing --------- order ------ III (Please read the precautions on the back first (Fill in this page again) 483131 A7
483131 經濟部智慧財產局員工消費合作社印制衣 A7 五、發明說明（8 ) 銲墊220上’並同時亦塗佈於各個黏銲性通孔211的底端 211b;藉此而形成一第一銲塊231於信號銲墊22〇上，且 开> 成一第二銲塊232於各個黏銲性通孔211的底端2iib 上。由於此塗銲程序係採用習知技術，因此以下將不對其 中之細節步驟作進一步詳細之說明。 請接著參閱第2D圖，下一個步驟為將露墊型半導體 ^置100安置於印刷電路板2〇〇上，並使得其外露之置晶 I 110對齊及壓置於印刷電路板200的置墊區210，且使 得其外導腳120對齊至信號銲墊220且壓置於第一銲塊 231 上。 請接著參閱第2E圖，下一個步驟為進行一迴銲程序 (solder-reflow process)，藉此而同時迴銲第一銲塊231和 第二銲塊232。此迴銲程序會使得第一銲塊231因熔化而 自行迴銲至信號銲墊220和外導腳120的接觸表面上，因 此而將外導腳120銲結至信號銲墊220 ;並同時使得第二 1塊232因熔化而自行迴銲至黏銲層212的所有表面上， 因此將致使熔化之第二銲塊232自行垂直向上流至黏銲性 通孔211的頂端211a，並進而黏銲至露墊型半導體裝置 的置晶塾110的背面ll〇b上，因此而將露墊型半導體裝置 1〇〇銲結至印刷電路板200。此即完成露墊型半導體裝置 1〇〇藕接至印刷電路板200的表面藕接程序。 相較於習知技術’本發明的特點在於藉由黏銲性通孔 211而將銲料（即第二銲塊232)從印刷電路板2〇〇的下表面 200b垂直向上迴銲至印刷電路板200的上表面2〇〇a，因此 ----- - -- ^ ------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 8 16261 483131 A7 B7 五、發明說明（9 ) 可使得露墊型半導體裝置100的外露置晶墊110向下銲結 至印刷電路板200上。由於本發明所採用之銲塊並不像習 知技術所使用之大面積銲塊，因此即不會使得銲結於印刷 電路板上的露墊型半導體裝置產生浮銲現象。本發明之竊 接方法因此可使得露墊型半導體裝置牢固地藕接於印刷電 路板的定位上。 以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之實質技術内容的範圍。本發明之實質技術内容 係廣義地定義於下述之申請專利範圍中。任何他人所完成 之技術實體或方法，若是與下述之申請專利範圍所定義者 為完全相同、或是為-種等效之變更，均將被視為涵蓋於 此專利範圍之中。483131 Printed clothing A7 of the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (8) The pads 220 'are also coated on the bottom end 211b of each adhesive soldering through hole 211; thereby forming a first The soldering pad 231 is on the signal soldering pad 22 and is opened> to form a second soldering pad 232 on the bottom end 2iib of each of the adhesive soldering through holes 211. Since this coating and welding procedure uses conventional techniques, detailed steps will not be described in detail below. Please refer to FIG. 2D. The next step is to place the exposed pad semiconductor 100 on the printed circuit board 200, and align the exposed die I 110 and press the pad on the printed circuit board 200. Region 210, so that its outer guide pin 120 is aligned with the signal pad 220 and pressed onto the first solder bump 231. Please refer to FIG. 2E. The next step is to perform a solder-reflow process to re-solder the first solder bump 231 and the second solder bump 232 at the same time. This re-welding procedure will cause the first solder bump 231 to be re-welded to the contact surface of the signal pad 220 and the outer guide pin 120 by melting, so that the outer guide pin 120 is welded to the signal pad 220; and at the same time, The second block 232 re-solders itself to all surfaces of the adhesive layer 212 due to melting, so the molten second solder block 232 will flow vertically upward to the top end 211a of the adhesive through-hole 211 by itself, and then stick to the solder On the back surface 110b of the wafer-type semiconductor device 110, the wafer-type semiconductor device 100 is soldered to the printed circuit board 200. This completes the surface bonding process of connecting the exposed pad type semiconductor device 100 to the printed circuit board 200. Compared with the conventional technology, the present invention is characterized in that the solder (ie, the second solder bump 232) is re-soldered vertically from the lower surface 200b of the printed circuit board 200 to the printed circuit board through the adhesive bonding via 211. The upper surface of 200 is 200a, so -------^ ------- (Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 Specifications (210 X 297 mm) 8 16261 483131 A7 B7 V. Description of the invention (9) The exposed crystal pad 110 of the exposed pad type semiconductor device 100 can be soldered down to the printed circuit board 200. Since the solder bump used in the present invention is not a large-area solder bump used in the conventional technology, the floating pad type semiconductor device that is bonded to a printed circuit board does not cause floating soldering. The stealing method of the present invention therefore enables the exposed pad type semiconductor device to be firmly attached to the position of the printed circuit board. The above descriptions are merely preferred embodiments of the present invention, and are not intended to limit the scope of the essential technical content of the present invention. The essential technical content of the present invention is broadly defined in the scope of the following patent applications. Any technical entity or method completed by another person, if it is exactly the same as defined in the scope of patent application described below, or an equivalent change, will be deemed to be covered by this patent scope.
^---------—訂 -------ί ^ - (請先閱讀背面之產事項III寫本頁) I 經濟部智慧財產局員工消費合作社印製 9 16261^ ----------- Order ------- ί ^-(Please read the Product Matters on the back III to write this page) I Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Cooperatives 9 16261