A7 B7 466727 5489twf.DOC/005 五、發明說明（/ ) 本發明是有關於一種封裝基板結構與封裝方法，且特 別是有關於一種可防止元件位置區域上的焊罩層產生裂 縫的基板結構與封裝製程。 + 積體電路之封裝（Package)，其目的在於提供晶粒（Die) 與印刷電路板（Printed Circuit Board, PCB)或其他適當元 件之間電性連接的媒介、以及保護晶片’爲製作積體電路 成品的最後步驟。就一般球格陣列封裝製程而言，在封裝 件的組裝（assembling)的過程中，首先將晶粒配裝至基板之 一表靣上的個別元件位置（device site)，並進行晶粒與基板 的電性連接，之後以塑膠材質，進行晶粒的封膠製程 (encapsulating process)，接著，於基板的另一表面進行植球 製程，形成球格陣列之焊接球。之後再進行沖壓分離製程 (singulation process)，將基板切開，以使每一經過封膠製程 之晶粒分離開，完成球格陣列封裝件的組裝。 而在習知之基板的兩表面上，均會形成有一層焊罩層 (solder mask layer)，其目的是在保護基板上的線路區域， 以免除線路區域在封裝製程中遭受不必要的蝕刻侵害，並 可防止線路區域在植球製程以及電鍍過程中受到污染，並 且有效隔離各個線路區域，防止產生不必要電性導通，使 基板具有良好的可靠度及製造良率，以利後續進行之封裝 製程。 通常基板中用於黏著晶粒之元件位置爲一矩形，元件 位置僅以其矩形之四角與基板相連。一般用於進行沖壓分 離製程的沖壓分離器具爲直角截角刀具(right angle cutting 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐） (請先閱讀背面之注意事項再填寫本頁) \..衣----II 訂-------線 — 經濟部智慧財產局員工消費合作社印製 6 72 7 5489twf.DOC/005 五、發明說明（夂） edge)，其直角截角相對應於元件位置之每一角，在進行沖 壓分離製程，經由切割元件位置之四角，將元件位置與基 板分離開來。 ’ 在進行一連串封裝製程過程中，各項處理步驟所造成 .的外來應力，會在基板邊綠上的焊罩層上產生裂縫，並且 裂縫會由基板邊緣，經由基板與元件位置之連接處向元件 位置延伸=而暴露元件位置上的線路區域，此外在進行封 裝製程過程中的熱應力也會造成焊罩層產生如同上述的裂 縫。由於在焊罩層上產生裂縫，因此會致使水氣或是污染 物沿裂縫進入線路區域，污染封裝元件，降低封裝件之可 靠度（reliability)，並且侵入之水氣會在後續高溫中導致焊罩 層裂開，降低封裝件的良率。 因此本發明就是在提供一種可防止元件位置區域上的 焊罩層產生裂縫的基板結構。此結構包括一基板，此基板 具有一上表面與一下表面，且基板還區分成一周邊區·域與 一元件位置區域，而基板之上表面與下表面上形成有一層 焊罩層，而焊罩層並裸露部份基板之上表面與下表面形成 一裸露區域，此裸露區域將焊罩層分隔成兩互不相連之一 周邊區域焊罩層與一元件位置區域焊罩層。 本發明還提供一種可防止焊罩層產生裂縫之封裝製 程，此方法簡述如下：首先提供一基板，此基板具有一上 表面與一下表面，且基板還包括一周邊區域與一元件位置 區域。之後，於基板之上表面與下表面形成一焊罩層，此 焊罩層裸露部份基板之上表面與下表面形成一裸露區域， 4 (請先閱讀背面之注意事項再填寫本頁) 、衣----；.----訂---------線.. 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用令國國家標準（CNS>A4規格（210 X 297公釐） 4 6 6 72 7 54S9twf.D〇C/005 Α7 __Β7_____ 五、發明說明（今） 其中裸露區域將焊罩層區成爲一周邊區域焊罩層與一元件 位置區域焊犟層。接著於基板之上表面的元件位置區域進 行一晶粒黏著製程。繼之，於基板之上表面的元件位置區 域進行一封膠製程及植球製程。續之進行一沖壓分離製 程，以分離元件位置區域與周邊區域。 依照本發明的一較佳實施例，此裸露區域包圍元件位 置區域，以使位於元件位置區域上的焊罩層與位於周邊區 域上的焊罩層彼此不相連，因此進行後續晶粒黏著、打導 線製程、封膠製程以及植球製程等步驟時，因爲作業過程 中造成焊罩層由基板邊緣產生裂縫，或是熱製程所產.生之 熱應力釋放不均造成之裂縫，會因爲元件位置區域焊罩層 與周邊區域焊罩層互不相連，而不會向元件位置區域延 伸，甚至延伸至完成封膠之封裝件中。所以可以解決習知 因爲焊罩層在封裝製程中產生的裂縫，導致封裝件之可靠 度下降，良率降低等問題。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 、 細說明如下： 圖式之簡單說明： 第1Α圖至第1Β圖，所繪示爲根據本發明之基板部份 上視圖： 第2圖爲完成元件封裝製程之基板之上表面的上視 圖； 第3圖爲完成元件封裝製程之基板之下表面的上視 5 ^紙張尺度適用^國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 衣"n ^ 1-· ϋ I ^ · Ε> ϋ I .1 ^ I I ^ ^ ^ n I ^ ^ It ^ t— n- ^ ^ ^ n n ^ tt I _ 466727 5489twf.DOC/005 經濟部智慧財產局員H消費合作社印製 B7 五、發明說明（f) 圖；A7 B7 466727 5489twf.DOC / 005 V. Description of the Invention (/) The present invention relates to a package substrate structure and a packaging method, and in particular to a substrate structure and a substrate structure that can prevent cracks in a solder mask layer on a component location area. Packaging process. + Package of the integrated circuit, the purpose of which is to provide a medium for the electrical connection between the die and the printed circuit board (PCB) or other appropriate components, and to protect the chip. The final step in the finished circuit. As for the general ball grid array packaging process, during the assembly of the package (assembling), the die is first assembled to an individual device site on a surface of one of the substrates, and the die and the substrate are carried out. After the electrical connection is performed, a plastic material is used to perform an encapsulating process of the crystal grains. Then, a ball implantation process is performed on the other surface of the substrate to form a solder ball of a ball grid array. Then, a singulation process is performed to cut the substrate so that each die after the sealing process is separated to complete the assembly of the ball grid array package. A solder mask layer will be formed on both surfaces of the conventional substrate, the purpose of which is to protect the circuit area on the substrate to prevent the circuit area from being subjected to unnecessary etching damage during the packaging process. It can prevent the circuit area from being contaminated during the ball-planting process and the plating process, and effectively isolate each circuit area, prevent unnecessary electrical continuity, and make the substrate have good reliability and manufacturing yield to facilitate subsequent packaging processes. . Generally, the position of the component for attaching the die in the substrate is a rectangle, and the component position is connected to the substrate only by the four corners of the rectangle. The punching and separating device generally used for punching and separating processes is a right angle cutting tool (right angle cutting 3) This paper size applies to China National Standard (CNS) A4 (210 χ 297 mm) (Please read the precautions on the back before filling (This page) \ .. clothing ---- Order II ----------- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6 72 7 5489twf.DOC / 005 V. Description of Invention (夂) edge), The right-angle truncation angle corresponds to each corner of the component position. In the punching separation process, the component position is separated from the substrate by cutting the four corners of the component position. '' During a series of packaging processes, the external stress caused by various processing steps will cause cracks on the solder mask layer on the green side of the substrate, and the cracks will run from the edge of the substrate through the connection between the substrate and the component location. Extending the component position = Exposing the circuit area at the component position. In addition, the thermal stress during the packaging process will cause the solder mask layer to generate cracks as described above. Since cracks are generated on the solder mask layer, water vapor or pollutants will enter the circuit area along the cracks, contaminating the package components, reducing the reliability of the package, and the invading water and gas will cause welding in the subsequent high temperature. The cap layer cracks, which reduces the yield of the package. Therefore, the present invention is to provide a substrate structure which can prevent cracks in the solder mask layer on the component location area. This structure includes a substrate, the substrate has an upper surface and a lower surface, and the substrate is further divided into a peripheral area · area and a component location area, and a solder mask layer is formed on the upper surface and the lower surface of the substrate, and the solder mask And exposed portions of the upper surface and the lower surface of the substrate to form an exposed area, which separates the solder mask layer into two mutually unconnected peripheral region solder mask layers and a component location region solder mask layer. The present invention also provides a packaging process that can prevent cracks in the solder mask layer. The method is briefly described as follows: First, a substrate is provided, the substrate has an upper surface and a lower surface, and the substrate further includes a peripheral area and a component location area. After that, a solder mask layer is formed on the upper and lower surfaces of the substrate. This solder mask layer exposes an exposed area on the upper and lower surfaces of the substrate. 4 (Please read the precautions on the back before filling in this page). Clothing ----; .---- Order --------- line: printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives, this paper applies the national standard of the country (CNS > A4 specification (210 X 297 mm) 4 6 6 72 7 54S9twf.D0C / 005 Α7 __Β7 _____ V. Description of the invention (today) The exposed area will change the solder mask layer area into a peripheral region solder mask layer and a component location solder layer. Then A die bonding process is performed on the component position area on the upper surface of the substrate. Next, a glue process and a ball implantation process are performed on the component position area on the upper surface of the substrate. A stamping and separation process is performed to separate the component positions. According to a preferred embodiment of the present invention, the exposed area surrounds the component location area so that the solder mask layer located on the component location area and the solder mask layer located on the peripheral area are not connected to each other, so the subsequent steps are performed. Die adhesion , Wire making process, sealing process, and ball-planting process, because the solder mask layer is cracked by the edge of the substrate during the operation, or caused by the thermal process. Cracks caused by uneven thermal stress release will be caused by The solder mask layer in the component location area and the solder mask layer in the peripheral area are not connected to each other, and will not extend to the component location area, or even into the package that completes the sealing. Therefore, it is possible to solve the problem that the solder mask layer is generated during the packaging process. Cracks, leading to problems such as a decrease in the reliability of the package, a decrease in the yield, etc. In order to make the above and other objects, features, and advantages of the present invention more obvious and easier to understand, a preferred embodiment is given below with the accompanying The drawings are detailed and detailed as follows: Brief description of the drawings: Figures 1A to 1B show the top view of the substrate part according to the present invention: Figure 2 is the substrate on which the component packaging process is completed Top view of the surface; Figure 3 is a top view of the lower surface of the substrate after the component packaging process is completed 5 ^ Paper size applies ^ National Standard (CNS) A4 specification (210 X 297 mm) (Please read first Please fill in this page again for the above items) Printed clothes for the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs " n ^ 1- · ϋ I ^ · Ε > ϋ I .1 ^ II ^ ^ ^ n I ^ ^ It ^ t— n- ^ ^ ^ nn ^ tt I _ 466727 5489twf.DOC / 005 Member of Intellectual Property Bureau, Ministry of Economic Affairs, H Consumer Cooperative, printed B7 V. Description of invention (f) Figure;
第4圖爲完成元件封裝製程之基板之上表面的部份上 視圖；以及 T 第5圖爲完成元件封裝製程之基板之上表面的部份上 視圖。 其中，各圖標號與構件名稱之關係如下： 100 :基板 l〇〇a :基板上表面 100b:基板下表面 102a :元件位置區域 102b:周邊區域 103:切割線 104 :槽孔 106:切割線交匯孔 110 :焊接球焊墊 114、]14a、114b :焊罩層 116a、416、516 :焊罩層所裸露之基板上表面. 116b :焊罩層所裸露之基板下表面 ]17 :裂縫 118:封膠材料 實施例 請參照第1A圖至第1B圖，所繪示爲根據本發明之基 板之部份上視圖。第2圖爲完成元件封裝製程之基板之上 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I I ----I _i i I I I I - I I ί I (請先閱讀背面之注意事項再填寫本頁) . I n E n I I n IV n VI n A7 B7 466727 5489twf,DOC/005 五、發明說明（r) 表面的上視圖。第3圖爲完成元件封裝製程之基板之下表 面的上視圖。 請參照第1A圖，首先提供一基板1〇〇，此基板1〇〇可 以是線路載板或晶片承載器等。基板100可使用樹脂片 (Prepreg)製成，例如是以玻璃環氧基樹脂爲材質之FR-4 基板、以雙順丁烯二酸醯亞胺（Bismaleimide-Triazine, BT) 樹脂爲材質之BT基板等。 而基板100具有一上表面100a與一下表面100b(請參 照第2圖與第3圖，後續晶粒黏著之上表面l〇〇a與後續焊 接球黏著之下表面l〇〇b)，而基板100又區分爲元件位置區 域102a與周邊區域102b，其中於上表面100a之元件位置 區域102a中已形成有電性連接之導電跡線（trace)(未繪 示），於下表面l〇〇b之元件位置區域102a中形成有在後續 製程中與電路板電性連接之導電跡線。 此外，在元件位置區域l〇2a與周邊區域102b之間還 包括長條狀槽孔104與切割線交匯孔106，而在基板100 上以虛線103標示之處爲後續進行沖壓分離製程時，直角 截角刀具所切割基板100之處。其中槽孔104位於元件位 摩區域102a的四邊，因此元件位置區域102a與周邊區域 102b之間僅以元件位置區域102a的四角相互連接（第1A與 圖僅繪示出元件位置區域102a之一角落）。 在相鄰兩槽孔104端點之間，亦即是元件位置區域 102a與周邊區域102b相連接的四角之處的基板100上，分 別具有切割線交匯孔106,此切割線交匯孔106係用來防止 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) (請先閱讀背面之注意事項再填窝本頁) 經濟部智慧財產局員工消費合作社印製Figure 4 is a partial top view of the upper surface of the substrate to complete the component packaging process; and T Figure 5 is a partial top view of the upper surface of the substrate to complete the component packaging process. The relationship between each icon number and the component name is as follows: 100: substrate 100a: substrate upper surface 100b: substrate lower surface 102a: component location area 102b: peripheral area 103: cutting line 104: slot 106: cutting line intersection Hole 110: solder ball pad 114, 14a, 114b: welding mask layer 116a, 416, 516: upper surface of the substrate exposed by the welding mask layer. 116b: lower surface of the substrate exposed by the welding mask layer] 17: crack 118: Please refer to FIG. 1A to FIG. 1B for examples of the sealing material. The top view of the substrate according to the present invention is shown. Figure 2 is the substrate on which the component packaging process is completed. 6 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) II ---- I _i i IIII-II ί I (Please read the back first Please note this page before filling in this page). I n E n II n IV n VI n A7 B7 466727 5489twf, DOC / 005 V. Description of the invention (r) Top view of the surface. Figure 3 is a top view of the lower surface of the substrate on which the component packaging process is completed. Referring to FIG. 1A, a substrate 100 is provided first, and the substrate 100 may be a circuit carrier board or a wafer carrier. The substrate 100 may be made of a resin sheet (Prepreg), for example, a FR-4 substrate made of glass epoxy resin, and a BT made of bismaleimide-triazine (BT) resin. Substrate, etc. The substrate 100 has an upper surface 100a and a lower surface 100b (please refer to Figs. 2 and 3, the subsequent grains adhere to the upper surface 100a and the subsequent solder balls adhere to the lower surface 100b), and the substrate 100 is further divided into a component location area 102a and a peripheral area 102b. An electrically connected conductive trace (not shown) has been formed in the component location area 102a on the upper surface 100a, and a lower surface 100b A conductive trace electrically connected to the circuit board in a subsequent process is formed in the element location area 102a. In addition, between the component location area 102a and the peripheral area 102b, a long slot hole 104 and a cutting line intersection hole 106 are included, and the place indicated by the dashed line 103 on the substrate 100 is a right angle when the subsequent punching and separating process is performed. Where the substrate 100 is cut by a chamfering tool. The slot 104 is located on four sides of the element position region 102a. Therefore, the element position region 102a and the peripheral region 102b are connected to each other only by the four corners of the element position region 102a. (Figure 1A and FIG. ). There are cutting line intersection holes 106 on the substrate 100 between the endpoints of two adjacent slot holes 104, that is, the four corners where the element position area 102a and the peripheral area 102b are connected, respectively. This cutting line intersection hole 106 is used for To prevent 7 paper sizes from applying Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling in this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
n n n ϋ -i-r-6J It il I ^ ^ It n n I n- ϋ Kk I .4:64 Tf 5489twf.DOC/005 B7 五、發明說明（A ) 在進行沖壓分離製程時，產生直角切口切割不良的問題。 (請先閱讀背面之注意事項再填寫本頁) 之後，於基板1 〇 0之兩表面上分別形成一層焊罩層 114，此焊罩層1 14在基板100之上表面100a上裸露出焊 線手指（bonding finger)(未繪示）’而在基板100之下表面 l〇〇b裸露出焊接球焊墊ll〇(solder ball pad)(請參照第3 圖），更重要的是，焊罩層114更暴露出周邊區域102b與 元件位置區域l〇2a相連接的四個角落處之基板100部份上 表面116a(請參照第1A圖與第2圖）與部份下表面116b(請 參照第3圖）。在本發明之較佳實施例中，焊罩層所裸露之 基板表面區域丨1 6a與116b分別與其周圍之槽孔104連接， 並且繞過切割線交匯孔位於切割線所包圍之區域外， 而可將焊罩層區隔成一元件位置區焊罩層114a以及一周邊 區域焊罩層〗14b。 經濟部智慧財產局員工消費合作社印製 由於這些裸露之上表面116a與下表面116b可將位於 基板100之上表面l〇〇a與下表面l〇〇b之焊罩層114區隔 爲元件位置區焊罩層114a以及周邊區域焊罩層114b，p此 當在進行後續晶粒黏著、打導線製程、封膠製程以及植球 製程等步驟時，因爲作業過程中造成焊罩層由基板100邊 緣產生裂縫（如第1B圖所示之裂縫117)，或是熱製程所產 生之熱應力釋放不均造成之裂縫（如第1B圖所示之裂縫 117)，會因爲元件位置區域焊罩層114a與周邊區域焊罩層 114b互不相連，而不會向元件位置區域102.延伸，更不會 延伸至完成封膠之封裝件中。所以可以解決習知因爲焊罩 層在封裝製程中產生的裂縫，導致封裝件之可靠度下降’ 本紙張尺度適用中國國家標準（CNS)A4^格（210 X 297公釐） " 5489twf.DOC/005 B7 五、發明說明（7) 良率降低等問題。 · 上述在基板1〇〇之上表面100a與下表面100b形成焊 罩層114之材質包括絕緣材料，例如紫外線型綠漆及熱硬 化型綠漆等，而形成焊罩之方法則包括滾筒塗佈法（Roller Coating)、簾幕塗佈法（Curtain Coating)、網版印刷法（Screen Prmting)、浸染法（Dip)以及乾膜（Dry Film)形成方法等。續 之移除部份焊罩層，以在基板100上形成裸露出部份基板 上表面116a與部份基板下表面116b之焊罩層114，並由 於此裸露之部份基板上表面116a與部份基板下表面116b 將焊罩層分隔成周邊區域焊罩層114b與元件位置區域焊 罩層114a。·其中移除部份焊罩層之方法包括濕式蝕刻法。 請參照第1泛圖，進行一連串之封裝製程，包括先進 h 行一晶粒黏著製程將晶粒（未繪示）黏著於基板100上表面 100a之元件位置區域102a上，之後在晶粒與基板100之 間形成電性連接，之後進行封膠製程，形成封膠材料Π8， 以保護晶粒不受外在環境破壞，並在基板之下表面l〇〇b進 行植球製程，以在焊接球焊墊上佈植焊接球。 之後進行後續沖壓分離製程，使元件位置區域l〇2a與 基板1〇〇分離，完成積體電路之封裝。 在進行晶粒黏著、打導線製程、封膠製程以及植球製 程等步驟的作業過程中，造成焊罩層由基板100邊緣產生 裂縫1Π，或是熱製程所產生之熱應力釋放不均而造成裂縫 Π7,由於裸露之上表面116a與下表面116b可將位於基板 1〇〇之上表面l〇〇a與下表面100b之焊罩層114區隔爲元件 9 本紙張尺度適用中國國家標準（CNS)A4視格（210 X 297公嫠） (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製nnn ϋ -ir-6J It il I ^ ^ It nn I n- ϋ Kk I .4: 64 Tf 5489twf.DOC / 005 B7 V. Description of the Invention (A) In the process of punching and separating, the right-angled cut is bad. problem. (Please read the precautions on the back before filling in this page.) After that, a solder mask layer 114 is formed on both surfaces of the substrate 100. This solder mask layer 1 14 exposes the bonding wires on the upper surface 100a of the substrate 100. Bonding finger (not shown), and the solder ball pad 110 (see FIG. 3) is exposed on the bottom surface 100b of the substrate 100, and more importantly, the solder mask The layer 114 further exposes part of the upper surface 116a of the substrate 100 (see FIG. 1A and FIG. 2) and part of the lower surface 116b (see FIG. 1A and FIG. 2) of the substrate 100 at the four corners connecting the peripheral region 102b and the component location region 102a. (Figure 3). In a preferred embodiment of the present invention, the exposed substrate surface areas of the solder mask layer 16a and 116b are connected to the surrounding slot holes 104, respectively, and bypass the cutting line and the intersection hole is located outside the area surrounded by the cutting line, and The solder mask layer can be divided into a component position region solder mask layer 114a and a peripheral region solder mask layer 14b. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. As these exposed upper surfaces 116a and lower surfaces 116b can separate the solder mask layer 114 located on the upper surface 100a and lower surface 100b of the substrate 100 as the component location Zone solder mask layer 114a and peripheral region solder mask layer 114b. When performing subsequent steps such as die bonding, wire bonding process, sealing process, and ball implantation process, the solder mask layer is caused by the edge of the substrate 100 during the operation. Cracks (such as the crack 117 shown in FIG. 1B) or cracks caused by the uneven release of thermal stress generated by the thermal process (such as the crack 117 shown in FIG. 1B) will be caused by the solder mask layer 114a in the component location area The solder mask layer 114b is not connected to the peripheral area and does not extend to the component location area 102. It also does not extend into the encapsulated package. Therefore, it is possible to solve the problem that the reliability of the package is reduced due to the cracks caused by the solder mask layer in the packaging process. This paper size applies the Chinese National Standard (CNS) A4 ^ grid (210 X 297 mm) / 005 B7 V. Description of the invention (7) Problems such as lower yield. · The materials for forming the solder mask layer 114 on the upper surface 100a and the lower surface 100b of the substrate 100 include insulating materials, such as ultraviolet-type green paint and thermosetting green paint, and the method of forming a solder mask includes roller coating. Method (Roller Coating), curtain coating (Curtain Coating), screen printing (Screen Prmting), dip method (Dip), and dry film (Dry Film) formation methods. Continue to remove part of the solder mask layer to form a solder mask layer 114 on the substrate 100 that exposes part of the upper surface 116a and part of the lower surface 116b of the substrate, and because of the exposed part of the upper surface 116a and the part of the substrate The lower substrate surface 116b separates the solder mask layer into a peripheral region solder mask layer 114b and a component location region solder mask layer 114a. A method in which a part of the solder mask layer is removed includes a wet etching method. Please refer to the first general diagram to perform a series of packaging processes, including an advanced h-line die-bonding process to adhere the die (not shown) to the component location area 102a of the upper surface 100a of the substrate 100, and then the die and the substrate An electrical connection is formed between 100, and then a sealing process is performed to form a sealing material Π8 to protect the crystal grains from external environmental damage. A ball implantation process is performed on the bottom surface of the substrate 100b to solder the balls. Place solder balls on the pads. Thereafter, a subsequent stamping and separating process is performed to separate the component location area 102a from the substrate 100 to complete the packaging of the integrated circuit. During the operations such as die adhesion, wire bonding process, sealing process and ball-planting process, the solder mask layer is cracked from the edge of the substrate 100, or the thermal stress caused by the thermal process is not uniformly released. The crack Π7, because the exposed upper surface 116a and the lower surface 116b can separate the solder mask layer 114 located on the substrate 100 above the surface 100a and the lower surface 100b as the element 9 This paper size applies to the Chinese national standard (CNS ) Grid A4 (210 X 297 Gong) (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
Ί I I I I I I K l> 1 ϋ n I I I I ^ n I —i I - l l I I ϋ n n I - tl n n - l I 經濟部智慧財產局員工消費合作社印製 4 6 6 727 5489twf,DOC/005 A7 ____B7_ 五、發明說明（2 ) 位置區焊罩層1 14a以及周邊區域焊罩層114b，因此元件位 置區域焊罩層U4a與周邊區域焊罩層114b互不相連，所 以裂縫117不會向元件位置區域102延伸，更不會延伸至 完成封膠之封裝件中。而習知因爲焊罩層在封裝製程中產 生裂縫，導致封裝件之可靠度下降，良率降低等問題可以 得到解決。 本發明中在基板1〇〇之上表面l〇〇a與下表面l〇〇b上 形成有焊罩層H4,且焊罩層114裸露出部份基板上表面以 及基板下表面，此裸露的部份基板上表面與基板下表面， 將焊罩層區隔成互不相連的元件位置區域焊罩層以及周邊 區域焊罩層。由於元件位置區域焊罩層以及周邊區域焊罩 層互不相連，因此在進行後續晶粒黏著、打導線製程、封 膠製程以及植球製程等步驟，所造成焊罩層由基板1〇〇邊 緣產生裂縫，或是熱製程所產生之熱應力釋放不均造成之 裂縫，會因爲元件位置區域焊罩層與周邊區域焊罩層互不 栢連，而不會向元件位置區域延伸，更不會延伸至完成封 膠之封裝件中。所以可以解決習知因爲焊罩層在封裝製程 中產生的裂縫，導致封裝件之可靠度下降，良率降低等問 題。 於本發明之較佳實施例中，係以暴露基板周邊區域與 基板的元件位置區域相連接處的基板表面的焊罩層，來表 示以裸露之基板表面將焊罩層區隔成爲周邊區域焊罩層以 及元件位置區域焊罩層。然而在實際應用上，焊罩層所裸 露之基板表面並不侷限於基板之周邊區域與基板之元件位 (請先閱讀背面之注意事項再填寫本頁) v^· -----„-----訂---------線！ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 5489twf.DOC/005 A7 B7 五、發明說明（ί) 置區域的連接處，也不限制所裸露之區域在沖壓分離製程 的切割線所包圍區域之外（如第1A圖所示），所裸露的基 板表面區域可以位於切割線上(如第4圖中的裸露區域 416)，亦可以是位於切割線所包圍之區域內（如第5圖中的 裸露區域5〗6)。此外，所裸露的基板表面區域可以位於元 件位置區域上，達到抑止裂縫向元件位置區域中延伸，並 且暴露出線路區之目的即可。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發日月之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Ί IIIIIIK l > 1 ϋ n IIII ^ n I —i I-ll II ϋ nn I-tl nn-l I Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 4 6 6 727 5489twf, DOC / 005 A7 ____B7_ V. Invention Explanation (2) The solder mask layer 114a in the location area and the solder mask layer 114b in the peripheral area, therefore, the solder mask layer U4a in the component position area and the solder mask layer 114b in the peripheral area are not connected to each other, so the crack 117 does not extend to the component position area 102. And it will not extend into the finished package. However, it is known that problems such as a decrease in the reliability and a decrease in the yield of the package due to cracks in the solder mask layer during the packaging process can be solved. In the present invention, a solder mask layer H4 is formed on the upper surface 100a and the lower surface 100b of the substrate 100, and the solder mask layer 114 exposes part of the upper surface of the substrate and the lower surface of the substrate. Part of the upper surface of the substrate and the lower surface of the substrate separate the solder mask layer into the solder mask layer and the peripheral mask mask which are not connected to each other. Because the solder mask layer in the component location area and the solder mask layer in the peripheral area are not connected to each other, the subsequent steps of die bonding, wire bonding process, sealing process, and ball implantation process, the solder mask layer is formed by the edge of the substrate 100. The occurrence of cracks or cracks caused by the uneven release of thermal stress caused by the thermal process, because the solder mask layer in the component location area and the solder mask layer in the peripheral area are not connected to each other, and will not extend to the component location area, let alone Extend into the finished package. Therefore, it is possible to solve problems such as the cracks generated during the packaging process of the solder mask layer, which reduces the reliability of the package and the yield. In a preferred embodiment of the present invention, the solder mask layer on the substrate surface where the peripheral region of the substrate is connected to the component location region of the substrate is used to indicate that the solder mask layer is separated into the peripheral region by the bare substrate surface. The mask layer and the solder mask layer in the component location area. However, in practical applications, the surface of the substrate exposed by the solder mask layer is not limited to the peripheral area of the substrate and the component position of the substrate (please read the precautions on the back before filling this page) v ^ · ----- „- ---- Order --------- Line! This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 5489twf.DOC / 005 A7 B7 V. Description of the Invention (ί) Set The connection of the areas does not limit the exposed area outside the area surrounded by the cutting line of the stamping and separation process (as shown in FIG. 1A), and the exposed substrate surface area can be located on the cutting line (as shown in FIG. 4). Exposed area 416), or it can be located in the area surrounded by the cutting line (such as the exposed area 5 in Figure 5). In addition, the exposed surface area of the substrate can be located on the component location area to prevent cracks from reaching the component. The purpose is to extend in the location area and expose the line area. Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art will not depart from the spirit of the present invention. And range, when it can be used as a variety of Therefore, the protection scope of this issue will be determined by the scope of the attached patent application. (Please read the precautions on the back before filling this page) Printed by the Intellectual Property Bureau Staff Consumer Cooperatives Paper size applies to China National Standard (CNS) A4 (210 X 297 mm)