經濟部中央標苹局員X消费合作ii.印tMember of the Central Bureau of the Ministry of Economic Affairs X Consumer Cooperation ii. India
4 6 6 6 2 1 Ο 6 5 6 T W F . D O C / 0 ϋ 2 八 η Β7 五、發明説明（I ) 本發明是關於半導體元件製程，且特別是有關於半導 體元件全面性平坦化之方法。 當積體電路的積集度增加到某一個程度之後，因爲金 屬線的線寬無法同樣依MOS元件縮小的比例加以縮減（這將 使導線的電阻上升），所以以往單一層金屬層的設計，將無 法完成整個積體電路的連線工作，而必須以兩層，3層， 甚至5層各別的金屬內連線層，來執行這項工作。這就是 我們所說的多重金屬內連線技術（Multiple-Level Interconnect Technology)。當然了，這幾種金屬層之間， 必須以絕緣能力良好的介電材料加以隔離，以防止短路。 在VLSI製程上，我們通常都使用介電常數（Dielectric Constant)較低的Si〇2，來做爲各層金屬間的隔離層材料。 因爲這些金屬連線會使得積體電路的表面，產生高低起伏 不定的外觀，這種粗糙的金屬線外觀，將使得接下來做爲 金屬線隔離層用的31〇2層的沈積，產生困難，甚至無法完 全的將金屬線間的縫隙加以塡滿，而留下孔洞（Voids)。在 這層外觀同樣粗糙的SiOJi離層上，很明顯的，我們將無 法順利的進行第二層金屬層的製作，而必須設法將這層外 觀因金屬線而產生高低起伏的$丨〇2層，加以平坦之。 平坦化（planarization)是現在半導體的製程上，非常 重要的步驟之一，特別是在製程線寬低於2.G //πι以下後， 爲了降低晶片表面因元件間的距離縮短所造成的影響，並 使多虽金屬内連線的製戶與彼此間的連接不會造成太大的 困擾，如何將表面的高低起伏加以平坦化，□是現在VLSI --s--------裝------訂 (請先閱讀背面之注意事項再填寫本頁) 私紙烺义哎過η;巾闷押家挖乘u'\s ) 公球1 經濟部中央榡隼局員工消費合作^印製 4 6 6 6 2 1 Ο 6 5 6 T W F - D C /Ο Ο 2 Β7 五、發明説明（）） 製程中，必須解決的當務之急。 所謂的平坦化，就是將晶片表面的介電層外觀加以平 坦的一種半導體製程技術，經平坦化後的介電層，因無劇 烈的高低落差，在製作接下來的第二層金屬內連線時，將 比較容易進行，且經轉移的導線圖案也將較精確。爲了增 加導線的電傳導力，低電阻係數的鋁，是現在半導體製程 上，最普遍被使用的導電材料。但是因爲鋁的溶點較低， 在進行內連線介電層的製作時，第一層金屬鋁製作完成 後，爲了不讓位於介電層下方的鋁線結構遭破壞，沈積內 連線介電層的製程，必須在溫度低於500〜450 °C以下的環 境進行才可，故此薄膜通常是以化學氣相沈積法來製作 的，且通常以可在450 °C以下進行介電材質沈積的電漿加 強式化學氣相沈積法使用最普遍。 習知一種平坦化的方法，是在高低起伏的晶片表面， 沈積一層厚度超過所需甚多的二氧化矽層，然後以非等向 性蝕刻的方法，將此二氧化矽層回蝕刻到所需的厚度；然 而這種平坦化的方法只能在晶片表面獲得部份平坦化的結 果。最直接的方式，就是在不平坦的區域沈積或覆蓋上-層二氧化矽，如此便能達成製作下一層金屬內連線時所需 的局部性或全面性的介電層平坦度；這種平坦化的製作方 式，就是現在半導體界所採用的旋塗式玻璃（spin cm glass ; SOG)製程的基本槪念。 S0G是現在最普遍的一種平玑化技術，其作法類似光阻 旋塗技術，把·種溶於溶劑內之介電材料，以旋筚方式塗 4 I - I- -- I 4 -II -- I [—I -ii (請先閱讀背面之注意事項再填寫本頁) UUk d 崎 Θ 十 W W Ϋ 1 \4 2 h) -. 公贷） 經濟部中央榡準局員工消费合作社印背 4 6 662 1 06 5 6TWF.DOC/002 A7 _______B7_ 五、發明説明（3 ) 佈在晶片上，經塗佈的介電材料可隨著溶劑在晶片的表面 流動，因此可以容易的塡入晶片表面的凹槽裡，而達到局 部性平坦化的目的。經過適當的熱處理以去除用來溶解介 電材料的溶劑後，一種用來塡補沈積介電層凹陷區域的平 坦化製程，便告完成；接下來便可在經平坦化後的內連線 介電層表面上，製造第二層以上的內連線金屬層。 SOG是一種相當簡易的平坦化技術，因爲介電層材料是 以溶劑的型態覆蓋在晶片的表面，因此SOG對高低起伏外 觀的溝塡能力（gap fill)比以化學氣相沈積法所製作的介 電層佳，且其較少造成孔洞（voids)，現已成爲常用的一種 介電層的平坦化技術。 然而，S0G技術僅能進行製程線寬到G.5 jt/m的溝塡與平坦 化，且其所提供的是一種局部性平坦化，當晶片表面凸起 間的間距（spacing)較短時，S0G的平坦能力較佳，而當晶 片表面凸起間的間距很長時，S0G所提供的平坦能力將變 得非常有限。請參照第1圖，在一晶片上之介電層10上形 成金屬內連線12，然後再以S0G 14塡補內連線之間的溝 槽，使晶片表面全面性平坦化，以利後續元件的製造；其 中在A與B區域因內連線間距較短，S0G的平坦能力較佳， 而在C區域則其內連線間距較長，S0G的平坦能力變得較 差，無法眞正做到全面性平坦化。 一種可流動旋塗式玻璃（flowable spin on g 1 ass or spin on polymer ; SOP)，其爲具甲基之矽氧烷類SOG，爲 有低電羾係數，可降低元件之RC延遲，a其以冇nj流動之 n UK ^^1 1 —I— ^^1 士^I- - - -i In - --_ m Te (請先閱讀背面之注意事項再填寫本頁) 經濟部中央掭準局K工消资合作.ΐ印^ ；662 1 06 5 6TWF.DOC. 002 八7 五、發明説明（if ) 特性，故可溝塡至線寬約（M5 /zm之能力。然而，在SOP上 方再形成另層之金屬內連線時，在濺鍍過程中S0P會有出 氣現象（out-gassing)，產生孔洞（voids)而造成有害的介 電窗口（poison via)。 習知一種避免造成有害介電窗口之方法：電子束固化 (E-bean cur*ing)SOP層，其主要是以電子束轟擊SOP層， 破壞原本SOP鍵結，使其內部重新排列，減少出氣現象。 然此方法將使原本SOP之化性由有機變爲無機，提高介電 常數；且以高能量的電子束轟擊SOP表面後會使其表面扭 曲，降低原本SOP之平坦度。 習知另一種避免造成有害介電窗口之方法：形成氣體 (Forming gas)，其主要是以H2/N2二種氣體所形成的電漿 處理SOP表面，使其內部重新排列，減少出氣現象。然此 方法之單位時間產出量，比以〇2電漿處理降低許多，影響 生產。 有鑑於此’本發明提出一全面性平坦化方法，其步驟 包括：提供一半導體基底，其上並形成至少有一電晶體， 包括閘極，源/汲極擴散區及隔離用的場氧化層；形成一 第一介電層於該晶片上；形成一金屬層於該第一介電層 上，並蝕刻之以形成金屬內連線；形成一第二介電層於該 第一介電層上；形成一第三介電層於該第二介電層上，並 溝塡該金屬內連線間的溝槽；對第二介電層表面施以離子 摻雜’使其表面平坦化；形成.第四介電質於該第三介電 層上。其利用SOP來塡補溝槽，可使塗佈在金屬内連線h ^^^1- ^^^^1 nn n^i (請先閎讀背面之注意事項再填寫本頁) 衣纸屮义f('\s ) i 2Ι〇7>)-.λ.λ ) 經濟部中央標隼局W.T1消費合作社印焚 46662) 0656TWF.DOC/00 2 五、發明説明（女） 的SOP迴流至溝槽，增加其平坦度；且以砷離子摻雜SOP 層，避免在金屬層濺鍍時產生出氣現象，造成有害的介電 窗口，而又不會影響介電層之電阻係數及平坦度。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1圖是剖面圖，顯示不同金屬線間距對S0G溝塡與平 坦化能力的影響情形。 第2A〜2B圖是根據本發明之剖面流程圖。 實施例 首先，請參照第2A圖，提供一半導體基底，例如是矽 基底20，其上並形成有電晶體，包括閘電極24及位於閘電 極兩側之矽基底表面之源/汲極擴散區28，且更包括隔離 用的場氧化區22以及位於閘電極側壁之側壁間隙層26。其 次，以化學氣相沈積法或熱氧化法形成二氧化矽層3G於晶 片上，其較佳厚度約介於4K〜8KA。接著，再以直流濺鍍 法（DC sputtering)形成一金屬層於二氧化砂層30上，並 蝕刻定義之，以形成金屬內連線32。然後，以電漿加強化 學氣相沈積法（PECVD)沈積一富含矽的氧化層（si 1 icon rich oxide ; SR0)於金屬內連線及二氧化矽層上，其厚度 約介於1000〜2000人。在SR0上以旋轉塗佈方式（spin coating)塗佈·可流動S0G層36，其材質例如是Allied SigitilAS-X18系列，其介電常數小於3 ;塗佈完後將晶片 ^ϋ· - _ -^11 IJ1 - —^1 I ^^1 ^^1----- XW ·7^-νβ (請先鬩讀背面之注意事項再填寫本頁) 7 466621 0656TWF，D(.)c/〇〇2 五、發明説明（（^ ) 置於加熱板上，以溫度約18Q °c加熱2mi η，使位於金屬內 連線上的SOG迴流至金屬內連線的溝槽裡，使流塡至晶片 平坦度達95%以上。接著，以砷離子對S0G表面進行離子摻 雜’改變表層S0G內之甲基鍵結，避免其在金屬濺鍍過程 中產生C〇2及H2〇氣體，也就是所謂的出氣現象’而導致孔 洞及有害介電窗口出現；其中砷離子摻雜過的S0G 38厚度 約爲塗佈的S0G厚度之1/2〜1/3。 接著，請參照第2B圖，於摻雜過的S0G表面再形成一 二氧化矽層40，其是利用四乙基矽酸或矽甲烷以PECVD法 形成的，如此便可達到線寬約0.35 之全面性烜化表面， 而線寬在0.35 以下之元件，其可再配合化學機械硏磨 法，將S0G上之二氧化矽層再硏磨’使其表面更加平坦化， 在此不再贅述。 雖然本發明已以一較佳實施例揭露如上’然其並非用 以限定本發明，任何熟習此技藝者’在不脫離本發明之精 神和範圍內，當可作些許之更動與潤飾’因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 ----.----1 -裝——----訂 {請先閱讀背面之注意事項再填寫本頁) 經濟部中矢標準局Μ工消fr合作.ΐ印鱿 . —__ ~4 6 6 6 2 1 Ο 6 5 6 T W F. D O C / 0 ϋ 2 8 η B7 V. Description of the Invention (I) The present invention relates to a process for manufacturing semiconductor devices, and more particularly to a method for comprehensively planarizing semiconductor devices. When the integration degree of the integrated circuit is increased to a certain degree, because the line width of the metal line cannot be reduced according to the proportion of the reduction of the MOS device (this will increase the resistance of the wire), so the previous design of a single metal layer, It will not be possible to complete the wiring work of the entire integrated circuit, and it must be performed with two, three, or even five separate metal interconnect layers. This is what we call Multiple-Level Interconnect Technology. Of course, these types of metal layers must be separated by a dielectric material with good insulation to prevent short circuits. In the VLSI process, we usually use Si02 with a lower dielectric constant as the material for the isolation layer between the various layers of metal. Because these metal wires will make the surface of the integrated circuit fluctuate, this rough metal wire appearance will make it difficult to deposit the 3202 layer used as the metal wire isolation layer. It is not even possible to completely fill the gaps between the metal wires and leave holes (Voids). On this layer of SiOJi with the same rough appearance, it is obvious that we will not be able to successfully produce the second metal layer, but we must try to make this appearance of the $ 丨 〇2 layer that fluctuates due to the metal wire. And flatten it. Planarization is one of the most important steps in the current semiconductor manufacturing process, especially after the process line width is less than 2.G // πm, in order to reduce the impact of the wafer surface due to the shortened distance between components And to make the connection between the customers who connect with the metal interconnects and each other not cause much trouble, how to flatten the surface fluctuations is now VLSI --s -------- Install ------ order (please read the notes on the back before filling in this page) Consumption cooperation ^ Printing 4 6 6 6 2 1 Ο 6 5 6 TWF-DC / Ο 〇 2 Β7 V. Description of the invention ()) In the manufacturing process, the top priority must be resolved. The so-called planarization is a semiconductor process technology that flattens the appearance of the dielectric layer on the surface of the wafer. After the planarized dielectric layer has no sharp level difference, the next second metal interconnect is produced. In this case, it will be easier to perform and the transferred wire pattern will be more accurate. In order to increase the electrical conductivity of the wire, aluminum with low resistivity is the most commonly used conductive material in semiconductor manufacturing. However, because aluminum has a relatively low melting point, during the production of the interconnect dielectric layer, after the first layer of metallic aluminum is manufactured, in order to prevent the aluminum wire structure located below the dielectric layer from being damaged, the interconnect is deposited. The manufacturing process of the dielectric layer must be performed in an environment with a temperature lower than 500 ~ 450 ° C. Therefore, the thin film is usually made by chemical vapor deposition, and the dielectric material is usually used below 450 ° C. The most commonly used method is the deposited plasma enhanced chemical vapor deposition method. It is known that a method of planarization is to deposit a silicon dioxide layer having a thickness more than necessary on the surface of the undulating wafer, and then etch back the silicon dioxide layer to the surface by anisotropic etching. Required thickness; however, this method of planarization can only obtain a partial planarization result on the wafer surface. The most direct way is to deposit or cover the top-layer silicon dioxide on uneven areas, so as to achieve the local or comprehensive dielectric layer flatness required for the next metal interconnect; The flattening manufacturing method is the basic idea of the spin cm glass (SOG) process currently used in the semiconductor industry. S0G is the most common flattening technology. Its method is similar to photoresist spin coating technology. A kind of dielectric material dissolved in a solvent is applied by spin coating. 4 I-I--I 4 -II- -I [—I -ii (Please read the precautions on the back before filling out this page) UUk d Saki Θ Ten WW Ϋ 1 \ 4 2 h)-. Public loan) Printed on the back of the employee ’s consumer cooperative of the Central Procurement Bureau of the Ministry of Economic Affairs 4 6 662 1 06 5 6TWF.DOC / 002 A7 _______B7_ V. Description of the invention (3) Disposed on the wafer, the coated dielectric material can flow with the solvent along the surface of the wafer, so it can be easily inserted into the surface of the wafer. Inside the groove, and achieve the purpose of local flattening. After a suitable heat treatment to remove the solvent used to dissolve the dielectric material, a planarization process to supplement the recessed areas of the deposited dielectric layer is completed; then the planarized interconnects can be used. On the surface of the electrical layer, an interconnect metal layer of more than a second layer is manufactured. SOG is a relatively simple planarization technique. Because the dielectric layer material covers the surface of the wafer in the form of a solvent, the gap fill of SOG to the fluctuating appearance is higher than that produced by chemical vapor deposition. The dielectric layer is good, and it causes fewer voids, and it has become a commonly used dielectric layer planarization technology. However, the SOG technology can only perform trenching and planarization with a process line width up to G.5 jt / m, and it provides a localized planarization. When the spacing between the protrusions on the wafer surface is short S0G has better flatness, and when the pitch between the bumps on the wafer surface is long, the flatness provided by S0G will become very limited. Referring to FIG. 1, a metal interconnect 12 is formed on a dielectric layer 10 on a wafer, and then the grooves between the interconnects are filled with S0G 14 to flatten the surface of the wafer in a comprehensive manner for subsequent Manufacture of components; among them, the area of A and B is short because of the short distance between interconnects, so the flatness of S0G is better, while the area of C is longer because of the distance between interconnects, the flatness of S0G becomes poorer, which cannot be done right. To comprehensive flattening. A flowable spin-on glass (flowable spin on g 1 ass or spin on polymer; SOP), which is a siloxane-based SOG with a methyl group, has a low electric coefficient, and can reduce the RC delay of the device. Flowing through 冇 nj UK ^^ 1 1 —I— ^^ 1 Taxi ^ I----i In---_ m Te (Please read the notes on the back before filling this page) Central Ministry of Economic Affairs Bureau K industrial and consumer cooperation. Ϊ́ 印 ^; 662 1 06 5 6TWF.DOC. 002 8 7 5. Description of the invention (if) characteristics, so it can ditch to the line width of about (M5 / zm ability. However, in the SOP When another layer of metal interconnect is formed on the top, the SOP will have out-gassing during the sputtering process, which will generate voids and cause harmful dielectric windows (poison via). The method of harmful dielectric window: E-bean cur * ing SOP layer, which mainly bombards the SOP layer with an electron beam, destroys the original SOP bond, rearranges the inside of it, and reduces the phenomenon of outgassing. Will change the original SOP from organic to inorganic to increase the dielectric constant; and the surface of the SOP will be surfaced with a high-energy electron beam Twist and reduce the flatness of the original SOP. Another method to avoid the harmful dielectric window: forming gas, which mainly treats the surface of the SOP with the plasma formed by H2 / N2 gas, making it The internal rearrangement reduces the phenomenon of outgassing. However, the output per unit time of this method is much lower than that of plasma treatment, which affects production. In view of this, the present invention proposes a comprehensive flattening method, the steps of which include: providing A semiconductor substrate having at least one transistor formed thereon, including a gate electrode, a source / drain diffusion region, and a field oxide layer for isolation; forming a first dielectric layer on the wafer; forming a metal layer on the first A dielectric layer is etched to form metal interconnects; a second dielectric layer is formed on the first dielectric layer; a third dielectric layer is formed on the second dielectric layer, and trenches are formed沟槽 trenches between the metal interconnects; applying ion doping to the surface of the second dielectric layer to flatten its surface; forming. A fourth dielectric on the third dielectric layer. It uses SOP to Replenishing grooves for coating in metal Line h ^^^ 1- ^^^^ 1 nn n ^ i (Please read the precautions on the back before filling out this page) Clothing paper meaning f ('\ s) i 2Ι〇7 >)-. Λ. λ) Printed by W.T1 Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. To avoid the phenomenon of gas generation during metal layer sputtering, which will cause harmful dielectric windows without affecting the resistivity and flatness of the dielectric layer. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1 It is a sectional view showing the effect of different metal line spacing on the SOG trench and planarization ability. 2A to 2B are cross-sectional flowcharts according to the present invention. Embodiment First, referring to FIG. 2A, a semiconductor substrate, such as a silicon substrate 20, is provided with a transistor formed thereon, including a gate electrode 24 and a source / drain diffusion region on the surface of the silicon substrate on both sides of the gate electrode. 28, and further includes a field oxidation region 22 for isolation and a sidewall gap layer 26 on a sidewall of the gate electrode. Secondly, a silicon dioxide layer 3G is formed on the wafer by a chemical vapor deposition method or a thermal oxidation method, and its preferred thickness is between about 4K and 8KA. Next, a DC sputtering method is used to form a metal layer on the sand dioxide layer 30, and the etching is defined to form a metal interconnect 32. Then, a plasma-enhanced chemical vapor deposition (PECVD) method is used to deposit a silicon-rich oxide layer (si 1 icon rich oxide; SR0) on the metal interconnects and the silicon dioxide layer, and the thickness is about 1000- 2000 people. Spin-coatable and flowable SOG layer 36 on SR0. The material is, for example, Allied SigitilAS-X18 series, and its dielectric constant is less than 3; after coating, the wafer ^ ϋ ·-_- ^ 11 IJ1-— ^ 1 I ^^ 1 ^^ 1 ----- XW · 7 ^ -νβ (Please read the precautions on the back before filling this page) 7 466621 0656TWF, D (.) C / 〇 〇2 V. Description of the invention ((^) Placed on a hot plate and heated at a temperature of about 18Q ° C for 2 mi η, so that the SOG on the metal interconnect is reflowed into the groove of the metal interconnect, and the flow reaches The flatness of the wafer is above 95%. Next, the surface of SOG is ion-doped with arsenic ions to change the methyl bond in the surface SOG to avoid the generation of CO2 and H2O gas during the metal sputtering process, that is, The so-called outgassing phenomenon 'results in the appearance of holes and harmful dielectric windows; the thickness of the SOG 38 doped with arsenic ions is about 1/2 to 1/3 of the thickness of the coated SOG. Next, please refer to Figure 2B. A silicon dioxide layer 40 is formed on the surface of the doped SOG. The silicon dioxide layer 40 is formed by using PECVD method of tetraethylsilicic acid or silicic acid, so that the line width can be about 0.35. Comprehensively honing the surface, and for components with a line width below 0.35, the surface of the silicon dioxide layer on the SOG can be further honed with the chemical mechanical honing method to make the surface flatter, which will not be repeated here. Although the present invention has been disclosed above with a preferred embodiment, 'but it is not intended to limit the present invention, any person skilled in the art' can make some changes and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. ----.---- 1 -Installation -------- Order {Please read the precautions on the back before filling this page) Cooperation with the Nakaya Standards Bureau, Ministry of Economic Affairs, M & F.