4651 2 9 A7 B7 五、發明説明（) 【發明背景】 . 【發明領域】 裝— C. (請先聞請背面之注意事項再填寫本頁) 本發明係關於一種半導體光電裝置，具有切割成非矩 形形狀之基板。本發明尤其關於一種半導體光電裝置，具 有側壁表面皆位於同一結晶平面家族的平行四邊形或三角 形基板° 【相關技藝之說明】 Q. 半導體光電裝置，例如發光二極體、雷射、以及光偵 測器，經常由成長於單晶基板上的若干磊晶化合物半導體 層所組成。單晶基板之選擇主要取決於結晶學的考量，例 如磊晶化合物半導體層與單晶基板之晶體結構與晶格常 數。一般而言，與磊晶化合物半導體層同屬相同結晶系的 單晶基板可使磊晶化合物半導體層容易且迅速成長於其 上。再者，單晶基板之晶格常數必須儘可能接近磊晶化合 物半導體層之晶格常數，藉以防止在磊晶化合物半導體層 中發生伸張或壓縮應力。 近年來，氮化鎵(GaN)型化合物半導體材料已經吸引 了許多硏究的興趣，因爲其具有產生藍色、綠色、或藍綠 色光之能力。在GaN型化合物半導體材料之所有應用可 能中，發出藍光之GaN型發光二極體已是今曰商業上可 獲得的產品。基於前述結晶學之考量’ GaN型發光二極 體經常形成於藍寶石(A1203)基板或碳化矽(SiC)基板上’ 該二種基板皆屬於六方晶系。 4 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐） 4 65 1 2 9 A7 ___B7_ 五、發明説明（） 圖1係顯示作爲GaN型發光二極體之基板使用的藍寶 石或碳化矽晶圓10之頂視圖。經由適當的半導體製程，眾 多相同的GaN型發光二極體(未圖示)一起被製作於晶圓1〇 上。習知上，此等GaN型發光二極體排列成被稱爲「晶粒」 之矩形元件11陣列，而其邊緣尺寸爲釐米級或更小。爲了 獲得封裝用之獨立的GaN型發光二極體，故藉由使用例如 裝配有鑽石刀之劃片器(scrito)之切割工具，沿著晶粒邊緣 12切割或割裂六方晶系晶圓10。 不幸地，矩形晶粒切割製程，亦即切割晶圓成爲矩形 晶粒之製程，無法在晶圓10上產生平順且乾淨的切口，因 爲由藍寶石或碳化矽所形成的晶圓10並非立方晶系之晶 體。另一方面，切割工具上之磨損與損壞因矩形晶粒切割 製程而加速。結果，矩形晶粒切割製程關聯有至少三項缺 .點。首先，既然切割工具之消耗大，故製程成本變高。次 之，製造程序必須中斷以便用新的切割工具替換舊的切割 工具，導致製程時間增加。最後，矩形晶粒切割製程之良 率因晶粒碎裂而受到抑制。 【發明槪述】 本發明之目的在於提供一種半導體光電裝置，具有沿 著一晶圓之相同結晶平面家族切割出之非矩形基板。該非 矩形基板具有一其上形成有層狀半導體結構的主表面，以 及環繞該主表面之側壁表面。該主表面之形狀係多邊形， 特別係平行四邊形或三角形，並且其所有內角皆爲60或120 5 本紙張尺度適用中國國家樣準（CNS〉A4規格（210X297公釐） -- (請先閲讀背面之注意事項再填寫本買) 465 1 2 9 A7 B7 五、發明說明（） 度。該側壁表面皆位於相同的結晶平面家族。 依據本發明，首先準備一晶圓，例如藍寶石、碳化矽、 或磷化鎵晶圓。在該晶圓之主表面上，眾多半導體光電結 構，例如發光二極體，被製作成一多邊形晶粒陣列，該多 邊形晶粒之邊緣皆沿著該晶圖中之相同的結晶平面家族延 伸。此外，每一多邊形晶粒之所有內角皆爲60度或120度。 沿著晶粒邊緣，一切割工具將晶圓切割或割裂成個別的多 邊形晶粒。既然所有晶粒邊緣皆沿著晶圓之結晶平面延伸， 故切割工具平順且乾淨地將晶圓分隔成晶粒。 因而，在依據本發明之晶粒切割製程中，切割工具可 輕易產生平順且乾淨的切口。切割工具之磨損與損壞亦降 低。既然晶粒碎裂被有效地避免，故依據本發明之晶粒切 割製程之良率增強。 【較佳實施例之詳細說明】 本發明之前述與其他目的、特徵、以及優點將於參照 下文中之詳細說明與附圖後更爲明顯。茲將參照圖示詳細 說明依據本發明之較佳實施例。 典型上，六方晶系晶圓，例如藍寶石或碳化砂晶圖， 係用作爲GaN型半導體光電裝置之基板，如前所述。圖之⑻ 至2(c)係顯示六方晶系之結晶軸與結晶平面之示意圖。如圖 2(a)至2(c)所示，六方晶系乃定義於由三個共平面軸&、％、 與a3以及一垂直於ai、％、與％軸之c軸所架構成的座標系 統中。a!、％、與和軸中之任二軸間戶斤夾之角度爲no度。 64651 2 9 A7 B7 V. Description of the invention (Background of invention). [Field of invention] Packaging — C. (Please read the notes on the back before filling out this page) The present invention relates to a semiconductor optoelectronic device, which is cut into Non-rectangular substrate. In particular, the present invention relates to a semiconductor optoelectronic device having a parallelogram or triangular substrate with sidewall surfaces all located in the same crystal plane family. [Explanation of related technologies] Q. Semiconductor optoelectronic devices, such as light emitting diodes, lasers, and light detection The device is often composed of several epitaxial compound semiconductor layers grown on a single crystal substrate. The choice of single crystal substrates depends mainly on crystallographic considerations, such as the crystal structure and lattice constant of epitaxial compound semiconductor layers and single crystal substrates. In general, a single crystal substrate of the same crystal system as the epitaxial compound semiconductor layer can easily and rapidly grow the epitaxial compound semiconductor layer thereon. Furthermore, the lattice constant of the single crystal substrate must be as close to the lattice constant of the epitaxial compound semiconductor layer as possible to prevent stretching or compressive stress from occurring in the epitaxial compound semiconductor layer. In recent years, gallium nitride (GaN) type compound semiconductor materials have attracted much research interest because of their ability to generate blue, green, or blue-green light. Among all possible applications of GaN-type compound semiconductor materials, GaN-type light-emitting diodes that emit blue light are commercially available products today. Based on the aforementioned crystallographic considerations, 'GaN-type light-emitting diodes are often formed on a sapphire (A1203) substrate or a silicon carbide (SiC) substrate.' Both substrates belong to the hexagonal crystal system. 4 This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) 4 65 1 2 9 A7 ___B7_ V. Description of the invention () Figure 1 shows the sapphire or carbonization used as the substrate of GaN light-emitting diode Top view of silicon wafer 10. Through an appropriate semiconductor process, many identical GaN-type light emitting diodes (not shown) are fabricated on the wafer 10 together. Conventionally, these GaN-type light emitting diodes are arranged in an array of rectangular elements 11 called "grains", and their edge sizes are in the order of centimeters or less. In order to obtain an independent GaN-type light emitting diode for packaging, a hexagonal wafer 10 is cut or split along the die edge 12 by using, for example, a cutting tool equipped with a diamond knife scrito. Unfortunately, the rectangular die cutting process, that is, the process of cutting the wafer into rectangular die, cannot produce a smooth and clean cut on the wafer 10 because the wafer 10 formed of sapphire or silicon carbide is not a cubic crystal system Of crystals. On the other hand, wear and damage on cutting tools is accelerated by the rectangular die cutting process. As a result, the rectangular die cutting process is associated with at least three defects. First of all, since the consumption of cutting tools is large, the process cost becomes high. Second, the manufacturing process must be interrupted in order to replace the old cutting tool with a new cutting tool, resulting in increased process time. Finally, the yield of the rectangular die-cutting process is suppressed due to die cracking. [Invention description] The object of the present invention is to provide a semiconductor optoelectronic device having a non-rectangular substrate cut along the same crystal plane family of a wafer. The non-rectangular substrate has a main surface on which a layered semiconductor structure is formed, and a side wall surface surrounding the main surface. The shape of the main surface is a polygon, especially a parallelogram or a triangle, and all the internal angles are 60 or 120. 5 This paper size applies to the Chinese national standard (CNS> A4 size (210X297 mm)-(Please read first Note on the back then fill in this purchase) 465 1 2 9 A7 B7 V. Description of the invention () degrees. The surface of the side walls are located in the same crystal plane family. According to the present invention, first prepare a wafer, such as sapphire, silicon carbide, Or gallium phosphide wafer. On the main surface of the wafer, many semiconductor optoelectronic structures, such as light-emitting diodes, are fabricated into a polygonal die array, and the edges of the polygonal die are the same along the crystalline pattern. The family of crystal planes extends. In addition, all the internal angles of each polygonal die are 60 degrees or 120 degrees. Along the edge of the die, a cutting tool cuts or splits the wafer into individual polygonal die. Since all the crystals The edges of the grains all extend along the crystal plane of the wafer, so the cutting tool smoothly and cleanly divides the wafer into grains. Therefore, in the grain cutting process according to the present invention, cutting It can easily produce smooth and clean cuts. The abrasion and damage of the cutting tool are also reduced. Since the chip fragmentation is effectively avoided, the yield of the chip cutting process according to the present invention is enhanced. [Details of the preferred embodiment [Description] The foregoing and other objects, features, and advantages of the present invention will become more apparent with reference to the following detailed description and drawings. The preferred embodiments according to the present invention will be described in detail with reference to the drawings. Typically, the six parties Crystalline wafers, such as sapphire or carbide sand crystal maps, are used as substrates for GaN-type semiconductor optoelectronic devices, as described previously. Figures 2 to 2 (c) are schematic diagrams showing the crystal axis and crystal plane of the hexagonal crystal system. As shown in Figures 2 (a) to 2 (c), the hexagonal crystal system is defined by three coplanar axes &,%, and a3, and a c axis perpendicular to the ai,%, and% axes. In the coordinate system formed, the angle between any two axes of a !,%, and the axis is no degree. 6
本紙張尺度適用令國國家標準（CNS)A4規格（210 X 297公釐） 4651 2 9 B7 五、發明說明（） 簡單言之，圖2⑻至2(C)分別顯示六方晶系之(0001)、(11 ϊ〇)、 與(l〇i〇)平面。 作爲GaN型半導體光電裝置所用之基板，藍寶石與碳 化矽晶圓通常係從沿著<〇〇〇1>方向成長的晶體上切割出， 其被稱之爲(0001)晶圖。 依據本發明，爲了製造GaN型半導體光電裝置於(〇〇〇1) 晶圓之主表面上，既然{l〇i〇}平面因連結鍵之排列而爲容易 切開的平面，故每一晶粒係設計成所有邊緣皆沿著{l〇i〇}平 面。應注意者爲：{1〇ί0}平面係代表一平面家族，包括(l〇i〇) 平面以及與其等效的平面，該等效平面爲(〇_平面、(i 100) 平面、（ϊ010)平面、（〇ί 10)平面、以及(1ϊ00)平面。藉由此 等排列，在晶粒切割製程中容易藉由切割工具沿著每一晶 粒之邊緣將其從(0001)晶圓中切割出。切割工具之磨損與損 壞因而大大地降低。 參照圖3⑻至3(c)，以GaN型發光二極體之製造步驟 爲例說明依據本發明之六方晶系基板上之晶粒排列與方 位。在圖3⑻中，首先預備一六方晶系晶圓30作爲GaN型 發光二極體之基板。在六方晶系晶圓30上依序形成一 η型 GaN型化合物半導體層31、一由InGaN所形成的主動層32， 用以產生藍光、以及一 p型GaN型化合物半導體層33。繼 而，進行乾式蝕刻製程以部份移除P型GaN型化合物半導 體層33、主動層32、以及η型GaN型化合物半導體層31。 如圖;3(b)所示，於乾式蝕刻製程後部分η型GaN型化合物 半導體層31顯露出。 7 本紙張尺度適用t國國家標準（CNS>A4規格（210 X 297公釐） illlll — _^·ΙΙΙΙΙΙ — (锖先間讀背面之注意事展#'填窝本頁) / : f ^ '4 65 1 2 9 Β7 五、發明說明（） 參照圖3(c)，一 p型電極34與一 η型電極35分別形成 於ρ型GaN型化合物半導體層33與η型GaN型化合物半 導體層31之顯露表面上。因而完成一GaN型發光二極體。 以相同的方式，許多相等的GaN型發光二極體可被製 作成一位於六方晶系晶圓上之晶粒陣列。如前所述，當使 用(0001)晶圓時，每一晶粒之邊緣皆排列成沿著{l〇i〇}平面 延伸。結果，每一晶粒皆形成爲一多邊形形狀，該多邊形 形狀之內角係選自於由60度與120度所組成之族群中之一 角度。 圖4係顯示排列於六方晶系晶圓40上之平行四邊形晶 粒41，其爲依據本發明之多邊形晶粒之一例子。倘若使用 (0001)晶圓40，貝晦一平行四邊形晶粒41之邊緣410皆沿 著{1〇ί〇}平面延伸。圖5係顯示排列於六方晶系晶圓50上 之三角形晶粒51，其爲依據本發明之多邊形晶粒之另一例 子。相似地，倘若使用(〇〇〇1)晶圓時，則每一三角形晶 粒51之邊緣Μ0皆沿著{1〇ί〇}平面延伸。 在晶粒切割製程中，藉由使用切割工具將晶圓40或50 切割或割裂成分離的平行四邊形或三角形晶粒41或51。既 然晶粒邊緣皆沿著容易切開的結晶平面1故切割工具於晶 圓40或50上產生平順且乾淨的切口。結果，依據本發明 之平行四邊形或三角形晶粒切割製程有效地降低切割工具 上之磨損與損壞。由切割工具之替換所引起的製程成本因 而降低。再者，因爲由新的切割工具取代舊的切割工具所 引起的中斷次數減少，所以製程時間縮短。此外，既然晶 8This paper size is applicable to the national standard (CNS) A4 specification (210 X 297 mm) 4651 2 9 B7 V. Description of the invention () In brief, Figures 2⑻ to 2 (C) show the hexagonal crystal system (0001) , (11 ϊ〇), and (10〇〇) plane. As substrates used for GaN-type semiconductor optoelectronic devices, sapphire and silicon carbide wafers are usually cut from crystals grown in the < 001 > direction, which is called a (0001) crystal pattern. According to the present invention, in order to fabricate a GaN-type semiconductor optoelectronic device on the main surface of a (0001) wafer, since the {l0i〇} plane is a plane that can be easily cut due to the arrangement of the bonding keys, each grain is The system is designed so that all edges are along the {l〇i〇} plane. It should be noted that: {1〇ί0} plane system represents a family of planes, including the (l0i〇) plane and its equivalent planes, the equivalent planes are (〇_ plane, (i 100) plane, (ϊ010 ) Plane, (〇ί 10) plane, and (1ϊ00) plane. With this arrangement, it is easy to use the cutting tool along the edge of each die from the (0001) wafer in the die cutting process. Cut out. The abrasion and damage of the cutting tool are greatly reduced. Referring to FIGS. 3 (a) to 3 (c), taking the manufacturing steps of the GaN-type light emitting diode as an example, the grain arrangement and In FIG. 3 (a), a hexagonal system wafer 30 is first prepared as a substrate of a GaN-type light-emitting diode. An n-type GaN-type compound semiconductor layer 31 is sequentially formed on the hexagonal system wafer 30. The active layer 32 formed by InGaN is used to generate blue light and a p-type GaN-type compound semiconductor layer 33. Then, a dry etching process is performed to partially remove the P-type GaN-type compound semiconductor layer 33, the active layer 32, and η Type GaN type compound semiconductor layer 31. As shown in FIG. 3 (b), After the etching process, part of the n-type GaN compound semiconductor layer 31 is exposed. 7 This paper size is applicable to the national standard of China (CNS > A4 specification (210 X 297 mm)) illlll — _ ^ · ΙΙΙΙΙΙΙ — (锖 Read the back side first) Notice of Exhibition # 'filling this page) /: f ^' 4 65 1 2 9 Β7 V. Description of the invention () Referring to FIG. 3 (c), a p-type electrode 34 and an n-type electrode 35 are formed at ρ, respectively. Type GaN-type compound semiconductor layer 33 and n-type GaN-type compound semiconductor layer 31 on the exposed surfaces. Thus, a GaN-type light-emitting diode is completed. In the same manner, many equal GaN-type light-emitting diodes can be fabricated into one A die array on a hexagonal wafer. As mentioned earlier, when a (0001) wafer is used, the edges of each die are arranged to extend along the {100%} plane. As a result, each die The grains are formed into a polygonal shape, and the internal angle of the polygonal shape is selected from an angle of a group consisting of 60 degrees and 120 degrees. FIG. 4 shows parallelogram crystals arranged on a hexagonal system wafer 40 Grain 41, which is an example of a polygonal grain according to the present invention. With the (0001) wafer 40, the edges 410 of the bevel-parallel quadrilateral grain 41 all extend along the {1〇ί〇} plane. FIG. 5 shows the triangular grains 51 arranged on the hexagonal crystal wafer 50, This is another example of a polygonal die according to the present invention. Similarly, if a (001) wafer is used, the edge M0 of each triangular die 51 extends along the {1〇ί〇} plane. In the die cutting process, the wafer 40 or 50 is cut or split into separate parallelogram or triangular grains 41 or 51 by using a cutting tool. Since the edges of the grains are all along the easy-to-cut crystalline plane1, the cutting tool produces a smooth and clean cut on the wafer 40 or 50. As a result, the parallelogram or triangle die cutting process according to the present invention effectively reduces wear and damage on the cutting tool. The cost of the process caused by the replacement of the cutting tool is reduced. Furthermore, because the number of interruptions caused by the replacement of the old cutting tool by the new cutting tool is reduced, the process time is shortened. Moreover, since crystal 8
訂 I I I I ά 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 46512 9 B7 五、發明說明（) 粒碎裂被有效地避免，故依據本發明之晶粒切割製程之良 率增強。 雖然本發明已參照具有六方晶系基板之半導體光電裝 置之例子加以詳細說明，但本發明可應用至具有閃鋅晶系 基板例如磷化鎵(GaP谨板之半導體光電裝置。在此種例子 中，磷化鎵晶圓經常係從沿著<111>方向成長的晶體上切割 下，其被稱之爲(111)晶圓。依據本發明，爲了製造半導體 光電裝置於(111)晶圓之主表面上，既然{li〇}平面因連結鍵 之排列而爲容易切開的平面，故每一晶粒係設計成所有邊 緣皆沿著{li〇}平面延伸。應注意者爲·· {li〇}平面係代表一 平面家族，包括(“〇)平面以及與其等效的平面’該等效平 面係(i 10)平面、（i〇l)平面、(Oi 1)平面、(1〇ί)平面、以及(01Ϊ) 平面。藉由此等排列，在晶粒切割製程中容易藉由切割工 具沿著每一晶粒之邊緣將其從(m)晶圓中切割出。因而， 在晶粒切割製程中切割工具容易產生平順且乾淨的切口， 並且既然晶粒碎裂被有效地避免故晶粒切割製程之良率增 強。 雖然本發明業已藉由較佳實施例作爲例示加以說明， 應了解者爲：本發明不限於此被揭露的實施例。相反地， 本發明意欲涵蓋對於熟習此項技藝之人士而言係明顯的各 種修改與相似配置。因此，申請專利範圍隻範圍應根據最 廣的證釋，以包容所有此類修改與相似配置。Order IIII ά This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 46512 9 B7 V. Description of the invention () Grain fragmentation is effectively avoided, so the grain cutting process according to the present invention is good Rate enhancement. Although the present invention has been described in detail with reference to an example of a semiconductor optoelectronic device having a hexagonal crystal-based substrate, the present invention can be applied to a semiconductor optoelectronic device having a zinc-based crystal substrate such as gallium phosphide (GaP plate). In such an example The gallium phosphide wafer is often cut from a crystal grown in the < 111 > direction, which is called a (111) wafer. According to the present invention, in order to manufacture a semiconductor optoelectronic device on the (111) wafer, On the main surface, since the {li〇} plane is a plane that can be easily cut due to the arrangement of the bonding bonds, each grain system is designed so that all edges extend along the {li〇} plane. It should be noted that {li 〇} plane system represents a family of planes, including ("〇) plane and planes equivalent to it 'the equivalent plane system (i 10) plane, (i〇l) plane, (Oi 1) plane, (1〇ί ) Plane and (01Ϊ) plane. With this arrangement, it is easy to cut each die along the edge of each die from the (m) wafer in the die cutting process by the cutting tool. Cutting tools in the pellet cutting process tend to produce smooth and clean cuts, and Since chip cracking is effectively avoided, the yield of the chip cutting process is enhanced. Although the present invention has been described by way of example, it should be understood that the present invention is not limited to the disclosed embodiment. On the contrary, the present invention is intended to cover various modifications and similar configurations that are obvious to those skilled in the art. Therefore, the scope of patent application should only be based on the broadest interpretation to encompass all such modifications and similar configurations.
本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)
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I I 訂 _ I άI I order _ I ά
4 6512 9 五、發明說明（） 【圖式之簡單說明】 圖1係顯示先前技藝中半導體光電裝置在晶圓上之排 列之頂視圖； 取 圖2(a)至2(c)係分別顯示六方晶系之(0001)、（10〇)、 與(l〇i〇)平面； 圖3⑻至3(c)係依序顯示發光二極體之製造步驟之剖面 圖； 圖4係顯示依據本發明平行四邊形晶粒於晶圓上之排 列與方位之頂視圖；以及 圖5係顯示係顯示依據本發明三角形晶粒於晶圓上之 排列與方位之頂視圖。 [符觀明） 10晶圓 11晶粒 12晶粒邊緣 30六方晶系晶圓 31 η型GaN型化合物半導體層 32主動層 33 P型GaN型化合物半導體層 34 P型電極 35 η型電極 4〇六方晶系晶圓 41平行四邊形晶粒4 6512 9 V. Description of the invention (Simplified description of drawings) Figure 1 is a top view showing the arrangement of semiconductor optoelectronic devices on a wafer in the prior art; Figures 2 (a) to 2 (c) are shown separately The (0001), (100), and (110) planes of the hexagonal crystal system; Figs. 3 (a) to 3 (c) are cross-sectional views sequentially showing the manufacturing steps of the light emitting diode; A top view of the arrangement and orientation of the parallelogram die on the wafer according to the invention; and FIG. 5 is a top view showing the arrangement and orientation of the triangle die on the wafer according to the invention. [Fu Guanming] 10 wafers 11 grains 12 grain edges 30 hexagonal wafers 31 n-type GaN-type compound semiconductor layer 32 active layer 33 P-type GaN-type compound semiconductor layer 34 P-type electrode 35 η-type electrode 40 Wafer 41 Parallelogram crystal grains
未紙張尺度適用中國國家標準（CNS〉A4規格（210 X 297公釐） 4 6512 9 A7 五、發明說明（） 410 邊緣 50六方晶系晶圓 51三角形晶粒 510 邊緣Unprinted dimensions apply Chinese national standard (CNS> A4 specification (210 X 297 mm) 4 6512 9 A7 V. Description of the invention () 410 Edge 50 Hexagonal system wafer 51 Triangle grain 510 Edge
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ά 本紙張尺度適用_國國家標準（CNS)A4規格（210 χ 297公釐）ά This paper is applicable to the national standard (CNS) A4 (210 χ 297 mm)