JP2002170992A - Semiconductor optoelectronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor optoelectronic device in which chipping of die can be prevented effectively, wear and damage of a cutting tool can be reduced greatly, and the yield of dicing process can be enhanced. SOLUTION: In a wafer having a hexagonal system or zinc blend crystal structure, multiple semiconductor optoelectronic devices are formed in an array of nonrectangular dies. When a (0001) hexagonal system wafer is used, respective edges of the dies are arranged along 10-10} plane. When a wafer having (111) zinc blend crystal structure is used, respective edges of the dies are arranged along 1-10} plane. By such an arrangement, each internal angle of the die is set at 60 deg. or 120 deg.. Since all edges of a die are drawn along easily separable similar crystal faces during dicing process, the wafer can be diced well into dies by means of the cutting tool.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor optoelectronic device having a substrate cut in a non-rectangular shape, and more particularly to a parallelogram or triangular substrate having the same side walls all having the same crystal structure. The present invention relates to such a semiconductor optoelectronic device.

[0002]

2. Description of the Related Art A semiconductor device, such as a light emitting diode, a laser or a photodetector, generally comprises an epitaxial compound semiconductor layer grown on a single crystal substrate. The single crystal substrate is selected mainly with reference to crystal characteristics, such as the crystal structure and the lattice constant of the epitaxial compound semiconductor layer and the single crystal substrate. Generally, a single crystal substrate belonging to the same crystal system as the epitaxial compound semiconductor layer can easily and quickly form the epitaxial compound semiconductor layer on the upper surface thereof. Further, by making the lattice constant of the single crystal substrate as close as possible to the lattice constant of the epitaxial compound semiconductor, the occurrence of tensile strain or compressive strain occurring in the epitaxial compound semiconductor layer is prevented.

In recent years, gallium nitride (GaN) type compound semiconductor materials have been spotlighted as materials for manufacturing blue, green and blue-green light emitting devices. For example, a GaN-type light emitting diode that produces a blue light ray has already been commercialized. As described above, the GaN-type light emitting diode is generally formed on a sapphire substrate or a silicon carbide substrate belonging to a hexagonal system due to crystal considerations.

FIG. 1 is a plan view showing a sapphire or silicon carbide wafer 10 used as a substrate of a GaN type light emitting diode. Through a suitable semiconductor manufacturing process, a number of similar GaN light emitting diodes (not shown) are formed together on the wafer 10. Conventionally, these G
The aN-type light emitting diodes are arranged in an array of rectangular elements 11 called "die", and the dimension of the edge is formed in millimeters or smaller. A hexagonal wafer 10 is cut along the die edge 12 by a cutting tool, for example with a scriber having a diamond knife, to obtain a separate GaN light emitting diode for packaging.

[0005]

However, since the wafer 10 on which sapphire or silicon carbide is formed is not a cubic crystal, when the wafer is cut into a rectangular die, the wafer 10 is smooth and clean. Can not be cut. Further, as the dicing process proceeds, wear and damage of the cutting tool increase. As a result, the consumption of the cutting tool becomes severe, and the cost of the manufacturing process increases. Also, the manufacturing process is interrupted and a new cutting tool must be replaced, which increases the manufacturing time. Further, the yield of the dicing process for a rectangular die is reduced due to the effects of die chipping and the like.

[0006]

SUMMARY OF THE INVENTION It is a principal object of the present invention to provide a semiconductor optoelectronic device having a non-rectangular substrate cut and formed along similar crystal planes of a wafer. The non-rectangular substrate has a main surface on which a layered semiconductor structure is formed on an upper surface, a side wall surface surrounding the main surface,
Having. The main surface has a polygonal shape, in particular, a parallelogram or a triangle, and all the internal angles are formed at 60 degrees or 120 degrees. Further, the side wall surfaces are all located in the same crystal face.

According to the present invention, first, a wafer of sapphire, silicon carbide, gallium phosphide, or the like is prepared. On the main surface of these wafers, a number of semiconductor optoelectronic structures, such as light emitting diodes, are manufactured into an array of polygonal dies, all edges of which are on the same crystal face of the wafer. Stretched along. Also, each polygonal die is formed such that all interior angles are between 60 degrees and 120 degrees. Subsequently, the wafer is cut along the edges of the die into independent polygon dies using a cutting tool. Therefore, all die edges are stretched along the wafer crystal plane,
The cutting tool can cut the wafer smoothly and neatly into dies.

Therefore, in the dicing step of the present invention, a flat and clean cut surface can be formed by the cutting tool. Further, wear and damage of the cutting tool can be significantly reduced. Furthermore, since the chipping of the die is effectively prevented, the yield of the dicing process according to the present invention is improved.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
A preferred embodiment of the present invention will be described in detail.

As described above, a hexagonal wafer, for example,
Sapphire or silicon carbide wafers are generally GaN
It is used as a substrate of a type semiconductor optoelectronic device. FIG.
(A) to FIG. 2 (c) show the hexagonal crystal axis and the crystal.
Surface. As shown in FIGS. 2 (a) to 2 (c),
The hexagonal system has three axes a-₁,
a ₂, A₃And these axes a₁, A₂, A₃Orthogonal to
It is defined in a coordinate system composed of the C axis. a₁, A₂, A
₃Angle between any two axes is 120 degrees
It is. In other words, FIGS. 2A to 2C
Are hexagonal {0001} and {11 bar 2
0｝

[0011]

(Equation 3) {10 bar 10}

[0012]

(Equation 4) Is shown.

[0013] Sapphire and silicon carbide wafers are generally used as substrates used in GaN semiconductor optoelectronic devices.
Since it is obtained by cutting a crystal grown along the <0001> direction, it is called a (0001) wafer.

According to the present invention, in order to form a GaN type semiconductor optoelectronic device on the main surface of a (0001) wafer,
Each die is designed with edges along the {10 bar 10} plane, since the {10 bar 10} plane is the plane that is easily cut by the bond arrangement. Here, the {10 bar 10} plane is a plane house including the {10 bar 10} plane and its equivalent plane, and the equivalent plane is {01 bar 10} plane, {bar 1100} plane,
{Bar 1010} plane, {0 Bar 110} plane, {1 Bar 100} plane. With such an arrangement, in the dicing process, they can be more easily cut along the edges of the dies from the (0001) wafer by the cutting tools, and the wear and damage of the cutting tools can be significantly reduced.

Referring to FIGS. 3A to 3C, the arrangement and orientation of the dies on the hexagonal substrate of the present invention will be described by taking a manufacturing process of a GaN type light emitting diode as an example. As shown in FIG. 3A, first, a hexagonal wafer 30 is prepared as a substrate of a GaN-type light emitting diode. The n-type GaN-type compound semiconductor layer 31, an active layer 32 made of InGaN, which generates blue light, and a p-type GaN-type compound semiconductor layer 33 are sequentially formed on the hexagonal wafer 30. You. Then, as shown in FIG. 3B, the p-type GaN compound semiconductor layer 33, the active layer 32, and a part of the n-type GaN compound semiconductor layer 31 are removed by dry etching, and the n-type GaN compound semiconductor layer 31 is removed. Only a part of the type compound semiconductor layer 31 is exposed.

Finally, as shown in FIG.
A p-type electrode 34 and an n-type electrode 35 are formed on the surfaces of the aN-type compound semiconductor layer 33 and the n-type GaN type compound semiconductor layer 31, respectively, to complete a GaN-type light emitting diode.

In this way, many identical GaN-type light emitting diodes are manufactured in a die array located on a hexagonal wafer. As described above, when a (0001) wafer is used, the edge of each die is {1010}
They are arranged to extend along a plane. As a result, each die is formed into a polygon, and the interior angle of the polygon is any angle selected from the group consisting of 60 to 120 degrees.

FIG. 4 is a plan view showing parallelogram dies 41 arranged on a hexagonal wafer 40. (0001)
If a wafer 40 is used, all edges 410 of each parallelogram die 41 extend along the {10 bar 10} plane. FIG. 5 is a plan view showing the triangular dies 51 arranged on the hexagonal wafer 50. Similarly, (00
01) When the wafer 50 is used, all the edges 510 of each triangular die 51 extend along the {10 bar 10} plane.

In the dicing step, the wafer 40 or 50 is cut into separate parallelogram or triangular dies 41 or 51 by a cutting tool. Since the edges of the die are all along a crystal plane that can be easily cut, the cutting tool can form a flat and clean cut in the wafer 40 or 50. Therefore, according to the dicing process of the parallelogram or the triangular die of the present invention, the wear and damage of the cutting tool can be effectively reduced, so that the manufacturing cost by replacing the cutting tool is reduced. Also, the production time is shortened because the process of replacing the old cutting tool with the new cutting tool is less frequently stopped.
Furthermore, since die chipping is effectively prevented,
The yield of the dicing process according to the present invention is improved.

Although the present invention has been described in detail with reference to an example of a semiconductor optoelectronic device having a hexagonal system substrate, the present invention relates to a semiconductor optoelectronic device having a zinc blende crystal structure, for example, a gallium phosphide (GaP) substrate. It can also be applied. In this case, the gallium phosphide wafer is usually called a (111) wafer because it is cut from a crystal grown along the <111> direction. In accordance with the present invention, to fabricate semiconductor optoelectronic devices on the main surface of the (111) wafer, each die has all the dies because the {1 bar 10} plane is a plane that is easily separated due to bond alignment. The edges can be designed to extend along a {1 bar 10} plane that is easily cut with an array of bonds. Here, {1 bar 10}
The plane is a plane house including a {1 bar 10} plane and its equivalent plane, and the equivalent plane is a {bar 110} plane,
{Bar 101} plane, {0 bar 11} plane, {10 bar 1} plane, {01 bar 1} plane. In such an arrangement, in the dicing process, they can be easily cut from the (111) wafers along the edges of the respective dies by a cutting tool. Therefore, in the dicing process, a flat and clean cut surface can be formed, and chipping of the die is effectively prevented, so that the yield of the dicing process is improved.

The embodiments of the present invention described above are specific examples that have been submitted in order to briefly explain the technology of the present invention, and the present invention is not limited to the above-described embodiments.
Various modifications are possible within the scope of the present invention.

[Brief description of the drawings]

FIG. 1 is a plan view showing a state where a conventional semiconductor optoelectronic device is arranged on a wafer.

2 (a) to 2 (c) are diagrams showing hexagonal {0001 {11 bar 20} 10 bar 10} planes, respectively.

FIGS. 3A to 3C are cross-sectional views sequentially showing a manufacturing process of a light emitting diode.

FIG. 4 is a plan view showing a parallelogram die arranged on a wafer according to the present invention.

FIG. 5 is a plan view showing triangular dies arranged on a wafer according to the present invention.

[Explanation of symbols]

 Reference Signs List 10 wafer 11 die 12 edge 30 hexagonal wafer 31 n-type GaN compound semiconductor layer 32 active layer 33 p-type GaN compound semiconductor layer 34 p-type electrode 35 n-type electrode 40 hexagonal wafer 41 parallelogram die 410 edge 50 hexagonal wafer 51 triangular die 510 edge

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F041 AA41 CA23 CA33 CA34 CA37 CA40 CA46 CA76 5F049 MA01 MB07 NA08 PA17 SS01 SS03

Claims (6)

[Claims] The present invention has a main surface and a plurality of side wall surfaces surrounding the main surface, wherein the main surface is a polygonal surface, and an angle in a group consisting of 60 degrees to 120 degrees or the like is adopted as an inner angle thereof. A semiconductor optoelectronic device comprising: a substrate having a plurality of side walls, each of which has a similar crystal face, and a layered semiconductor structure formed on the main surface of the substrate. 2. The semiconductor optoelectronic device according to claim 1, wherein said substrate employs a kind of material in a group consisting of sapphire and silicon carbide. 3. The main surface is located on a {0001} surface, and each of the plurality of side wall surfaces has the following formula: The semiconductor optoelectronic device according to claim 2, wherein: 4. The semiconductor optoelectronic device according to claim 1, wherein said substrate is formed of gallium phosphide. 5. The method according to claim 1, wherein the main surface is located on a {111} plane, and each of the plurality of side wall surfaces has the following formula: The semiconductor optoelectronic device according to claim 4, wherein: 6. The semiconductor optoelectronic device according to claim 1, wherein the main surface is a parallelogram or a triangle.