A7 B7 4 6 33 0 8 6328twf1/002 第89116341號說明書修正頁 修正日期90/7/23 經濟部智慧財產局員工消費合作社印製 五、發明說明（I ) 本發明是有關於一種積體電路的製造方法’且特別是 有關於一種動態隨機存取記憶體中避免位元線接觸窗之間 發生短路的方法。 爲因應電子元件輕、薄、短、小之趨勢’半導體元件 的製造方法必須提高其積集度以符合需求。提高積集度的 方法，除了縮小半導體元件其構件本身的尺寸之外，半導 體元件其構件間的距離亦必須縮小。然而，不論是縮小半 導體元件其構件本身的尺寸，或是縮小半導體元件其構件 間的距離，在製程上均會衍生一些問題。以下係以習知線 寬縮小之後，位元線接觸窗在形成的過程中所面臨的一些 I..::問題作爲說明。 請參照第1圖，第2圖與第3圖，習知記憶元件之位 % 元線接觸窗，係在基底100形成隔離區103，界定出主動 @區102之後，在基底100上形成彼此相互平行的字元線 f l 106，其後，再於基底100上沉積硼磷矽玻璃(BPSG)介電 攻令層108，並在介電層108之中形成裸露出主動區102的位 系ί::元線接觸窗開口 Η0，最後再於位元線接觸窗開口 110之 中塡入複晶矽層112以形成位元線接觸窗。 隨著元件高密度的需求，不論是字元線106本身的寬 度或是字元線106其彼此之間的間隙(Gap)寬度均必須縮小 以符合高度積集化之目的。但是，字元線106其彼此間的 間隙104寬度縮小之後，將使得間隙的高寬比(Aspect rati〇) 增加。當介電層108塡入此種具有高寬比的間隙i〇4時， 則非常容易導致如隧道般之空孔(Key H〇le)114的形成。此 本紙張尺度適用中國國家標準（CNS>A4規格（2]0 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝 -----訂---------線 463308 6328twf.doc/006 A7 ___ B7 五、發明說明（>) 種隧道般之空孔1H的形成，會使得後續所形成之位元線 接觸窗開口 Π0其彼此之間透過空孔114而相互導通。 另一方面，線寬縮小之後，位元線接觸窗開口 110的 高寬比亦隨之而增加。爲了使塡充於位元線接觸窗開口 110 之中的複晶矽層112具有良好的階梯覆蓋能力，複晶矽層 112係採用化學氣相沉積的方式來形成。然而，具有良好 階梯覆蓋能力之導體層116將會使得與位元線接觸窗開口 110相互導通的空孔114亦會塡入導體層116，因而導致兩 相鄰的位元線接觸窗112透過空孔114之中的導體層116 而發生短路。 爲防止位元線接觸窗發生短路，習知一種避免形成空 孔的方法，係增加硼磷矽玻璃介電層中硼、磷的濃度，以 增加介電層的流動性。然而此方法卻有自動摻雜（Auto-Doping)的風險。 習知另一種避免形成空孔的方法，係藉由硼磷矽玻璃 介電層其回火溫度的提昇來達到目的。但是，其回火的溫 度則必須考量整個元件的熱預算(Thermal Budget)。 此外，習知爲了避免形成空孔的方法，亦有透過增加 字元線與字元線之間之間隙的空間，降低其高寬比來達到 目的，而此方法卻與提昇積集之目標背道而馳。 本發明提供一種避免在沉積介電層的過程中因爲空孔 的形成而導致後續所形成之位元線接觸窗發生短路的方 法。 本發明提出一種避免位元線接觸窗之間發生短路的方 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公# ) (請先間讀背面之注意事項再填寫本頁) '.^1 ~SJI n n 線丨 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 463308 6 3 2 8twf . doc/ 0 06 A7 __B7 五、發明說明（> ) 法，此方法係在定義字元線圖案時，利用減少兩相鄰位元 線接觸窗之間之字元線的寬度的特殊設計，以增加兩相鄰 字元線之間的空間、降低其高寬比，以使後續沉積之介電 層，在此間隙不會發生空孔，進而使得所形成之位元線接 觸窗開口，可以透過無空孔之介電層加以阻隔而無法相互 導通。 本發明提出一種具有溝渠式電容之動態隨機存取記億 體的製造方法，此方法係先在基底中形成溝渠式電容器， 之後，在基底上形成一第一字元線與一第二字元線，此第 一字元線與第二字元線之側壁具有數個相互對應的突出區 與數個相互對應的凹陷區，接著，在基底上形成一介電層， 再於突出區之間的介電層中形成數個位元線接觸窗並塡入 導體材料以形成位元線接觸窗，最後再於基底上形成與位 元線接觸窗電性連接的位元線。 依照本發明實施例所述，上述凹陷區之間之間隙的高 寬比較低於突出區之間之間隙的高寬比，因此凹陷區之間 的間隙中所形成的介電層不會形成空孔，使得所形成之位 元線接觸窗開口，可以透過無空孔之介電層加以阻隔而無 法相互導通。因此，以階梯覆蓋能力較佳的化學氣相沉積 法在位元線接觸窗開口之中塡入導體材料時，雖然在位元 線接觸窗開口周圍，與其相互導通的空孔亦有塡入導體材 料的可能，但是，由於無空孔之介電層可以阻隔兩相鄰的 位元線接觸窗，因此可以避免兩相鄰的位元線接觸窗發生 短路的現象。 5 本紙張尺度適用中國國家標準（CNS)A4規^ (210:297公釐) --------------------訂---------線 I (請先閱讀背面之注意事項再填寫本頁) 463308 6328twf.doc/006 A7 _B7 五、發明說明（4) 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1圖是習知一種記憶元件之上視圖； 第2圖是第1圖之II-II剖面的剖面圖； 第3圖是第1圖之III-III剖面的剖面圖； 第4圖係繪示依照本發明較佳實施例之一種具有溝渠 式電容之動態隨機存取記憶體之上視圖； 第5圖係繪示第4圖其V-V剖面之剖面圖； 第6圖係繪示第4圖其VI-VI剖面之剖面圖；以及 第7圖係繪示第4圖其VII-VII剖面之剖面圖。 圖式之標記說明： 100、400 :基底 102、 402 :主動區 103、 403 :隔離區 104 :間隙 106、406a、406b :字兀>線 108、408 :介電層 110、410 :接觸窗開口 112、116、412、416 :導體層 114、414 :空孔 418、420 :寬度 422 :突出區 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -n n n n 一6,1 » 1^- n n _ϋ n 1 ϋ 經濟部智慧財產局員工消費合作社印製 463308 6328twf.d〇c/006 A7 __B7 五、發明說明（f) 424 :凹陷區 426、428 :間隙 實施例 第4圖係繪示依照本發明較佳實施例之一種具有溝渠 式電容之動態隨機存取記憶體之上視圖。第5圖、第6圖 與第7圖係分別繪示第4圖其V-V剖面、VI-VI剖面以及 VII-VII剖面之剖面圖。 請參照第4圖、第5圖第6圖與第7圖，首先，在基 底400中形成隔離區403，以在基底400上界定出主動區 402。隔離區403的形成方法例如爲淺溝渠隔離法（STI)。 接著，在基底400中形成溝渠式電容器404。 之後，在基底400上形成一層介電層405其材質例如 爲氧化矽，形成的方法例如爲熱氧化法。接著，在基底400 上形成一層導體層，並經由微影與蝕刻製程，以形成字元 線406a與406b。字元線406a與406b中，跨越主動區402 以及主動區402周圍的部分，其寬度418均維持原佈局之 線寬，而在兩主動區402之間的部分，其寬度420則略小 於原佈局之線寬，如第5圖與第6圖所示。換言之，字元 線406a與字元線406b的側壁具有相互對應的突出區422 與凹陷區424，其中，突出區422係字元線406a、406b跨 越主動區402以及主動區402周緣的部分；凹陷區424係 字元線406a、406b跨越主動區402與主動區402之間的部 分。突出區422之間的間隙426的寬度較小於凹陷區424 之間之間隙42.8的寬度。 7 ^紙張尺度適用中@國家^準（CNS)A4規格（210 X 297公 (諝先閱讀背面之注意事項再填窝本頁) 訂j丨丨I!線 _ 經濟部智慧財產局員工消費合作社印製 4 6 3 3 0 8 A7 B7 6328twf1/002 五、發明說明（石） (請先間讀背面之注意事項再填寫本頁) 用以形成上述字元線406a與字元線406b之導體層例 如爲複晶矽，其形成的方法例如爲化學氣相沉積法；而字 元線406a、406b其寬度418 ' 420的特殊設計可以在光罩 上直接設計(Layout)出，然後經由微影與蝕刻製程以形成， 以得到最佳的製程空間(Process Window)。舉例來說，字元 線406a與字元線406b的寬度418爲200nm，較佳的字元 線406a與字元線406b的寬度420例如是185nm至195nm。 經濟部智慧財產局員工消費合作社印製 接著，在基底400上形成一層介電層408，以覆蓋字 元線406a、406b以及字元線406a與字元線406b之間的間 隙426與408。由於突出區422之間的間隙426其寬度較 小於凹陷區424之間之間隙428的寬度，間隙428的高寬 比較小於間隙426的高寬比，因此，當介電層408覆蓋間 隙428時，其覆蓋的效果較好並不會形成空孔，如第5圖 所示；而覆蓋於間隙426之介電層408即使其覆蓋的效果 較差，而形成如第6圖所示的空孔414時，亦可以透過間 隙428之中所形成的介電層408加以阻隔，使得兩相鄰之 突出區422之間之間隙428中所形成的空孔414不會相互 導通，其結果可由第4圖其VII-VII剖面之剖面圖(第7圖） 淸楚得知。 之後，以微影與蝕刻技術在突出區422之間(間隙428) 的介電層408中形成位元線接觸窗開口 410，以裸露出主 動區402之基底400表面。位元線接觸窗開口 410將與間 隙426之介電層408中所形成之空孔414相互導通，但是， 由於凹陷區424之間（間隙428)所形成之介電層408並無空 8 本紙張尺度適用巾國國家標準<CNS)A4規格（2】〇x 297公釐） A7 B7 463308 6 3 2 8 twf . doc /0 0 6 五、發明說明（9) 孔，因此兩相鄰之位元線接觸窗410並不會透過空孔414 而相互導通。 接著，在位元線接觸窗開口 4丨0之中塡入導體材料 412，以形成位元線接觸窗。爲了增加導體材料4〗2的階 梯覆蓋能力，較佳的導體材料412的形成方法例如爲化學 氣相沉積法，而其材質例如爲複晶矽。由於以化學氣相沉 積法進行材料層之沉積時具有良好的階梯覆蓋能力’因此 當導體材料412係以化學氣相沉積法沉積時’與位元線接 觸窗開口 410相互導通的空孔414亦會塡入導體材料，標 示爲416。由於間隙428所形成的介電層408可以加以阻 隔，因此兩相鄰之位元線接觸窗412 ’並不因空孔414所 塡入之導體材料416而相互導通’進而造成短路的現象。 之後，在基底400上形成一層導體層，並經由微影與 蝕刻製程以形成與位元線接觸窗412連接的位元線。 簡而言之，上述方法係在定義字元線圖案時，減少兩 相鄰位元線接觸窗之間之字元線的寬度，以增加此間隙之 兩相鄰字元線之間的間隙寬度，以降低其高寬比，使後續 沉積之介電層在此間隙不會發生空孔，進而使得所形成之 位元線接觸窗開口，可以透過無空孔之介電層而加以阻 隔。 因此，根據上述實施例所述，本發明具有下列優點： 1. 本發明可以避免位元線接觸窗之介電層產生空孔。 2. 本發明可以避免位元線接觸窗之間發生短路。 3. 本發明可以在不減少積集度的情況下，達到避免空 9 本紙張尺度適用中國@豕標準（CNS)A4規格（21〇 X 297公楚） (請先閱讀背面之注意事項再填寫本頁) — II•訂- if —----線 經濟部智慧財產局員工消費合作社印製 463308 6 3 2 e twf . doc / 0 0 6 A7 _ B7 五、發明說明（》） 孔形成之目的。 雖然本發明已以具有溝渠式電容器之動態隨機存取記 憶體作爲較佳實施例揭露如上，然其並非用以限定本發 明，任何熟習此技藝者，在不脫離本發明之精神和範圍內， 當可作各種之更動與潤飾，因此本發明之保護範圍當視後 附之申請專利範圍所界定者爲準。 —^----„------ .--------- 訂 i.-------線 (請先Μ讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用+國國家標準（CNS)A4規格（210x297公釐）A7 B7 4 6 33 0 8 6328twf1 / 002 No. 89116341 Revised Sheet Revision Date 90/7/23 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention (I) The present invention relates to an integrated circuit The manufacturing method ', and more particularly, it relates to a method for avoiding a short circuit between a bit line contact window in a dynamic random access memory. In response to the trend of lighter, thinner, shorter, and smaller electronic components', the manufacturing method of semiconductor devices must increase their accumulation to meet demand. In order to increase the accumulation degree, in addition to reducing the size of the components of the semiconductor element itself, the distance between the components of the semiconductor element must also be reduced. However, whether it is reducing the size of the components of the semiconductor element itself or reducing the distance between the components of the semiconductor element, there will be some problems in the manufacturing process. The following is a description of some I .. :: problems faced by the bit line contact window during the formation of the conventional line width reduction. Please refer to Fig. 1, Fig. 2 and Fig. 3. The position of the memory cell is shown in Fig. 1. The element line contact window is formed on the substrate 100 to form an isolation region 103. After defining the active @region 102, each other is formed on the substrate 100. Parallel word lines fl 106. Thereafter, a borophosphosilicate glass (BPSG) dielectric attack layer 108 is deposited on the substrate 100, and a bit system is formed in the dielectric layer 108 to expose the active region 102. : The element line contact window opening Η0, and finally a polycrystalline silicon layer 112 is inserted into the bit line contact window opening 110 to form a bit line contact window. With the demand for high-density components, both the width of the word lines 106 and the width of the gaps between the word lines 106 must be reduced to meet the purpose of high accumulation. However, when the width of the gap 104 between the word lines 106 is reduced, the aspect ratio of the gap will increase. When the dielectric layer 108 enters such a gap i04 having an aspect ratio, it is very easy to cause the formation of a tunnel-like hole (Key Hole) 114. This paper size applies to Chinese national standards (CNS > A4 size (2) 0 X 297 mm) (Please read the precautions on the back before filling this page) -Line 463308 6328twf.doc / 006 A7 ___ B7 V. Description of the invention (>) The formation of tunnel-like holes 1H will make the subsequent bit lines contact the window openings Π0 and pass through the holes 114 between each other On the other hand, after the line width is reduced, the aspect ratio of the bit line contact window opening 110 also increases. In order to fill the polycrystalline silicon layer 112 in the bit line contact window opening 110, It has good step coverage, and the polycrystalline silicon layer 112 is formed by chemical vapor deposition. However, the conductor layer 116 with good step coverage will make the holes that are in electrical communication with the bit line contact window openings 110. 114 also penetrates into the conductive layer 116, which causes two adjacent bit line contact windows 112 to short-circuit through the conductive layer 116 in the void 114. In order to prevent the bit line contact windows from being short-circuited, it is known to avoid formation Void method, adding borophosphosilicate glass dielectric layer The concentration of boron and phosphorus increases the fluidity of the dielectric layer. However, this method has the risk of auto-doping. It is known that another method to avoid the formation of voids is through the use of borophosphosilicate glass. The electrical layer has an increase in the tempering temperature to achieve the purpose. However, the tempering temperature must consider the thermal budget of the entire component. In addition, in order to avoid the formation of voids, there is also an increase in characters The space of the gap between the line and the character line reduces its aspect ratio to achieve the purpose, but this method runs counter to the goal of improving the accumulation. The present invention provides a method for avoiding the problem of voids during the process of depositing a dielectric layer. A method for forming a short circuit of a bit line contact window formed later. The present invention proposes a method for avoiding a short circuit between the bit line contact windows. The paper size is applicable to China National Standard (CNS) A4 (210 X 297) Public #) (Please read the notes on the back before filling in this page) '. ^ 1 ~ SJI nn line 丨 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 463308 6 3 2 8twf .doc / 0 06 A7 __B7 V. Description of the invention (>) method, this method is to reduce the word line between two adjacent bit line contact windows when defining the word line pattern The special design of the width of the electrode to increase the space between two adjacent word lines and reduce the aspect ratio, so that the subsequent deposited dielectric layer will not have voids in this gap, thus making the formed bits The opening of the line contact window can be blocked by a dielectric layer without voids and cannot be connected to each other. The invention provides a method for manufacturing a dynamic random access memory device with a trench capacitor, which first forms a trench in a substrate Then, a first word line and a second word line are formed on the substrate. The sidewalls of the first word line and the second word line have a plurality of corresponding protruding areas and a plurality of corresponding sides. Then, a dielectric layer is formed on the substrate, several bit line contact windows are formed in the dielectric layer between the protruding regions, and a conductive material is inserted into the bit line contact window to form a bit line contact window. Bit lines are formed on the substrate A bit line electrically connected to the window. According to the embodiment of the present invention, the height-to-width ratio of the gaps between the recessed regions is lower than the height-to-width ratio of the gaps between the protruding regions, so the dielectric layer formed in the gaps between the recessed regions does not form voids. The holes allow the formed bit line to contact the opening of the window, which can be blocked by the dielectric layer without voids and cannot be connected to each other. Therefore, when a chemical vapor deposition method with better step coverage capability is used to pierce the conductor material into the bit line contact window openings, although the bit line contact window openings are surrounded by the conductive holes, there are also pierced conductors. Materials are possible. However, since a dielectric layer without holes can block two adjacent bit line contact windows, a short circuit between two adjacent bit line contact windows can be avoided. 5 This paper size applies the Chinese National Standard (CNS) A4 ^ (210: 297 mm) -------------------- Order -------- -Line I (please read the notes on the back before filling this page) 463308 6328twf.doc / 006 A7 _B7 V. Description of the invention (4) In order to make the above and other objects, features, and advantages of the present invention more obvious and understandable In the following, preferred embodiments are described in detail, in conjunction with the accompanying drawings, which are described in detail as follows: Brief description of the drawings: Figure 1 is a top view of a conventional memory element; Figure 2 is II- of Figure 1- Section II is a sectional view; FIG. 3 is a sectional view of the III-III section of FIG. 1; and FIG. 4 is a diagram illustrating a dynamic random access memory having a trench capacitor according to a preferred embodiment of the present invention. FIG. 5 is a sectional view of the VV section of FIG. 4; FIG. 6 is a sectional view of the VI-VI section of FIG. 4; and FIG. 7 is a view of VII-VII of FIG. 4 Sectional section view. Description of the drawing symbols: 100, 400: substrate 102, 402: active area 103, 403: isolation area 104: gap 106, 406a, 406b: word > line 108, 408: dielectric layer 110, 410: contact window Openings 112, 116, 412, 416: Conductor layer 114, 414: Holes 418, 420: Width 422: Protruded area This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the back first Please fill in this page again) -nnnn -1,1 »1 ^-nn _ϋ n 1 印 Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 463308 6328twf.d〇c / 006 A7 __B7 V. Description of the invention (f) 424: recessed area 426, 428: gap embodiment. FIG. 4 is a top view of a dynamic random access memory with trench capacitor according to a preferred embodiment of the present invention. Figures 5, 6, and 7 are cross-sectional views of the V-V, VI-VI, and VII-VII sections of Figure 4, respectively. Referring to FIG. 4, FIG. 5, FIG. 6, and FIG. 7, first, an isolation region 403 is formed in the substrate 400 to define an active region 402 on the substrate 400. A method for forming the isolation region 403 is, for example, a shallow trench isolation method (STI). Next, a trench capacitor 404 is formed in the substrate 400. After that, a dielectric layer 405 is formed on the substrate 400, and the material is, for example, silicon oxide, and the method for forming the dielectric layer 405 is, for example, a thermal oxidation method. Next, a conductor layer is formed on the substrate 400, and the lithography and etching processes are performed to form the character lines 406a and 406b. The width 418 of the word lines 406a and 406b that spans the active area 402 and the surrounding area of the active area 402 maintains the line width of the original layout, and the portion 420 between the two active areas 402 is slightly smaller than the original layout The line width is shown in Figures 5 and 6. In other words, the sidewalls of the word line 406a and the word line 406b have protruding areas 422 and recessed areas 424 corresponding to each other. The protruding areas 422 are portions of the word lines 406a and 406b that cross the active area 402 and the periphery of the active area 402. The area 424 is a character line 406a, 406b that spans a portion between the active area 402 and the active area 402. The width of the gap 426 between the protruding regions 422 is smaller than the width of the gap 42.8 between the recessed regions 424. 7 ^ Paper size is applicable @ 国 ^ 准 （CNS) A4 size (210 X 297 male (谞 Read the precautions on the back before filling in this page) Order j 丨 丨 I! _ Intellectual Property Bureau, Ministry of Economic Affairs, Consumer Consumption Cooperative Printed 4 6 3 3 0 8 A7 B7 6328twf1 / 002 5. Description of the invention (stone) (please read the precautions on the back before filling this page) Used to form the conductor layer of the above character line 406a and character line 406b For example, it is polycrystalline silicon, and its formation method is, for example, chemical vapor deposition; and the special design of the character lines 406a and 406b with a width of 418'420 can be directly designed on the photomask, and then lithography and The etching process is used to form to obtain the optimal process window. For example, the width 418 of the character lines 406a and 406b is 200nm, and the widths of the better character lines 406a and 406b are 200b. 420 is, for example, 185nm to 195nm. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Next, a dielectric layer 408 is formed on the substrate 400 to cover the character lines 406a, 406b, and between the character lines 406a and 406b. Gaps 426 and 408. Because of the gap between the protruding areas 422 The width of 426 is smaller than the width of the gap 428 between the recessed regions 424. The height and width of the gap 428 are smaller than the aspect ratio of the gap 426. Therefore, when the dielectric layer 408 covers the gap 428, the coverage effect is better and No voids will be formed, as shown in FIG. 5. Even if the dielectric layer 408 covering the gap 426 has a poor coverage effect, when the voids 414 shown in FIG. 6 are formed, the gaps 428 can be transmitted through. The dielectric layer 408 formed in the substrate is blocked so that the voids 414 formed in the gap 428 between two adjacent protruding regions 422 will not be conductive with each other. The result can be seen in the cross-sectional view of the VII-VII section of FIG. 4 (Fig. 7) After knowing that, a bit line contact window opening 410 is formed in the dielectric layer 408 between the protruding regions 422 (gap 428) by lithography and etching techniques to expose the active region 402. The surface of the substrate 400. The bit line contact window openings 410 will be in electrical communication with the voids 414 formed in the dielectric layer 408 of the gap 426, but the dielectric layer 408 formed between the recessed regions 424 (gap 428) and No-empty 8 This paper size is applicable to national standards < CNS) A4 specifications (2) x 297 mm) A7 B7 463308 6 3 2 8 twf. doc / 0 0 6 V. invention is described in (9) hole, so the two adjacent bit line contact hole 410 and through hole 414 is not turned on each other. Next, a conductive material 412 is inserted into the bit line contact window openings 4 and 0 to form a bit line contact window. In order to increase the step coverage capability of the conductive material 4, the preferred method for forming the conductive material 412 is, for example, chemical vapor deposition, and the material is, for example, polycrystalline silicon. Because the chemical vapor deposition method has a good step coverage ability when depositing the material layer, so when the conductor material 412 is deposited by the chemical vapor deposition method, the voids 414 that are in communication with the bit line contact window opening 410 are also The conductor material will be inserted and designated 416. Since the dielectric layer 408 formed by the gap 428 can be blocked, two adjacent bit line contact windows 412 'do not conduct to each other due to the conductive material 416 inserted in the hole 414 and cause a short circuit phenomenon. After that, a conductive layer is formed on the substrate 400, and a bit line connected to the bit line contact window 412 is formed through a lithography and etching process. In short, the above method is to reduce the width of a character line between two adjacent bit line contact windows when defining a character line pattern to increase the gap width between two adjacent character lines of the gap. In order to reduce its height-to-width ratio, the subsequent deposited dielectric layer will not have voids in this gap, so that the formed bit line contacting the window opening can be blocked by the dielectric layer without voids. Therefore, according to the above embodiments, the present invention has the following advantages: 1. The present invention can avoid voids in the dielectric layer of the bit line contact window. 2. The invention can avoid short circuit between the bit line contact windows. 3. The present invention can be avoided without reducing the degree of accumulation. The paper size is applicable to the Chinese @ 豕 standard (CNS) A4 specification (21〇X 297). (Please read the notes on the back before filling (This page) — II • Order-if —---- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 463308 6 3 2 e twf .doc / 0 0 6 A7 _ B7 V. Description of the invention (") Hole formation purpose. Although the present invention has been disclosed above with a dynamic random access memory having a trench capacitor as a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art will not depart from the spirit and scope of the present invention. Various modifications and retouching can be made, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. — ^ ---- „------ .--------- Order i .------- line (please read the notes on the back before filling this page) Ministry of Economy Printed by the Intellectual Property Bureau Staff Consumer Cooperatives Paper size applicable + National Standard (CNS) A4 (210x297 mm)