506042 A7 B7 五、發明說明（） 發明頜域 本發明是有關於一種半導體元件的製造方法，且特別 是有關於一種隨機存取記憶體（Random Dynamie Aeeess Memory ; DRAM)電容器的製造方法。 發明背景 當半導體進入深次微米（Deep Sub-Micron)的製程時， 元件的尺寸逐漸縮小，使整個積體電路的運作速度將因此 而能有效地提昇。對具有相同電路佈局之半導體元件而 言，整個電路之運作速度和其內部元件密度有關。在高元 件密度下，以DRAM而言，其電容器節點接點(node contact) 和位元線之間的空間勢必要縮小，因此如何做好此二者之 間的絕緣，也日益成爲一個棘手的問題。 第1圖是習知之隨機存取記憶體的結構剖面圖。請參 照第1圖，基底100中有元件隔離結構105，用以隔離出 主動區。基底100上有多個閘極110，在閘極110兩側之 基底100中有汲極115與源極120，組成了 DRAM記憶胞 之電晶體。絕緣層125覆蓋在基底100與閘極110上，絕 緣層I25之中有多個汲極插塞135與源極插塞H5分別位 於汲極開口 130與源極開口 140中。 在絕緣層150中有多個電容器開口 155位於汲極插塞 135之上，而電容器開口 155表面所覆蓋的即是下電極 160，下電極160表面覆蓋有薄薄一層之介電層（圖上未示 出），再其上則爲上電極165，組成DRAM記憶胞之電容 2 本紙張尺度適用+國國家標準（CNS)A4規格（210 X 297公釐） ' (請先閱讀背面之注音？事項再9本頁) 訂： -線· 經濟部智慧財產局員工消費合作社印製 506042 A7 ____B7 五、發明說明（） 器。所以電容器下電極160藉由汲極插塞135和電晶體之 汲極115電性導通。再往上是絕緣層17〇，位元線180依 序穿過絕緣層170與絕緣層15〇和源極插塞145相接，並 錯以和電晶體之源極12 0電性導通。 在第ί圖中，可以看到電容器的上電極165與位元線 180之間的距離a十分有限。首先在定義上電極165時， 因爲在微影時有所謂的對準誤差存在。而在後續定義位元 線開口 185時’又有一次微影時之對準誤差存在。因此無 法有效地將a値縮小，以免上電極165與位元線185之間 發生短路之問題。 發明目的與槪沭 因此本發明之一目的就是在提供一種電容器的製造方 法，以有效地增加上電極與位元線之間的距離，以避免短 路之問題。 本發明之另一目的就是在提供一種電容器的製造方 法，以自動對準方式來形成電容器的上電極，增加上電極 與位元線之製程裕度(process window)。 經濟部智慧財產局員工消費合作社印製 本發明之又一目的爲提供一種動態隨機存取記憶體的 製造方法，可有效地降低位元線與電容器之高深寬比値 (aspect ratio)並提高元件集積度。 根據上述目的，本發明提供一種電容器的製造方法包 括形成多個源極開口與汲極開口於覆蓋在電晶體上之第一 絕緣層中，以分別 ^暴露出電晶體之源極與汲極，然後 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 506042 A7 B7 五、發明說明（） 形成多個源極插塞與汲極插塞分別於源極開口與汲極開口 中。接著形成第二絕緣層於第一絕緣層、源極插塞與汲極 插塞上，再彤成多個電容器開口於第二絕緣層中，以分別 暴露出汲極插塞與其周圍之第一絕緣層的表面。然後形成 共形（conformal)之第一導電層於第二絕緣層上與電容器開 口中，再將預定位置上之第一導電層與位於其下之第二絕 緣層自上往下去除一部分。接著形成共形之電容器介電層 於第一導電層之表面上，再形成第二導電層於第二絕緣層 上並塡滿電容器開口。然後對第二導電層進行平坦化步驟 直至暴露出第二絕緣層之表面爲止。 根據上述目的，本發明提供一種動態隨機存取記憶體 的製造方法包括形成多個源極開口與汲極開口於覆蓋在電 晶體上之第一絕緣層中，以分別一一暴露出電晶體之源極 與汲極，然後形成多個源極插塞與汲極插塞分別於源極開 口與汲極開口中。接著形成第二絕緣層於第一絕緣層、源 極插塞與汲極插塞上，再形成多個電容器開口於第二絕緣 層中，以分別暴露出汲極插塞與其周圍之第一絕緣層的表 面。然後形成共形之第一導電層於第二絕緣層上與電容器 開口中，再將位於相鄰之電容器開口間且位於元件隔離結 構上之第一導電層與位於其下之第二絕緣層自上往下去除 一部分。接著形成共形之電容器介電層於第一導電層之表 面上，再形成第二導電層於第二絕緣層上並塡滿電容器開 口。然後對第二導電層進行平坦化步驟直至暴露出第二絕 緣層之表面爲止。接著形成第三絕緣層於第二導電層與第 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再本頁) · 線- 506042 A7506042 A7 B7 V. Description of the invention () Inventive jaw field The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a random access memory (Random Dynamie Aeeess Memory; DRAM) capacitor. BACKGROUND OF THE INVENTION When a semiconductor enters a deep sub-micron process, the size of the device is gradually reduced, so that the operation speed of the integrated circuit can be effectively improved as a result. For semiconductor components with the same circuit layout, the operating speed of the entire circuit is related to its internal component density. At high component densities, the space between the capacitor's node contact and the bit line must shrink in terms of DRAM. Therefore, how to make the insulation between the two becomes increasingly difficult. problem. FIG. 1 is a cross-sectional view showing a structure of a conventional random access memory. Referring to FIG. 1, a component isolation structure 105 is provided in the substrate 100 to isolate the active area. The substrate 100 has a plurality of gate electrodes 110. On the two sides of the gate electrode 110, there are a drain electrode 115 and a source electrode 120, which form a transistor of a DRAM memory cell. The insulating layer 125 covers the substrate 100 and the gate electrode 110. In the insulating layer I25, a plurality of drain plugs 135 and source plugs H5 are located in the drain opening 130 and the source opening 140, respectively. In the insulating layer 150, a plurality of capacitor openings 155 are located above the drain plug 135, and the surface of the capacitor opening 155 is covered with the lower electrode 160, and the surface of the lower electrode 160 is covered with a thin layer of dielectric layer (above) (Not shown), and then there is the upper electrode 165, which constitutes the capacitance of the DRAM memory cell. 2 This paper size is applicable to the + National Standard (CNS) A4 specification (210 X 297 mm). '(Please read the note on the back? Matters re-page 9) Order:-Line · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 506042 A7 ____B7 V. Description of the invention () device. Therefore, the capacitor lower electrode 160 is electrically conducted through the drain plug 135 and the drain 115 of the transistor. Further up is the insulating layer 170, and the bit line 180 sequentially passes through the insulating layer 170 and is connected to the insulating layer 150 and the source plug 145, and is electrically connected to the source 120 of the transistor. In the figure, it can be seen that the distance a between the upper electrode 165 of the capacitor and the bit line 180 is very limited. First, when defining the upper electrode 165, there is a so-called alignment error during lithography. In the subsequent definition of the bit line opening 185 ', there is another alignment error in the lithography. Therefore, it is impossible to effectively reduce a 免 to avoid the problem of short circuit between the upper electrode 165 and the bit line 185. OBJECTS AND PROBLEMS OF THE INVENTION Therefore, it is an object of the present invention to provide a method for manufacturing a capacitor to effectively increase the distance between the upper electrode and the bit line to avoid the problem of short circuits. Another object of the present invention is to provide a method for manufacturing a capacitor, which forms an upper electrode of the capacitor in an automatic alignment manner, and increases a process window of the upper electrode and a bit line. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Another object of the present invention is to provide a method for manufacturing a dynamic random access memory, which can effectively reduce the aspect ratio of bit lines and capacitors and improve components Accumulation degree. According to the above object, the present invention provides a method for manufacturing a capacitor, which includes forming a plurality of source openings and drain openings in a first insulating layer covering a transistor to expose the source and drain of the transistor, respectively. Then 3 paper sizes apply the Chinese National Standard (CNS) A4 (210 X 297 mm) printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy 506042 A7 B7 V. Description of the invention () Form multiple source plugs and drains The plugs are respectively in the source opening and the drain opening. Next, a second insulating layer is formed on the first insulating layer, the source plug and the drain plug, and then a plurality of capacitor openings are formed in the second insulating layer to expose the drain plug and the first surrounding it respectively. The surface of the insulation. Then, a conformal first conductive layer is formed on the second insulating layer and the opening of the capacitor, and then the first conductive layer at a predetermined position and the second insulating layer located thereunder are partially removed from the top down. Next, a conformal capacitor dielectric layer is formed on the surface of the first conductive layer, and then a second conductive layer is formed on the second insulating layer and fills the capacitor opening. The second conductive layer is then planarized until the surface of the second insulating layer is exposed. According to the above object, the present invention provides a method for manufacturing a dynamic random access memory, which includes forming a plurality of source openings and drain openings in a first insulating layer covering a transistor to expose the transistors one by one. The source and the drain are then formed into a plurality of source plugs and drain plugs in the source opening and the drain opening, respectively. Next, a second insulating layer is formed on the first insulating layer, the source plug and the drain plug, and a plurality of capacitor openings are formed in the second insulating layer to expose the drain plug and the first insulation around it, respectively. The surface of the layer. A conformal first conductive layer is then formed on the second insulating layer and in the capacitor opening, and then the first conductive layer located between adjacent capacitor openings and on the element isolation structure and the second insulating layer below it Remove part from top to bottom. Next, a conformal capacitor dielectric layer is formed on the surface of the first conductive layer, and then a second conductive layer is formed on the second insulating layer and fills the capacitor opening. The second conductive layer is then planarized until the surface of the second insulating layer is exposed. Then form a third insulation layer on the second conductive layer and the fourth paper. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before this page) · Wire-506042 A7
五、發明說明（） 二絕緣層之上’再形成複數個位元_口於第三絕緣層與 第二絕緣層中，以分別暴露出源極插塞之表面。接著形成 多個位元線分滕位元_□中與其咖之部分的第三絕 緣層上。 依照上述本發明所提供之方法可知本發明藉平坦化方 法，以_谷益開口位置爲上電極之實際位置，不需要再一 次微影步驟來定義上電極，因此可以使定義位元線開口之 製程裕度較爲寬鬆。或者可以進一步縮小原先預留給位元 線開口之面積，使元件集積度再往上提升。或者可以加大 電容器所佔據的面積，使電容器的電容增加，則可降低電 容器開口與位元線開口之深寬比値以提升製程良率。 圖式之簡單說明 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： (請先閱讀背面之注意事項再本頁) -裝 太 . 線 經濟部智慧財產局員工消費合作社印製 第1圖是習知之隨機存取記憶體的結構剖面圖。 第2A - 2 E圖是依照本發明一較佳實施例的一種動態 隨機存取記憶體之製造流程剖面圖。 圖式之標記說明 100、200 ··基底 105、205 :元件隔離結構 本紙張尺度適用中國國家標準（CNS)A4規格（210. X 297公釐） 506042 A7 B7_ 五、發明說明（） 110、210 :閘極 115、215 :汲極 120、220 :源極 125、150、170、225、250、280 :絕緣層 130、230 :汲極開口 140、240 :源極開口 135、235 :汲極插塞 145、245 :源極插塞 155、255 :電容器開口 160 :下電極 165、260a :上電極 180、290 :位元線 185、285 :位元線開口 260、270 :導電層 265 :光阻層 a、b :距離 發明之詳細說明 請參照第2A - 2 E圖，其繪示是依照本發明一較佳實 施例的一種動態隨機存取記憶體之製造流程剖面圖。 請參照第2A圖，基底200中有元件隔離結構205， 用以隔離出主動區。基底200上有多個閘極210，在閘極 210兩側之基底200中有汲極215與源極220,組成了 DRAM 記憶胞之電晶體。 6 本紙張尺度適用令國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再本頁) 訂·- --線· 經濟部智慧財產局員工消費合作社印製 506042V. Description of the invention () On the second insulating layer, a plurality of bit ports are formed in the third insulating layer and the second insulating layer to expose the surfaces of the source plugs, respectively. Next, a plurality of bit lines are formed on the third insulating layer of the bit__ and its part. According to the method provided by the present invention, it can be known that the present invention uses the planarization method as the actual position of the upper electrode, and does not need a lithography step to define the upper electrode. Therefore, the bit line opening can be defined. The process margin is relatively loose. Or you can further reduce the area that was originally reserved for the bit line openings, so that the component concentration can be further increased. Alternatively, the area occupied by the capacitor can be increased to increase the capacitance of the capacitor, and the aspect ratio of the opening of the capacitor to the opening of the bit line can be reduced to improve the process yield. Brief description of the drawings In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and in conjunction with the attached drawings, the detailed description is as follows: (Please read first Note on the back page again)-Installed too. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Online Economics. Figure 1 is a sectional view of the structure of a conventional random access memory. Figures 2A-2E are cross-sectional views of a manufacturing process of a dynamic random access memory according to a preferred embodiment of the present invention. Description of the drawing's marks 100, 200 ·· Base 105, 205: Component isolation structure The paper size is applicable to Chinese National Standard (CNS) A4 (210. X 297 mm) 506042 A7 B7_ V. Description of the invention () 110, 210 : Gate 115, 215: Drain 120, 220: Source 125, 150, 170, 225, 250, 280: Insulating layer 130, 230: Drain opening 140, 240: Source opening 135, 235: Drain plug Plugs 145, 245: Source plugs 155, 255: Capacitor openings 160: Lower electrodes 165, 260a: Upper electrodes 180, 290: Bit line 185, 285: Bit line openings 260, 270: Conductive layer 265: Photoresist Layers a and b: For a detailed description of the distance invention, please refer to FIGS. 2A-2E, which are cross-sectional views showing a manufacturing process of a dynamic random access memory according to a preferred embodiment of the present invention. Referring to FIG. 2A, a component isolation structure 205 is provided in the substrate 200 to isolate the active area. There are a plurality of gates 210 on the substrate 200. A drain 215 and a source 220 are formed in the substrate 200 on both sides of the gate 210 to form a transistor of a DRAM memory cell. 6 This paper size applies the national standard (CNS) A4 specification (210 X 297 mm) (please read the precautions on the back before this page). 506042
A7 B7 Γ 五、發明說明（） 在基底200與閘極21〇上形成絕緣層225，再於絕緣 層225之中形成多個有多個汲極開口 230與源極開口 240。 接著分別於汲極開口 230與源極開口 240中形成汲極插塞 235與源極插塞245。 其中絕緣層225之材料例如可爲氧化矽或其他合適的 絕緣材料’其形成法例如可爲化學氣相沈積法。汲極開口 230與源極開□ 240的形成方法例如可爲微影蝕刻法。而 汲極插塞235與源極插塞245的形成方法例如可爲化學氣 相沈積法’而其材料例如可爲金屬鎢或其他合適的導電材 料。 * 接著在汲極插塞235、源極插塞245與絕緣層225之 上形成絕緣層250，再於其中形成電容器開口 255暴露出 汲極插塞235的表面，並暴露出汲極插塞235周圍之絕緣 層225的表面。在絕緣層250與電容器開口 255之表面上 形成共形之導電層260，再於導電層260上形成一層光阻 層265，將所有之電容器開口 255塡滿。 其中絕緣層25G之材料例如可爲氧化矽或其他合適的 絕緣材料，其形成法例如可爲化學氣相沈積法。電容器開 口 255的形成方法例如可爲微影触刻法。導電層26()之材 質例如可爲摻雜多晶砍並於其上生長出半球形砍晶粒 (Hemi-Sphere Silicon ; HSG)或是其他合適的導電材料，而 其形成方法例如可爲化學氣相沈積法。至於光阻層265的 形成方法例如可爲旋塗法。 請參照第2B圖，對光阻層265進行微影步驟，暴露 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝—丨A7 B7 Γ 5. Description of the invention () An insulating layer 225 is formed on the substrate 200 and the gate electrode 210, and a plurality of drain openings 230 and source openings 240 are formed in the insulating layer 225. Then, a drain plug 235 and a source plug 245 are formed in the drain opening 230 and the source opening 240, respectively. The material of the insulating layer 225 may be, for example, silicon oxide or other suitable insulating materials, and the formation method thereof may be, for example, a chemical vapor deposition method. The method of forming the drain opening 230 and the source opening 240 may be, for example, a lithography method. The formation method of the drain plug 235 and the source plug 245 may be, for example, a chemical vapor deposition method, and the material thereof may be metal tungsten or other suitable conductive materials. * Next, an insulating layer 250 is formed on the drain plug 235, the source plug 245, and the insulating layer 225, and a capacitor opening 255 is formed therein to expose the surface of the drain plug 235 and expose the drain plug 235 The surface of the surrounding insulating layer 225. A conformal conductive layer 260 is formed on the surfaces of the insulating layer 250 and the capacitor opening 255, and a photoresist layer 265 is formed on the conductive layer 260 to fill all the capacitor openings 255. The material of the insulating layer 25G may be, for example, silicon oxide or other suitable insulating materials, and the formation method thereof may be, for example, a chemical vapor deposition method. The method of forming the capacitor opening 255 may be, for example, a lithography method. The material of the conductive layer 26 () may be, for example, doped polycrystalline choppers and hemi-sphere silicon (HSG) grains or other suitable conductive materials are grown thereon, and the formation method thereof may be, for example, chemical Vapor deposition. The method of forming the photoresist layer 265 may be, for example, a spin coating method. Please refer to Figure 2B for the lithography step of the photoresist layer 265 to expose 7 paper sizes that comply with the Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) Equipment— 丨
訂------II 經濟部智慧財產局員工消費合作社印製 506042 Α7 Β7 經濟部智慧財產局員工消費合作社印製 五、發明說明（） 出部分之相鄰電容器開口 255間之導電層260的上端部 分。 請參照第2C圖，去除暴露出之導電層260與其下之 絕緣層250，再將殘餘之光阻層265去除之，然後在殘餘 之導電層260的表面上形成介電層（圖上未示出)做爲電容 器介電層。導電層260與絕緣層250的去除方法例如可爲 乾蝕刻法，例如反應離子蝕刻法（Reactive I〇n Etching ; RIE)，以控制蝕刻時間來控制導電層260與絕緣層255預 備蝕刻掉之厚度。殘餘光阻層265之去除方法例如可爲電 漿灰化法，再以淸潔液淸潔之。而電容器介電層的材質例 如可爲氧化矽/氮化矽/氧化矽（ΟΝΟ)複層，或其他適合的 材料。 請參照第2D圖，接著形成導電層270覆蓋整個基底 200之表面，並塡滿電容器開口 255。然後對導電層270 進行平坦化步驟，直至暴露出絕緣層250之表面爲止，如 此形成電容器的上電極270。此平坦化步驟例如可使用化 學機械硏磨法。 請參照第2Ε圖，接著形成絕緣層280覆蓋於整個基 底200上，再於絕緣層280與250中形成位元線開口 285， 以暴露出汲極插塞245之表面。接著於位元線開口 285中 與其周圍之部分的絕緣層280上形成位元線290。其中絕 緣層280之材料例如可爲氧化矽或其他合適的絕緣材料， 其形成法例如可爲化學氣相沈積法。位元線開口 285的形 成方法例如可爲微影蝕刻法。而位元線290的材質例如可 8 (請先閱讀背面之注音？事項再 •裝i — 11^本頁) 訂： --線· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 506042 A7 五、發明說明（） 爲摻雜多晶矽、金屬鎢或其他合適的導電材料，g形 法例如可爲化學氣相沈積法。 、y 由第1圖與第2E圖之比較可知在第i圖中之位元線 與上電極間之距離a比第2E圖中之位元線與上電極間之 距離b要小得多。因此利用本發明所提供之方法可以使定 義電容器上電極與位元線之製程裕度加大。也就是本發明 所提供之方法藉由平坦化步驟，以電容器開口位置爲上電 極之實際位置，因此不需要再一次微影步驟來定義上電極 的位置。如此不僅可以使得定義位元線開口之製程裕度較 爲寬鬆，還甚至可以進一步縮小原先預留給位元線開口之 面積，使元件集積度再往上提升。或者可以加大電容器所 佔據的面積，使電容器的電容增加，如此在電容器儲存相 同電容量的情況下，電容器的高度可以再降低，則可降低 電容器開口與位元線開口之深寬比値以提升製程良率。 由上述本發明較佳實施例可知，應用本發明具有下述 之優點。 一、 提高電容器與位元線之製程裕度。 二、 提升半導體元件密度。 三、 降低電容器開口與位元線開口之深寬比値。 四、 提升產品之良率。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） I n H 1 n n K n n n n n n I * n n (請先閱讀背面之注意事項再本頁) - •線- 經濟部智慧財產局員工消費合作社印製Order ------ II Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 506042 Α7 Β7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () Conductive layer 260 between the adjacent 255 capacitor openings The upper part. Referring to FIG. 2C, the exposed conductive layer 260 and the underlying insulating layer 250 are removed, and the remaining photoresist layer 265 is removed, and then a dielectric layer is formed on the surface of the remaining conductive layer 260 (not shown in the figure) (Out) as the capacitor dielectric layer. The method for removing the conductive layer 260 and the insulating layer 250 may be, for example, a dry etching method, such as a reactive ion etching method (Reactive Ion Etching; RIE). The thickness of the conductive layer 260 and the insulating layer 255 to be etched away is controlled by controlling the etching time. . The method for removing the residual photoresist layer 265 may be, for example, a plasma ashing method, and then cleaning it with a cleaning solution. The material of the capacitor dielectric layer may be, for example, a silicon oxide / silicon nitride / silicon oxide (ONO) layer, or other suitable materials. Referring to FIG. 2D, a conductive layer 270 is formed to cover the entire surface of the substrate 200 and fill the capacitor opening 255. The conductive layer 270 is then planarized until the surface of the insulating layer 250 is exposed, and the upper electrode 270 of the capacitor is thus formed. This planarization step can use, for example, a chemical mechanical honing method. Referring to FIG. 2E, an insulating layer 280 is formed to cover the entire substrate 200, and bit line openings 285 are formed in the insulating layers 280 and 250 to expose the surface of the drain plug 245. Next, a bit line 290 is formed on the insulating layer 280 of the bit line opening 285 and a portion around the bit line opening 285. The material of the insulating layer 280 may be, for example, silicon oxide or other suitable insulating materials, and the formation method thereof may be, for example, a chemical vapor deposition method. The bit line opening 285 can be formed by, for example, a lithography method. The material of bit line 290 can be 8, for example (please read the note on the back? Matters and then install i — 11 ^ this page). Order:-Line · This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 public love) 506042 A7 5. Description of the invention () is doped polycrystalline silicon, metal tungsten or other suitable conductive materials, the g-shaped method can be, for example, a chemical vapor deposition method. , Y From the comparison between Fig. 1 and Fig. 2E, it can be seen that the distance a between the bit line in Fig. I and the upper electrode is much smaller than the distance b between the bit line in Fig. 2E and the upper electrode. Therefore, the method provided by the present invention can increase the process margin for defining the upper electrode of the capacitor and the bit line. That is, the method provided by the present invention uses the planarization step to take the capacitor opening position as the actual position of the upper electrode, so there is no need for another lithography step to define the position of the upper electrode. In this way, not only the process margin for defining the bit line openings can be loosened, but also the area originally reserved for the bit line openings can be further reduced, so that the component concentration can be further increased. Or you can increase the area occupied by the capacitor, so that the capacitance of the capacitor increases. In this way, if the capacitor stores the same capacitance, the height of the capacitor can be lowered, which can reduce the aspect ratio of the capacitor opening to the bit line opening. Improve process yield. As can be seen from the foregoing preferred embodiments of the present invention, the application of the present invention has the following advantages. 1. Improve the process margin of capacitors and bit lines. 2. Increase the density of semiconductor components. 3. Reduce the aspect ratio of the capacitor opening to the bit line opening. Fourth, improve product yield. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. 9 This paper size applies to China National Standard (CNS) A4 (210 X 297 public love) I n H 1 nn K nnnnnn I * nn (Please read the notes on the back before this page)-• Line-Intellectual Property of the Ministry of Economic Affairs Printed by Bureau Consumers Cooperative