A7 B7 4 7 8 4 twf,doc/008 五、發明說明（/ ) 本發明是有關於一種積體電路的製造方法，且特別是 有關於一種埋入式接觸窗(Buried Contact)之製造方法。 隨著積體電路積集度的增加，使得複晶砂層與單晶砂 基底之間的接觸，已由習知的金屬連線方式演進至埋入式 接觸窗（Buried Contact)。然而習知埋入式接觸窗的製造 方法在製程上面臨一些困境，以下係以習知之製造流程進 行說明。 第1A圖至第1D圖是繪示習知一種埋入式接觸窗之半 導體元件的製造流程剖面圖。請參照第1A圖，習知埋入 式接觸窗的製作係在已完成隔離區102製作的基底1 〇〇上 先形成一層氧化層1〇4與一層複晶砂層106，然後在複晶 砂層1〇6上形成一層光阻層108，並將複晶砂層104與氧 化層106圖案化。然後，進行離子佈植製程109以在基底 100之中形成埋窗110。 之後，請參照第1B圖’去除光阻層1〇8，然後，在基 底100上再形成第二層複晶矽層112。接著在複晶矽層112 上形成另一層光阻層114’以定義閘極與埋入式接觸窗之 局部內連線之區域。 然後’請參照第1C圖，進行蝕刻製程，蝕刻去除未被 光阻層II4所覆蓋的複晶矽層I〗2、複晶矽層106，以形 成閘極之導體層116與局部內連線118。其後再進行離子 植入製程120’以於基底100中形成輕摻雜源極/汲極區 122 ° 接著’請參照第1D圖’在閘極導體層116與局部內連 線118的側壁分別形成間隙壁124、間隙壁126，然後在 3 (請先閱讀背面之注意事項再填寫本頁) 裝！—訂i — ιί — ·^、 經濟部智慧財彦局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 416124 A7 4784twf.doc/008 __B7_____ 五、發明說明（>) 進離子植入製程，以在基底100之中形成重摻雜源極/ 汲極區130,以完成具有輕摻雜極極結構之源極/汲極區 132 ° 上述之習之方法係透過埋窗110使源極/汲極區132與 局部內連線118電性連接。但是，請參照第1B圖與第1C 圖，在形成閘極導體層Π6與局部內連線118的圖案化過 程中，必須準確對準，亦即是所形成之光阻層114的一側 邊134必須對準埋窗110的邊緣136，否則一但發生對準 錯誤(Misalignment)，將導致埋窗110與源極/汲極區132 無法電性連接的情形。第2A圖至第2B圖與第3A圖至第 3B圖係繪示在形成閘極導體層116與局部內連線118的過 程中發生錯誤對準的兩種情形，其中第2A圖至第2B圖係 對準時發生正向誤差之後，所形成之半導體元件的剖面示 意圖；第3A圖至第3B圖係繪示對準時發生負向誤差之 後，所形成之半導體元件的剖面示意圖。 請參照第2A圖，在形成閘極導體層116與局部內連線 118的過程中，發生正向對準誤差時，將使得位於埋窗110 上方的部分複晶矽層112因爲無法被光阻層114a所覆蓋而 裸露出來。由於位於埋窗110上方的複晶矽層112，係直 接覆蓋於基底100之上，其與基底100之間並不具有氧化 層104。因此，在後續的電漿蝕刻程序中，位於埋窗110 上方的複晶矽層112並無法像其他之處的複晶矽層112與 複晶矽層106，可以以氧化層104作爲蝕刻的終止層，所 以，埋窗110之處的基底100表面易遭受蝕刻的破壞，而 形成溝痕140。當溝痕140的深度過深，將會使得後續形 4 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公发） I--------I — ^ *---If--* 竣 (請先閱讀背面之注意事項再填寫本頁) A7 B7 416124 4784twf.doc/008 五、發明說明（多） 成之源極/汲極區132無法與埋窗110電性連接，而失去埋 入式接觸窗之功效，如第2B圖所示。 請參照第3A圖，當形成閘極導體層116與局部內連線 118的過程中，發生負向對準誤差時，將會使得所形成之 光阻層1Mb將埋窗區110完全覆蓋，並且會使光阻層U4b 延伸至埋窗110之外。在後續的蝕刻製程之後，所形成之 局部內連線11S除了會覆蓋埋窗110之外，還會延伸至埋 窗110的邊緣136之外。而延伸至埋窗110其邊緣136之 外的複晶矽層II2與複晶矽層106將會作爲後續形成輕摻 雜源極/汲極區122的離子罩幕層，而使最終形成的源極/ 汲極區132無法與埋窗110電性連接，而使元件失去埋入 式接觸窗之功效，如第3B圖所示。 本發明提出一種埋入式接觸窗的製造方法，此方法之 簡述如下：提供一基底，此基底的表面上已形成一層氧化 層與第一層導體層，且在第一層導體層、氧化層與基底之 中已形成一隔離區，接著，在基底上形成一層圖案化的光 阻罩幕層，此光阻罩幕層具有一開口，裸露出部分的隔離 區與部分的第一層導體層，之後，去除開口所裸露的部分 隔離區，以在隔離區中形成一凹槽，然後，以上述之罩幕 層爲植入罩幕，進行離子植入步驟，以在基底之中形成一 埋窗。其後將光阻罩幕層去除，並於基底上形成第二層導 體層，以塡滿凹槽。之後，再將第二層導體層與第一層導 體層圖案化，以形成與埋窗電性連接的局部內連線與閘極 之導體層。 本發明提出一種半導體元件的製造方法，此方法之簡 5 度適用中國國家標準（CNS)A4規格（210 X 297公釐） I l· I I l·---.--- ---I I! — 訂 I I I ! -峻 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 416124 4784twf,doc/008 A7 B7 五、發明說明（β) 述如下：提供一基底，在基底的表面上形成氧化層、第一 層導體層與氮化矽罩幕層，接著，將氧化層、第一層導體 層與氮化矽罩幕層圖案化，並在基底中形成一溝渠，然 後，在基底上形成一層絕緣層，並以化學機械硏磨法將溝 渠以外的絕緣層去除，以在溝渠中形成一隔離區。之後， 將氮化矽罩幕層去除，並在基底上形成一層圖案化的光阻 罩幕層，此罩幕層具有一開口，裸露出部分的隔離區與部 分的第一層導體層，之後，去除開口所裸露的部分隔離 區，以在隔離區中形成一凹槽，然後，以上述之光阻罩幕 層爲植入罩幕，進行離子植入步驟，以在基底之中形成一 埋窗。其後將光阻罩幕層去除，並於基底上形成第二層導 體層，以塡滿凹槽。之後，再將第二層導體層與第一層導 體層圖案化，以形成與埋窗電性連接之局部內連線與閘極 之導體層。 依照本發明實施例所述，上述將第二層導體層與第一 層導體層圖案化，以形成局部內連線與閘極導體層的步驟 係一光阻罩幕層覆蓋預定形成局部內連線與閘極之區 域，然後再經由蝕刻製程以形成之。其中，所覆蓋之預定 形成局部內連線區域，係至少覆蓋部分的埋窗，也就是 說，用以定義局部內連線區域之光阻罩幕層其邊緣僅需位 於埋窗的範圍之內，均是可以形成本發明之埋入式接觸 窗。由於本發明所容許的製程誤差範圍遠大於儀器發生對 準失誤的誤差範圍，因此本發明之製程的預度（Process Window)很寬，可以減少製程的困難度，增加製程的產能 (Throughput) ° -Γ . (請先閱讀背面之注意事項再填寫本頁) 裝-------—訂—I---— ϊ·^ 經濟部智慧財產局員工消費合作社印S取 本紙張尺度適用中國國家標準（CNS)A4規格（210 * 297公茇） 416124 A7 4784twf.doc/008 ___B7___ 五、發明說明（k) 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 圖式之簡單說明： 第1A圖至第1D圖是繪不習知一種埋入式接觸窗之半 導體元件的製造流程剖面圖； 第2A圖至第2B圖係繪示第1A圖中在形成閘極導體 層與局部內連線的過程中，發生正向對準誤差時，其半導 體元件的製造流程剖面圖； 第3A圖至第3B圖係繪示第1A圖中在形成閘極導體 層與局部內連線的過程中，發生負向對準誤差時’其半導 體元件的製造流程剖面圖；以及 第4A圖至第41圖繪示本發明之實施例，一種埋入式 接觸窗之半導體元件之製造方法的流程剖面圖。 圖式標記說明： 100 ' 200 基底 102 隔離區 104、202 氧化層 106 ' 112 複晶矽層 108' 114' 114a' 114b 光阻層 109、 120、128、216 離子植入製程 110、 218 埋窗 116 閘極導體層 118 局部內連線 122、242 輕摻雜源極/汲極區 7 本紙張尺度適用中國國家標準（CNS)A‘l規格（2〗0 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) — 11 ί I 訂· -------埃 經濟部智慧財產局具工消費合作社印製 經濟部智慧財產局員工消費合作社印製 416124 A7 4784twf,doc/008 _B7_ 五、發明說明（ί ) 124 ' 126 ' 244 ' 246 間隙壁 130、250重摻雜源極/汲極區 132 > 252 輕摻雜極汲結構之源極/汲極區 134 光阻之邊緣 136 埋窗之邊緣 204、204a、204b、222、222a、222b 導體層 206、212、226 罩幕層 208 溝渠 210 絕緣層 214 開口 220 凹槽 224 摻雜區 228 預定閘極區 230 預定局部內連線區 232 區域範圍 234 罩幕層之邊緣 236 閘極導體層 23 8 局部內連線 240 輕摻雜離子植入製程 248 重摻雜離子植入製程 實施例一 第4A圖至第41圖繪示本發明之實施例，一種埋入式 接觸窗之半導體元件之製造方法的流程剖面圖。 首先請參照第4D圖，本發明之埋入式接觸窗的製造係 先提供已形成氧化層202與導體層204以及隔離區210之 ---------1---^ii----1 訂---------歧 (請先閱讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標準（CNS)A4規格（210x297公釐） 416124 4 7 8 4 twf, doc/008 A7 B7 經濟部智慧財產局員工消費合作社印*'衣 五、發明說明（)） 基底200。形成如第4D圖之結構的方法可以經由第4A圖 至第4D圖之方法以達成之。但是’此方法並非用以限定 本發明。 請參照第4A圖，首先，提供一基底200，例如，具有 輕摻雜的P型井區或P型半導體，並於基底200上依序形 成氧化層202、導體層204與罩幕層2〇6。氧化層2〇2的 形成方法包括熱氧化法，例如是在溫度約爲800°C〜1〇〇〇。(： 的氧氣環境下，於基底200上生成一厚度約爲30埃〜200 埃的氧化層。導體層2〇4之材質例如爲摻雜複晶矽或金 屬’例如是鋁 '銅或鎢，形成的方法例如是化學氣相沉積 法’厚度約爲500埃至2500埃。罩幕層206之材質係與 後續用以形成隔離區之材質具有不同蝕刻率者，其材質例 如爲氮化矽，形成的方法例如爲化學氣相沉積法。 接著，請參照第4B圖，以微影成像技術與蝕刻程序將 罩幕層206、導體層204與氧化層202圖案化，並在基底 200之中形成溝渠208。然後，在基底200上形成一層絕 緣層210，以塡滿溝渠2〇8。絕綠層210之材質例如爲氧 化矽’其形成的方法例如是以四乙氧基矽烷(TEOS)爲氣體 源之化學氣相沉積法，較佳的方法係在形成氧化層之後， 更進一步進行氧化層之密實化。 然後’請參照第4C圖，將溝渠2〇8以外的絕緣層210 去除’以使留在溝渠2〇8之中的絕緣層210形成隔離區’ 較佳的去除方法例如是以罩幕層206爲硏磨終止層，利用 化學機械硏磨技術將罩幕層206其上表面上所覆蓋的絕緣 層210硏磨去除。 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I---^--I I I I I , — I! I I 訂，i ! 1 I _峻 (請先閱讀背面之注意事項再填寫本頁) A7 A7 經濟部智慧財產局員工消費合作社印製 wf.doc/008 五、發明說明（汉） 之後，請參照第4D圖’去除罩幕層206 ’以裸露出導 體層204之上表面。罩幕層206的去除方法例如爲濕式蝕 刻法。 接著，請參照第4E圖，在基底200上形成一層罩幕層 212，此罩幕層212之材質例如爲光阻，其具有一開口 214 裸露出部分的導體層204與絕緣層210的表面。其後，以 罩幕層212爲植入罩幕，進行離子植入製程216，以在對 應於開口 214之氧化層202下方形成一埋窗218。 接著，請參照第4F圖，去除開口 214所裸露的部分絕 緣層210，以形成裸露出導體層2〇4之側壁與部分的埋窗 218的凹槽220。去除的方法例如是以罩幕層210爲鈾刻 罩幕，利用乾式蝕刻製程以去除開口 214所裸露之部分絕 緣層210。 其後，請參照第4G圖，去除罩幕層212。然後，在導 體層204與絕緣層21〇的表面上形成另一層導體層222。 導體層222之材質例如爲摻雜複晶矽、金屬矽化物或金屬 形成的方法例如爲化學氣相沉積法，其較佳的厚度係足以 將凹槽220塡滿者，例如是500埃至2500埃左右。當導 體層222之材質爲摻雜複晶矽時，後續的熱製程將會使複 晶矽層中的摻雜擴散至基底200之中，而形成一摻雜區 224。此摻雜區224可視爲埋入式接觸窗的埋窗之一。當 導體層222塡入凹槽2：20之後，導體層222將與第一層導 體層204以及埋窗218電性耦接。 接著，請繼續參照第4G圖，在導體層222上形成一層 罩幕層226，此罩幕層226之材質例如爲光阻，係覆蓋預 本紙張尺度滷用中0®家標準（CNS)A4規格（210x 297公釐） t--------訂---------線 (請先閱讀背面之注音？事項再填寫本頁) A7 B7 416124 4784twf.doc/008 五、發明說明（γ ) <請先閲讀背面之注意事項再填寫本頁) 定形成闊極之區域228與局部內連線之處230。其中，罩 幕層226所覆蓋之預定形成局部內連線區域230，係至少 覆蓋部分的埋窗218，也就是說，用以定義局部內連線區 域230之罩幕層226其邊緣234僅需位於圖式中標記232 所示之範圍之中，均是可以彤成本發明之埋入式接觸窗。 較佳的係使罩幕層226之邊緣234位於範圍232的中心線 左右。由於標記234所涵蓋的範圍可以表示此製程的誤差 範圍，而此範圍又大於儀器發生對準失誤的誤差範圍，因 此本發明之製程的預度（Process Window)很寬，可以減少 製程的困難度，增加製程的產能（Throughput)。 之後，請參照第4H圖，去除罩幕層226所裸露之導體 層222與導體層204，以使留下之導體層222a與導體層 2〇4a形成閘極之閘極導體層236;留下之導體層222b與導 體層204b形成埋入式接觸窗之局部內連線238。去除的方 法例如是以罩幕層226爲蝕刻罩幕，進行非等向性蝕刻製 程以達成之。然後，將罩幕層226去除，再以閘極導體層 236與局部內連線238爲植入罩幕，進行輕摻雜離子植入 製程240，以在基底200中形成輕摻雜源極/汲極區242。 經濟部智慧財產局員工消費合作社印製 然後，請參照第圖，在閘極導體層236與局部內連 線238的側壁分別形成間隙壁244與間隙壁246。間隙壁 244、間隙壁246之材質例如爲氮化矽，其形成的方法例 如是以化學氣相沉積法在基底200上形成一層氮化矽層， 然後再經由回蝕刻製程’以形成間隙壁244與間隙壁246。 其後，再以閘極導體層236、局部內連線238、間隙壁M4 與間隙壁246爲植入罩幕，進行重摻雜離子植入步驟248， 本紙張尺度適用中國國家標準（CNS>A4規格<210 ^ 經濟部智慧財產局員工消費合作社印製 416124 4 7 8 4 twf. doc /〇 Ο 8 ^ ________B7_ 五、發明說明（（。） 以在基底200中形成重摻雜源極/汲極區250，以完成具有 輕摻雜汲極結構之源極/汲極區252之製作。 本發明之方法在形成閘極導體層236以及局部內連線 238的過程中，不論儀器是發生正向錯誤對準或負向錯誤 對準’由於製程的預度很寬，因此，所形成之局部內連線 238均可以座落於標記232所涵蓋的範圍之中，使其可以 透過埋窗218而與源極汲極區252電性耦接，使埋入式接 觸窗發揮其功能，而不會有習知方法中因爲正向錯誤對準 致使溝痕產生，或是負向錯誤對準致使埋窗與源極/汲極區 無法電性耦接的問題。 上述之方法所形成之局部內連線均可用以電性連接閘 極與源極/汲極區。故而，本發明可以應用於邏輯電路 (Logic Circuit)以及靜態隨機存取記憶體（Static Random Access Memory，中。 綜合以上所述，至少具有下列優點： 1. 本發明的製程艮寬，可以減少製程的困難度， 增加製程的產自\|4 2. 本發明之方法可方止習知對準誤差造成溝痕形 成以及埋窗與源極/汲極區電性無法耦接的問題。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 ----^----„----^--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國®家標準（CNS)AO見格（2]〇χ 297公釐）A7 B7 4 7 8 4 twf, doc / 008 5. Description of the Invention (/) The present invention relates to a method for manufacturing an integrated circuit, and more particularly to a method for manufacturing a buried contact window (Buried Contact). With the increase of the integration degree of the integrated circuit, the contact between the polycrystalline sand layer and the single crystal sand substrate has evolved from the conventional metal connection method to the buried contact window (Buried Contact). However, the manufacturing method of the conventional embedded contact window faces some difficulties in the manufacturing process. The following is a description of the conventional manufacturing process. FIGS. 1A to 1D are cross-sectional views illustrating a manufacturing process of a conventional semiconductor device of a buried contact window. Please refer to FIG. 1A. It is known that the fabrication of the buried contact window is to form an oxide layer 104 and a polycrystalline sand layer 106 on the substrate 100 which has completed the isolation zone 102. Then, the polycrystalline sand layer 1 is formed. A photoresist layer 108 is formed on 〇6, and the polycrystalline sand layer 104 and the oxide layer 106 are patterned. Then, an ion implantation process 109 is performed to form a buried window 110 in the substrate 100. After that, referring to FIG. 1B, the photoresist layer 108 is removed, and then a second polycrystalline silicon layer 112 is formed on the substrate 100. Next, another layer of photoresist layer 114 'is formed on the polycrystalline silicon layer 112 to define a region of local interconnections between the gate electrode and the buried contact window. Then, please refer to FIG. 1C, perform an etching process, and remove the polycrystalline silicon layer I that is not covered by the photoresist layer II4. The polycrystalline silicon layer 106 is formed to form a gate conductor layer 116 and local interconnects. 118. Thereafter, an ion implantation process 120 'is performed to form a lightly doped source / drain region 122 in the substrate 100. Then,' Please refer to FIG. 1D ', on the sidewalls of the gate conductor layer 116 and the local interconnects 118, respectively. Form gap wall 124, gap wall 126, and install in 3 (Please read the precautions on the back before filling in this page)! —Order i — ιί — · ^, Printed on the paper printed by the Employees ’Cooperatives of the Wisdom Finance and Economics Bureau of the Ministry of Economic Affairs Printed on a paper of China National Standard (CNS) A4 (210 X 297 mm) Printed by the Staffs’ Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 416124 A7 4784twf.doc / 008 __B7_____ 5. Description of the Invention (>) An ion implantation process is performed to form a heavily doped source / drain region 130 in the substrate 100 to complete a source with a lightly doped pole structure / Drain region 132 ° The above-mentioned method is to electrically connect the source / drain region 132 to the local interconnection 118 through the buried window 110. However, please refer to FIG. 1B and FIG. 1C. During the patterning process of forming the gate conductor layer Π6 and the local interconnects 118, it must be accurately aligned, that is, one side of the photoresist layer 114 formed. 134 must be aligned with the edge 136 of the buried window 110; otherwise, if an alignment error occurs, the buried window 110 and the source / drain region 132 cannot be electrically connected. Figures 2A to 2B and Figures 3A to 3B show two situations in which misalignment occurs during the formation of the gate conductor layer 116 and the local interconnects 118, of which Figures 2A to 2B FIG. 3 is a schematic cross-sectional view of a formed semiconductor element after a positive error occurs during alignment; FIGS. 3A to 3B are schematic cross-sectional views of a formed semiconductor element after a negative error occurs during alignment. Please refer to FIG. 2A. In the process of forming the gate conductor layer 116 and the local interconnects 118, when a forward alignment error occurs, a part of the polycrystalline silicon layer 112 located above the buried window 110 cannot be blocked by photoresist. The layer 114a is covered and exposed. Since the polycrystalline silicon layer 112 above the buried window 110 is directly covered on the substrate 100, there is no oxide layer 104 between the substrate 100 and the substrate 100. Therefore, in the subsequent plasma etching process, the polycrystalline silicon layer 112 above the buried window 110 is not like the polycrystalline silicon layer 112 and the polycrystalline silicon layer 106 elsewhere. The oxide layer 104 can be used as the termination of the etching. As a result, the surface of the substrate 100 where the window 110 is buried is susceptible to damage by etching, so that groove marks 140 are formed. When the depth of the groove marks 140 is too deep, it will make the subsequent paper size 4 conform to the Chinese National Standard (CNS) A4 specification (210x297). I -------- I — ^ * --- If- -* End (please read the precautions on the back before filling this page) A7 B7 416124 4784twf.doc / 008 V. Description of the invention (multiple) The source / drain region 132 of Cheng cannot be electrically connected to the buried window 110, and The effect of the embedded contact window is lost, as shown in Figure 2B. Please refer to FIG. 3A. When a negative alignment error occurs during the formation of the gate conductor layer 116 and the local interconnect lines 118, the formed photoresist layer 1Mb will completely cover the buried window area 110, and The photoresist layer U4b may extend beyond the buried window 110. After the subsequent etching process, the formed local interconnects 11S will extend beyond the edge 136 of the buried window 110 in addition to covering the buried window 110. The polycrystalline silicon layer II2 and the polycrystalline silicon layer 106 extending beyond the edge 136 of the buried window 110 will serve as an ion mask layer for the subsequent formation of a lightly doped source / drain region 122, so that the final source is formed. The electrode / drain region 132 cannot be electrically connected to the buried window 110, and the device loses the effect of the buried contact window, as shown in FIG. 3B. The present invention provides a method for manufacturing a buried contact window. The method is briefly described as follows: A substrate is provided, and an oxide layer and a first conductor layer have been formed on the surface of the substrate. An isolation region has been formed between the layer and the substrate. Then, a patterned photoresist mask curtain layer is formed on the substrate. The photoresist mask curtain layer has an opening, exposing part of the isolation region and part of the first layer of conductor. Layer, and then remove a part of the isolation area exposed by the opening to form a groove in the isolation area. Then, using the mask layer described above as the implant mask, an ion implantation step is performed to form a substrate in the substrate. Buried window. Thereafter, the photoresist mask curtain layer is removed, and a second conductive layer is formed on the substrate to fill the groove. After that, the second conductive layer and the first conductive layer are patterned to form a local interconnect and a conductive layer of the gate which are electrically connected to the buried window. The present invention proposes a method for manufacturing a semiconductor device. The simple 5 degree of this method is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) I l · II l · ---.--- --- II! — Order III!-Jun (please read the notes on the back before filling this page) Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 416124 4784twf, doc / 008 A7 B7 5. Description of the invention (β) is as follows: Provide a basis , Forming an oxide layer, a first conductor layer, and a silicon nitride mask layer on the surface of the substrate, and then patterning the oxide layer, the first conductor layer, and the silicon nitride mask layer, and forming a layer in the substrate The trench is then formed with an insulating layer on the substrate, and the insulating layer outside the trench is removed by chemical mechanical honing to form an isolation region in the trench. After that, the silicon nitride masking layer is removed, and a patterned photoresist masking layer is formed on the substrate. The masking layer has an opening, exposing a part of the isolation region and a part of the first conductive layer. , Removing a part of the isolation area exposed by the opening to form a groove in the isolation area, and then using the photoresist mask layer as the implant mask to perform an ion implantation step to form a buried layer in the substrate window. Thereafter, the photoresist mask curtain layer is removed, and a second conductive layer is formed on the substrate to fill the groove. After that, the second conductive layer and the first conductive layer are patterned to form a local interconnect and a gate conductive layer which are electrically connected to the buried window. According to the embodiment of the present invention, the above-mentioned step of patterning the second conductive layer and the first conductive layer to form a local interconnect and a gate conductor layer is a photoresist mask curtain layer covering a predetermined local interconnection. Line and gate areas are then formed by an etching process. Among them, the area where the local interconnects are scheduled to form is at least part of the buried window, that is, the edges of the photoresist curtain layer used to define the local interconnects need only be within the range of the buried window. Are all embedded contact windows that can form the present invention. Because the tolerance range of the process allowed by the present invention is much larger than the error range of the instrument misalignment, the process window of the present invention has a wide process window, which can reduce the difficulty of the process and increase the throughput of the process (Throughput) ° -Γ. (Please read the notes on the back before filling out this page) Loading --------- Order—I ---— ϊ · ^ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs China National Standard (CNS) A4 Specification (210 * 297 cm) 416124 A7 4784twf.doc / 008 ___B7___ 5. Description of the Invention (k) In order to make the above-mentioned objects, features, and advantages of the present invention more obvious and understandable, the following special A preferred embodiment will be described in detail with the accompanying drawings as follows: Brief description of the drawings: Figures 1A to 1D are cross-sections of a semiconductor device manufacturing process in which a buried contact window is not known. FIGS. 2A to 2B are cross-sectional views of the manufacturing process of a semiconductor device in the process of forming a gate conductor layer and local interconnects in FIG. 1A when a forward alignment error occurs; FIG. 3A Figures to 3B show 1A In the process of forming the gate conductor layer and local interconnects, a cross-sectional view of the manufacturing process of the semiconductor element when a negative alignment error occurs; and FIGS. 4A to 41 illustrate embodiments of the present invention. Process cross-sectional view of a method for manufacturing a semiconductor element of a buried contact window. Description of graphical symbols: 100 '200 substrate 102 isolation area 104, 202 oxide layer 106' 112 polycrystalline silicon layer 108 '114' 114a '114b photoresist layer 109, 120, 128, 216 ion implantation process 110, 218 buried window 116 Gate conductor layer 118 Local interconnects 122, 242 Lightly doped source / drain region 7 This paper size applies to China National Standard (CNS) A'l specification (2〗 0 X 297 mm) (Please read first Note on the back, please fill in this page again) — 11 ί I order ---------- Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Printed by the Consumer Goods Cooperative of the Ministry of Economic Affairs, printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economy, printed by 416124 A7 4784twf, doc / 008 _B7_ V. Description of the invention (ί) 124 '126' 244 '246 spacer 130, 250 heavily doped source / drain region 132 > 252 lightly doped source / drain region 134 photoresist Edge 136 Edge of buried window 204, 204a, 204b, 222, 222a, 222b Conductor layer 206, 212, 226 Cover layer 208 trench 210 insulation layer 214 opening 220 groove 224 doped region 228 predetermined gate region 230 predetermined portion Interconnect area 232 Area range 234 Edge of mask layer 236 Gate conductor layer 23 8 Internal wiring 240 Lightly doped ion implantation process 248 Heavyly doped ion implantation process Example 1 FIGS. 4A to 41 illustrate an embodiment of the present invention, a method for manufacturing a semiconductor device of a buried contact window Process sectional view. First, please refer to FIG. 4D. The manufacturing of the buried contact window of the present invention first provides the formed oxide layer 202, the conductive layer 204, and the isolation region 210. --------- 1 --- ^ ii- --- 1 Order --------- ambiguity (please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210x297 mm) 416 124 4 7 8 4 twf, doc / 008 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs * 'Clothing 5. Description of Invention ()) Base 200. The method of forming the structure as shown in FIG. 4D can be achieved through the methods of FIGS. 4A to 4D. However, this method is not intended to limit the present invention. Please refer to FIG. 4A. First, a substrate 200 is provided, for example, a lightly doped P-type well region or a P-type semiconductor, and an oxide layer 202, a conductor layer 204, and a mask layer 2 are sequentially formed on the substrate 200. 6. The method for forming the oxide layer 200 includes a thermal oxidation method, for example, at a temperature of about 800 ° C to 10,000. (: In the oxygen environment, an oxide layer with a thickness of about 30 angstroms to 200 angstroms is formed on the substrate 200. The material of the conductor layer 204 is, for example, doped polycrystalline silicon or a metal such as aluminum, copper, or tungsten, The formation method is, for example, a chemical vapor deposition method with a thickness of about 500 Angstroms to 2500 Angstroms. The material of the mask layer 206 is different from the subsequent material used to form the isolation region. The material is, for example, silicon nitride. The formation method is, for example, a chemical vapor deposition method. Next, referring to FIG. 4B, the mask layer 206, the conductor layer 204, and the oxide layer 202 are patterned by a lithography imaging technique and an etching process, and formed in the substrate 200. The trench 208. Then, an insulating layer 210 is formed on the substrate 200 to fill the trench 208. The material of the green insulating layer 210 is, for example, silicon oxide, and the formation method thereof is, for example, tetraethoxysilane (TEOS) as The chemical vapor deposition method of the gas source, the preferred method is to further compact the oxide layer after the oxide layer is formed. Then, 'refer to FIG. 4C, and remove the insulating layer 210 other than the trench 208'. To remain in the trench 208 The edge layer 210 forms the isolation region. A preferred method of removal is, for example, using the mask layer 206 as a honing termination layer, and honing and removing the insulating layer 210 covered on the upper surface of the mask layer 206 by a chemical mechanical honing technique. 9 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) I --- ^-IIIII, — I! II, i! 1 I _ Jun (Please read the precautions on the back before (Fill in this page) A7 A7 Printed by wf.doc / 008 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. After the description of the invention (Chinese), please refer to Figure 4D 'Remove the cover layer 206' to expose the conductor layer 204 Surface. The method of removing the mask layer 206 is, for example, a wet etching method. Next, referring to FIG. 4E, a mask layer 212 is formed on the substrate 200. The material of the mask layer 212 is, for example, a photoresist, which has a The opening 214 exposes the surfaces of the conductive layer 204 and the insulating layer 210. Thereafter, the mask layer 212 is used as an implant mask, and an ion implantation process 216 is performed to form a layer under the oxide layer 202 corresponding to the opening 214. Buried window 218. Next, refer to Figure 4F to remove the opening A part of the insulating layer 210 exposed at 214 is formed to expose the sidewall 220 of the conductor layer 204 and a recess 220 of the buried window 218. The removal method is, for example, using the mask layer 210 as a uranium engraved mask and using dry etching The process is to remove a part of the insulation layer 210 exposed by the opening 214. After that, please refer to FIG. 4G to remove the mask layer 212. Then, another conductor layer 222 is formed on the surfaces of the conductor layer 204 and the insulation layer 210. Conductor The material of the layer 222 is, for example, doped polycrystalline silicon, metal silicide, or a method for forming a metal, such as a chemical vapor deposition method, and a preferred thickness is sufficient to fill the groove 220, for example, 500 Angstroms to 2500 Angstroms. about. When the material of the conductor layer 222 is doped polycrystalline silicon, the subsequent thermal process will diffuse the doping in the polycrystalline silicon layer into the substrate 200 to form a doped region 224. This doped region 224 can be regarded as one of the buried windows of the buried contact window. After the conductive layer 222 is inserted into the groove 2:20, the conductive layer 222 is electrically coupled to the first conductive layer 204 and the buried window 218. Next, please continue to refer to FIG. 4G, and form a cover layer 226 on the conductor layer 222. The material of the cover layer 226 is, for example, a photoresist, which covers the pre-printed paper standard Halogen 0® House Standard (CNS) A4. Specifications (210x 297 mm) t -------- Order --------- line (Please read the phonetic on the back? Matters before filling out this page) A7 B7 416124 4784twf.doc / 008 5 2. Description of the invention (γ) < Please read the notes on the back before filling this page.) Determine the wide area 228 and the local interconnecting area 230. Among them, the predetermined formation of the local interconnect region 230 covered by the mask layer 226 is at least part of the buried window 218, that is, the edge 234 of the mask layer 226 used to define the local interconnect region 230 only needs to be Located in the range shown by the mark 232 in the drawing, they are all embedded contact windows that can be invented. It is preferred that the edge 234 of the mask layer 226 be located about the centerline of the range 232. Because the range covered by mark 234 can indicate the error range of this process, and this range is larger than the error range of the instrument misalignment, the process window of the process of the present invention is very wide, which can reduce the difficulty of the process Increase the throughput of the process. After that, please refer to FIG. 4H, remove the exposed conductive layer 222 and the conductive layer 204 of the cover layer 226, so that the remaining conductive layer 222a and the conductive layer 204a form the gate conductive layer 236 of the gate; The conductive layer 222b and the conductive layer 204b form a local interconnection 238 of the buried contact window. The removal method is achieved by using the mask layer 226 as an etching mask and performing an anisotropic etching process. Then, the mask layer 226 is removed, and the gate conductor layer 236 and the local interconnects 238 are used as implant masks, and a lightly doped ion implantation process 240 is performed to form a lightly doped source / Drain region 242. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Then, referring to the figure, a gap wall 244 and a gap wall 246 are formed on the side walls of the gate conductor layer 236 and the local interconnects 238, respectively. The material of the spacer 244 and the spacer 246 is, for example, silicon nitride, and the formation method thereof is, for example, forming a silicon nitride layer on the substrate 200 by a chemical vapor deposition method, and then forming the spacer 244 through an etch-back process. With a spacer 246. Thereafter, the gate conductor layer 236, the local interconnects 238, the spacer M4, and the spacer 246 are implanted as a mask, and a heavily doped ion implantation step 248 is performed. A4 specifications < 210 ^ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 416 124 4 7 8 4 twf. Doc / 〇〇 8 ^ ________B7_ V. Description of the invention ((.) To form a heavily doped source in the substrate 200 / The drain region 250 completes the fabrication of a source / drain region 252 with a lightly doped drain structure. In the process of forming the gate conductor layer 236 and the local interconnects 238 in the method of the present invention, regardless of whether the instrument occurs Positive misalignment or negative misalignment 'Due to the wide pre-preparation of the process, the local interconnects 238 formed can all be located within the area covered by the mark 232, allowing them to pass through the buried window 218 is electrically coupled to the source and drain region 252, so that the buried contact window can perform its function, and there is no conventional method that causes groove marks due to positive misalignment or negative misalignment. Problems that prevent the buried window from being electrically coupled to the source / drain region The local interconnects formed by the above methods can be used to electrically connect the gate and source / drain regions. Therefore, the present invention can be applied to logic circuits and static random access memories (Static Random Access Memory, medium. In summary, it has at least the following advantages: 1. The process of the present invention is wide, which can reduce the difficulty of the process, and increase the production of the process. | 2 2. The method of the present invention can be stopped. It is known that the alignment error causes the formation of groove marks and the electrical failure of the buried window and the source / drain region to be electrically coupled. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention, any familiarity Those skilled in the art can make various modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application. ^^- --- „---- ^ -------- Order --------- line (please read the precautions on the back before filling this page) This paper size is applicable to China® Home Standard ( CNS) AO see the grid (2) 0 × 297 mm)