A7 * ' _ _____〜 B7____ 五、發明説明（/) 發明之背暑 1. 發明之領域 本發明有關一種用於製造半導體記億體裝置之方法， 且更特別地有關一種用於製造半導體記憶體裝置之三重井 的方法。 2. 相關技藝之說明 大致地，互補之金屬氧化物半導體(COMOS)動態隨機 存取記憶體(DRAM)裝置係施加一反向偏壓vBB至基片以改 善避免閂鎖的能力、單元之隔離及操作之速度。然而，在 諸如次微米裝置之高度積體的半導體記憶體裝置之中，該 反向偏壓會在N通道電晶體中增加短通道效應。爲解決此 問題，已建議有一種三重井結構，其中該反向偏壓Vbb係 加於一記億體單元陣列區，而一接地電壓Vbb則施加於週 邊電路區之一區域中，其中將形成一N通道電晶體，藉此 增進該電晶體裝置之特性。 經濟部智慧財產局員工消費合作社印製 ’一----------裝— ·(請先时讀背面之注意事項\^寫本頁) -線 © 採用此種三重井結構之半導體記憶體裝置係顯示於第 1圖之中，參閱第1圖，其中該形成N通道電晶體之第一 P型井110及第二P型井120係形成於一 P型基片之上； 該等N通道電晶體含有閘極116及126，分別地形成於閘 極氧化物膜114及124之上且分別在成爲源極及汲極之N 型摻雜物區112及122之側；同時，一具有P通道電晶體 之第一 N型井係形成於週邊電路區之中，此處該P通道電 晶體含有將爲源極及汲極區之P型摻雜物區132 ’ 一閘極 氧化物膜134及一閘極136。 __' ___4_—_ 本紙張尺度適用中國國家標準（CNS ) A4規格（X 297公釐） 經濟部智慧財產局員工消費合作社印製 A7 __.__B7______ 五、發明説明（>〇 該第一 P型井110與第二P型井120係藉一包封該第 二P型井120之第二N型井140所分開。.該第二N型井 140具有一側壁區142，垂直延伸於基片100之表面下方至 一第一深度，及一橫向地以一第二深度形成於基片100之 表面下方且連接於側壁區142之下方部分之底部區144。 所以，反向偏壓VBB係施加於第二P型井120中所形 成之P型摻雜物區128，而接地電壓Vss係施加於第一 P型 井110中所形成之P型摻雜區118之中。同時，一電源電 .壓Vee係施加於第一N型井130中所形成之N型摻雜物區 138之中。 然而，如第1圖中所示，爲了形成一含有第一 P型井 110、第二P型井120、第一 N型井130、以及第二N型井 之底部區144及側區142之三重井結構，整個方法會是複 雜的，因爲微影法至少必須執行4次。 同時，在該三重井之結構中，重要的是，該第二N井 140之底部區144及側壁區142須完整地包封該第二P型井 120以完全地電氣隔離該第二p型井120與該第一 P型井 110。然而，若對準失誤在用於形成底部區144之微影術期 間發生時，會造成虛線所示之第二N型井140之底部區 144’，因而該底部區144’與該側壁區142之重疊不夠充分 ’導致第一 P型井110與第二p型井120間之短路。 發明之槪沭 爲解決上述問題，本發明之目的在於提供一種簡單之 方法用於形成一具有增進電氣特性之三重井。 本氏張尺度適用中國國家標準（CNS )八视格（210χ:297公釐） !~----------^ —— ~請先閱讀背面之注意事項λ寫本頁) 訂 -線 Θ A7 _______B7_ 五、發明説明（3) 根據本發明所製造之三重井結構具有一第一導電型之 第一井’一第一導電型之第二井，一第二導電型之第一井 ，及一包封該第一導型之第二井以便分開該第一導電型之 第一井與第一導電型之第二井的第二導電型之第二井，均 形成於第一導電型之一半導體基片中。同時，第二導電型 之第二井具有諸側壁區，在該基片之表面下方延伸至一具 有一第一深度之區；及具有一底部區，連接到該等側壁區 之下方部分且以一第二深度形成在該基片之表面下方。 根據本發明用於製造三重井結構的方法之一形態，該 第二導電型之第二井的底部區及該第一導電型之第二井係 利用相同之離子植入遮罩之圖型予以形成；接著，當形成 該第二導電型之第二井的底部區時，該第二導電型之摻雜 物係利用該離子植入遮罩之圖型以一相對垂直於該半導體 基片之入射角0來植入於該半導體基片之表面上，使得該 第二導電型之第二井之底部區形成於一較寬於該遮罩圖型 所暴露之區域中。， 較佳地，該入射角0之範圍從5度到30度，而界定該 第二導電型之第二井之底部區的遮罩圖型暴露該半導體基 片之區域於該第二導電型之第二井之側壁區之該等內壁之 間。 根據本發明用於製造三重井結構的方法之另一形態’ 該等側壁區及該第二導電型之第二井的底部區係利用相等 或相類似之離子植入能量予以形成，使得該等側壁區與底 部區相互重疊而完全地分開該第一導電型之第一井與該第 —------;___g_ __ 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 2.97公釐）_ . (請先閱讀背面之注意事項寫本頁) 裝· 訂 經濟部智慧財產局員工消費合作社印製 A7 ________B7 __ 五、發明説明（f) 一導電型之第二井，而該第二導電型之第二井的底部區及 該第一導電型之第二井則利用相同之遮罩圖型作爲離子植 入遮罩來形成。 較佳地，形成該等側壁區及該第二導電型之第二井的 底部區之步驟包含製備該第一導電型之半導體基片之諸子 步驟。一界定該第二導電型之第二井之該等側壁區之第一 遮罩圖型係形成於該第一導電型之半導體基片之上；接著 ，利用該第一遮罩圖型作爲離子植入遮罩而以一第一能量 來植入該第二導電型之摻雜物，去除該第一遮罩圖型，而 一界定該第二導電型之第二井之底部區的第二遮罩圖型則 形成於該半導體基片之上；最後，利用該第二遮罩圖型作 爲離子植入遮罩而以一相等或相類似於該第一能量之第二 能量來植入該第二導電型之摻雜物，而形成該第二導電型 之第二井的底部區於一相等或相類似於該第一深度之第二 深度處。 較佳地，在去除該第一遮罩圖型之步驟之前，該第二 導電型之摻雜物係利用該第一遮罩圖型作爲離子植入遮罩 而植入於一高於該第一能量之能量處。 仍是根據本發明用於製造三重井結構的方法之另一形 態，在製備第一導電型之半導體基片之後，一界定第二導 電型之第二井之底部區的遮罩圖型係形成在該第一導電型 之半導體基片之上，接著，第二導電型之摻雜係利用該遮 罩圖型作爲離子植入遮罩來植入以形成該第二導電型之第 二井之底部區，然後，在形成諸間隔物於該遮罩圖型之該 _；____7_____ 本紙浪尺度適用中國國家標準TcNS ) A4規格（210X297公釐） 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（匕） 等側壁上之後，利用該遮罩圖型及該等間隔物作爲離子植 入遮罩來植入第一導電型之摻雜物以形成第一導電型之第 二井。 較佳地，該遮罩圖型部分地或完全地暴露出形成於該 第一導電型之第二井之該等側壁處之第二導電型之第二井 的側壁區，及暴露出覆蓋著由該遮罩圖型所暴露之第二導 電型之第二井的側壁區。 根據本發明於製造三重井結構的方法之再一形態，一 界定該第一導電型之第二井的第一遮罩圖型係形成於該第 一導電型之半導體基片之上，接著，利用該第一遮罩圖型 作爲離子植入遮罩來植入爲一導電型之摻雜物以形成第一 導電型之第二井，然後，減少該第一遮罩圖型之大小而形 成一第二遮罩圖型，暴露出一較寬於該第一遮罩圖型所暴 露之區域的區域，最後，利用該第二遮罩圖型作爲離子植 入遮罩來植入第二導電型之摻雜物而形成該第二導電型之 第二井的底部區於該第一導電型之第二井下方，該底部區 具有較大於該第一導電型之第二井的寬度。 較佳地，該第二遮罩圖型係形成以部分地或完全地暴 露出形成在該第一導電型之第二井之該等側壁處之該第二 導電型之第二井之該等側壁區。 根據本發明，一具有完美結構之三重井可透過一簡單 之方法予以形成》 圖式之簡要說明 本發明之上述目的及優點將藉參照所附圖式詳細地描 __ _______8_ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項寫本頁) •裝· 訂 A7 ______B7___ 五、發明説明（&) 述其較佳實施例而呈更明顯，其中： 第1圖係具有可由本發明形成之三重井結構之半導體 記憶體裝置之截面圖； 第2至5圖係中間結構之截面圖，描繪根據本發明第 —實施例之用於形成三重井之方法； 第6至9圖係中間結構之截面圖，描繪根據本發明第 二實施例之用於形成三重井之方法； 第10及11圖係中間結構之截面圖，描繪根據本發明 第三實施例之用於形成三重井之方法； 第12及13圖係中間結構之截面圖，描繪根據本發明 第四實施例之用於形成三重井之方法；以及 第14及15圖係中間結構之截面，描繪根據本發明第 二實施例之用於形成三重井之方法； 較佳實施例之說明 現將參照其中顯示本發明諸較佳實施例之該等附圖來 更完整地描述本發明。然而，本發明可以用許多不同之形 式來實施，且不應解釋爲受限於本文所揭示之該等實施例 ;適言之，該等實施例係提供使得此揭示將完全且完整， 且將完全地轉移本發明之理念至該等熟習於本項技術者。 在該等圖式中，.諸層及諸區之厚度係誇大以爲了淸楚起見 ，同時，將理解的是，該等圖式中之導電型式係以P型基 片爲主作例示，所以，該基片之導電型式可替換性地爲N 型基片，當使用N型基片時，該等井之導電形式係相反於 該等顯示於圖式者。在不同圖示中之相同的參考數字代表 本紙張尺度適用中國國家標準（CNS ) A4規格（210Χ297公釐） (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（^) 相同之元件。 第一實施例 參閱第2圖，在藉一普通之方法在一例如第一導電型 之P型半導體基片200上形成一襯墊氧化物膜205之後， 第一遮罩圖型210M係形成以界定一例如第一 p型井21〇 之第一導電型之第一井，接著，P型摻雜物離子209係利 用該第一遮罩圖型210M作爲離子植入遮罩予以植入而形 成一第一 P型井210，然後，藉普通之方法來去除該第一 遮罩圖型210M。 參閱第3圖’一界定例如第一 N型井之第二導電型之 第一井及例如第一 N型井之第二導電型之第二井之諸側壁 的第二遮罩型342M係形成於具有第一 P型井210之半導 體基片200之整個表面上，接著，利用該第二遮罩圖型 342M作爲離子植入遮罩來植入一 N型之摻雜物離子341以 形成一第一 N型井330於週邊電路區之中，及形成第二N 型井之諸側壁區342於一單元陣列區之中，然後，藉普通 之方法來去除該第二遮罩圖型342M。 參閱第4圖，一界定第二N型井之底部區之第三遮罩 圖型444M係形成於基片200之整個表面上，該第三遮罩 圖型444M係形成以暴露出由該第二N型井之該等側壁區 342之內側壁所界定之半導體基片之區。 接著，利用該第三遮罩型444M作爲離子植入遮罩來 傾斜地植入N型摻雜離子443以形成第二N型井底部區 444，藉此完成一含有該等側壁區342及該底部區444之第 ________：____ 10 1J---r------ * (請先閲讀背面之注意事項再填寫本頁) 、τ 〇A7 * '_ _____ ~ B7____ 5. Description of the Invention (/) The Summer of the Invention 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly to a method for manufacturing a semiconductor memory. Method for installing triple wells. 2. Description of related techniques In general, complementary metal oxide semiconductor (COMOS) dynamic random access memory (DRAM) devices apply a reverse bias vBB to the substrate to improve the ability to avoid latch-up and cell isolation. And speed of operation. However, in highly integrated semiconductor memory devices such as sub-micron devices, this reverse bias can increase the short channel effect in the N-channel transistor. In order to solve this problem, a triple well structure has been proposed, in which the reverse bias voltage Vbb is applied to a memory cell array area, and a ground voltage Vbb is applied to an area of a peripheral circuit area, where An N-channel transistor, thereby improving the characteristics of the transistor device. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ———————————— (Please read the precautions on the back \ ^ write this page) -line © adopting this triple well structure The semiconductor memory device is shown in FIG. 1. Referring to FIG. 1, the first P-type well 110 and the second P-type well 120 forming the N-channel transistor are formed on a P-type substrate; The N-channel transistors include gates 116 and 126, which are formed on the gate oxide films 114 and 124, respectively, and on the sides of the N-type dopant regions 112 and 122 which become the source and the drain, respectively; A first N-type well system with a P-channel transistor is formed in the peripheral circuit region. Here, the P-channel transistor contains a P-type dopant region 132 'which will be a source and a drain region. A gate The oxide film 134 and a gate electrode 136. __ '___ 4 _—_ This paper size is applicable to Chinese National Standard (CNS) A4 (X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 __.__ B7______ 5. Description of the invention (> 〇 This first P type The well 110 and the second P-type well 120 are separated by a second N-type well 140 enclosing the second P-type well 120. The second N-type well 140 has a side wall region 142 extending perpendicularly to the substrate A bottom region 144 below the surface of 100 to a first depth, and a bottom region 144 laterally formed below the surface of the substrate 100 and connected to the lower portion of the side wall region 142 at a second depth. Therefore, the reverse bias VBB is applied The P-type dopant region 128 formed in the second P-type well 120, and the ground voltage Vss is applied to the P-type doped region 118 formed in the first P-type well 110. At the same time, a power source Vee is applied to the N-type dopant region 138 formed in the first N-type well 130. However, as shown in FIG. 1, in order to form a first P-type well 110 and a second P-type well The structure of the triple wells in the bottom region 144 and the side region 142 of the well 120, the first N-well 130, and the second N-well is as follows: It is complicated because the lithography method must be performed at least 4 times. At the same time, in the structure of the triple well, it is important that the bottom region 144 and the sidewall region 142 of the second N well 140 must completely encapsulate the second P Pattern well 120 to completely electrically isolate the second p-type well 120 from the first p-type well 110. However, if an alignment error occurs during the lithography used to form the bottom region 144, it will result in a dashed line The bottom region 144 'of the second N-type well 140, so that the bottom region 144' and the sidewall region 142 do not sufficiently overlap 'causes a short circuit between the first P-type well 110 and the second p-type well 120. 发明 的 槪沭 In order to solve the above problems, the purpose of the present invention is to provide a simple method for forming a triple well with enhanced electrical characteristics. The Benn scale is applicable to the Chinese National Standard (CNS) eight-view grid (210χ: 297 mm)! ~ ---------- ^ ---- ~ Please read the notes on the back λ and write this page) Order-line Θ A7 _______B7_ V. Description of the invention (3) The triple well structure manufactured according to the present invention has A first well of the first conductivity type'a second well of the first conductivity type, a second well A first well of the electric conductivity type and a second well of the second conductivity type encapsulating the second well of the first conductivity type so as to separate the first well of the first conductivity type from the second well of the first conductivity type, Both are formed in a semiconductor substrate of one of the first conductivity types. At the same time, the second well of the second conductivity type has sidewall regions extending below the surface of the substrate to a region with a first depth; and a bottom region connected to the lower portions of the sidewall regions and A second depth is formed below the surface of the substrate. According to one aspect of the method for manufacturing a triple-well structure of the present invention, the bottom region of the second well of the second conductivity type and the second well system of the first conductivity type are formed using the same pattern of ion implantation masks. Forming; then, when the bottom region of the second well of the second conductivity type is formed, the dopant of the second conductivity type uses the pattern of the ion implantation mask to be relatively perpendicular to the semiconductor substrate The incident angle 0 is implanted on the surface of the semiconductor substrate, so that the bottom region of the second well of the second conductivity type is formed in a region wider than the area exposed by the mask pattern. Preferably, the incident angle 0 ranges from 5 degrees to 30 degrees, and a mask pattern defining a bottom region of the second well of the second conductivity type exposes a region of the semiconductor substrate to the second conductivity type. Between the inner walls of the side wall area of the second well. According to another form of the method for manufacturing a triple-well structure according to the present invention, the side wall regions and the bottom region of the second well of the second conductivity type are formed using equal or similar ion implantation energy such that the The side wall area and the bottom area overlap each other to completely separate the first well of the first conductivity type from the first —------; ___g_ __ This paper size applies to China National Standard (CNS) A4 (210 X 2.97 cm) (%) _. (Please read the notes on the back to write this page) Binding and ordering printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ________B7 __ 5. Description of the invention (f) The second well of a conductive type, and the first The bottom region of the second well of the second conductivity type and the second well of the first conductivity type are formed using the same mask pattern as an ion implantation mask. Preferably, the step of forming the sidewall regions and the bottom region of the second well of the second conductivity type includes sub-steps of preparing a semiconductor substrate of the first conductivity type. A first mask pattern defining the sidewall regions of the second well of the second conductivity type is formed on the semiconductor substrate of the first conductivity type; then, the first mask pattern is used as ions A mask is implanted and a dopant of the second conductivity type is implanted with a first energy, the first mask pattern is removed, and a second defining a bottom region of the second well of the second conductivity type A mask pattern is formed on the semiconductor substrate; finally, the second mask pattern is used as an ion implantation mask to implant the second pattern with an equal or similar second energy to the first energy. The dopant of the second conductivity type, and the bottom region of the second well forming the second conductivity type is at a second depth equal to or similar to the first depth. Preferably, before the step of removing the first mask pattern, the dopant of the second conductivity type is implanted at a position higher than the first implant pattern using the first mask pattern as an ion implantation mask. The energy of energy. Still another form of the method for manufacturing a triple-well structure according to the present invention. After the semiconductor substrate of the first conductivity type is prepared, a mask pattern defining a bottom region of the second well of the second conductivity type is formed. On the semiconductor substrate of the first conductivity type, then, the doping of the second conductivity type is implanted using the mask pattern as an ion implantation mask to form a second well of the second conductivity type. The bottom area, then, the spacers on the mask pattern are formed by the _; ____7_____ This paper wave scale applies the Chinese national standard TcNS) A4 specifications (210X297 mm) printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 2. Description of the invention (dagger) After using the mask pattern and the spacers as ion implantation masks, the dopants of the first conductivity type are implanted to form the second well of the first conductivity type. Preferably, the mask pattern partially or completely exposes a sidewall region of a second conductive type second well formed at the sidewalls of the first conductive type second well, and exposes a covering The sidewall region of the second well of the second conductivity type exposed by the mask pattern. According to another form of the method for manufacturing a triple-well structure of the present invention, a first mask pattern defining a second well of the first conductivity type is formed on the semiconductor substrate of the first conductivity type, and then, Use the first mask pattern as an ion implantation mask to implant a dopant of a conductive type to form a second well of the first conductive type, and then reduce the size of the first mask pattern to form A second mask pattern exposing an area wider than the area exposed by the first mask pattern; and finally, using the second mask pattern as an ion implantation mask to implant a second conductive The bottom region of the second well of the second conductivity type is formed by a dopant of a type dopant below the second well of the first conductivity type, and the bottom region has a width larger than that of the second well of the first conductivity type. Preferably, the second mask pattern is formed to partially or completely expose the second wells of the second conductivity type formed at the sidewalls of the second well of the first conductivity type. Sidewall area. According to the present invention, a triple well with a perfect structure can be formed by a simple method "Brief description of the drawings The above-mentioned objects and advantages of the present invention will be described in detail by referring to the attached drawings __ _______8_ This paper scale is applicable to China National Standard (CNS) A4 specification (210X297 mm) (Please read the notes on the back to write this page) • Binding and ordering A7 ______B7___ 5. The & description of the invention describes its preferred embodiment and it is more obvious, of which : Fig. 1 is a cross-sectional view of a semiconductor memory device having a triple-well structure that can be formed by the present invention; Figs. 2 to 5 are cross-sectional views of an intermediate structure, depicting a method for forming a triple-well according to the first embodiment of the present invention Method; Figures 6 to 9 are sectional views of the intermediate structure, depicting a method for forming a triple well according to the second embodiment of the present invention; Figures 10 and 11 are sectional views of the intermediate structure, depicting the third embodiment according to the present invention Examples of a method for forming a triple well; Figures 12 and 13 are cross-sectional views of intermediate structures depicting a method for forming a triple well according to a fourth embodiment of the present invention; and No. 14 And FIG. 15 is a cross-section of an intermediate structure depicting a method for forming a triple well according to a second embodiment of the present invention; a description of a preferred embodiment will now be made with reference to the drawings in which preferred embodiments of the present invention are shown The invention is more fully described. The invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments disclosed herein; rather, the embodiments are provided so that this disclosure will be thorough and complete, and Completely transfer the concept of the present invention to those skilled in the art. In these drawings, the thicknesses of the layers and regions are exaggerated for the sake of clarity. At the same time, it will be understood that the conductive type in these drawings is mainly exemplified by the P-type substrate. Therefore, the conductive type of the substrate is alternatively an N-type substrate. When an N-type substrate is used, the conductive forms of the wells are opposite to those shown in the drawings. The same reference numerals in different illustrations indicate that this paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 × 297 mm) (Please read the precautions on the back before filling this page) Order the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed A7 B7 V. Description of Invention (^) The same components. The first embodiment is shown in FIG. 2. After a pad oxide film 205 is formed on a P-type semiconductor substrate 200 of, for example, a first conductivity type by a conventional method, a first mask pattern 210M is formed to A first well of a first conductivity type is defined, for example, a first p-type well 21o. Then, the p-type dopant ion 209 is formed by implanting the first mask pattern 210M as an ion implantation mask. A first P-type well 210 is then used to remove the first mask pattern 210M by a common method. Refer to FIG. 3 'a second mask type 342M system defining a first well of a second conductivity type such as a first N-type well and a second well of a second conductivity type such as a first N-type well On the entire surface of the semiconductor substrate 200 having the first P-well 210, the second mask pattern 342M is used as an ion implantation mask to implant an N-type dopant ion 341 to form a The first N-type well 330 is in the peripheral circuit region, and the sidewall regions 342 forming the second N-type well are in a cell array region. Then, the second mask pattern 342M is removed by a common method. Referring to FIG. 4, a third mask pattern 444M defining a bottom region of the second N-type well is formed on the entire surface of the substrate 200, and the third mask pattern 444M is formed to expose the first mask pattern 444M. A region of a semiconductor substrate defined by the inner sidewalls of the sidewall regions 342 of the two N-type wells. Then, the third mask type 444M is used as an ion implantation mask to implant N-type doped ions 443 obliquely to form a second N-type well bottom region 444, thereby completing a process including the sidewall regions 342 and the bottom. The first ________: ____ 10 1J --- r ------ * of area 444 * (Please read the notes on the back before filling this page), τ 〇
本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） A7 __' _B7___. 五、發明説明（/) 二N型井440。 爲了傾斜地植入該等N型摻雜離子442，該半導體基 片200係傾斜地承載於一離子植入裝置(未圖示)之上，使 得該等摻雜物離子以一相對垂直於該基片200之入射角Θ 來植入該基片200之表面中。 此處，該入射角0可從5度至30度之範圍，該入射角 係由底部區444與該等側壁區342間之重疊區域之寬度wl ，及摻雜物離子之.射出範圍(RP :從該基片之表面至一具有 最大摻雜濃度之區域的距離)所確定。 也就是說，該入射角Θ係由下一方程式⑴所計算出： ~請先閱讀背面之注意事項务#寫本頁) 裝- 訂 在方程式⑴之中，0代表入射角度，wl代表該底部區 444與該等側壁區342間之重疊區之寬度，及Rp代表摻雜 物之射出範圍。 根據本發明，該三重井之最適宜Rp範圍自至1.8微米 ，而最適宜之重疊寬度wl係範圍自0.2至0.8微米。因此 ，藉替換方程式⑴之Rp及wl之各最適宜準位。可理解的 是，在入射角範圍自5度至30度處植入該等摻雜物離子係 較佳的。 如上述，因爲在此實施例中，該等N型摻雜物離子 443係傾斜地植入，所以該第二N型井之底部區444可橫 向地延伸於該第三遮罩圖型444M所暴露之區域之外部， 因此，在該底部區444與該第二N型井之該等側壁區342 ------ 11_____ 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） 線 經濟部智慈財產局員工消費合作社印製 A 7 _ B7 五、發明説明（^ ) 間之重疊區之寬度wl會增加，藉此完全地電氣隔離該第 一 P型井210與將在接著之步驟所成之第二P型井520(參 閱第5圖）。所以，會防止該兩井210及520間之短路，且 可施加不同之電壓於該兩井。 參閱第5圖，P型摻雜物離子519係利用界定該第二 N型井之底部區444之第三遮罩圖型作爲離子植入遮罩予 以植入，藉以完成一第二P型井520。 如上述，藉根據本發明實施例來形成該三重井結構， 可使該底部區444與該第二型并之該等側壁區342間之 重疊區之寬度wl最大化，所以可藉完全地電氣隔離該兩 井於彼此來防止該第一 P型井210與該第二P型井520間 之短路。同時，該第二N型井之底部區444與該第二P型 井520可利用一遮罩圖型444M來形成。 此允許省略圖一形成例如光阻圖型之遮罩圖型之步驟 ，藉此簡化了該製程且降低了製造成本。 經濟部智慧財產局員工消費合作社印製 在本發明之此實施例中，在形成該第一 P型井210 ’ 該第一N型井330及該第—· N型井之該等側壁區342之後 ，形成該第二N型井之底部區444及該第二P型井。然而 ，該等步驟之順序可予以改變，也就是說，在形成該第二 N型井之底部區及該第二P型井520之後’可形成該第一 P型井210，該第一 N型井330及該第一 N型井之該等側 壁區342，同時，該第二P型井520可在形成該第二N型 井之底部區444之前形成。 第二實施例 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） A7 B7 五、發明説明（/ 0) 參閱第6圖，一界定該第一 N型井及該第二N型井之 該等側壁區之第一遮罩圖型642M係形成一具有第一P型 井610之半導體基片之襯墊氧化物膜之上，N型摻雜物離 子641係利用該第一遮罩圖型642M作爲離子植入遮罩而 在範圍0.2至l.OMeV(百萬電子伏特)之離子植入能量處予 以褲入，以形成各具有D1深度之第一 N型井630 ‘及該第 二N型井之諸側壁區642’ 。 接著，如第7.圖中所示，N型摻雜物離子741係再利 用該第一遮罩圖型642M作爲離子植入遮罩且改變該離子 植入能量至範圍至1.0至1.8MeV來植入以形成各具有D2 測度之第一 N型井730’及該第二N型井之諸側壁區742’。 結果，完成了一含有具D1深度之第一 N型并630 ‘及具 D2深度之第一 N型井730’之第一 N型井730，以及含有 具D1深度之該第二N型井之該等側壁區642 4及具有D2 深度之第二N型井之該等側壁區742’之該第二N型井之 諸側壁區742。接著，藉一般之方法來去除該第一遮罩圖 型 642M 〇 經濟部智慧財產局員工消費合作社印製 參閱第8圖，一界定該第二N型井之底部區的第二遮 罩圖型844M係形成於該襯墊氧化物膜605之上，接著， 利用該第二遮罩圖型844M作爲離子植入遮罩離子植入能 量範圍自1.0至1.8MeV處植入N型摻雜物離子843而形成 該第二N型井之底部區844。 所以，該第二N型井之該等側壁區742之最大射出範 圍Rp呈相等於該底部區844之最大射出範圍，使得該等側 _________L3___ 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0X297公釐） A7 B7 五、發明説明（Η ) 壁區742在如第8圖中所不之垂直方向中充分地與該底部 區844重疊，藉此完成一第二N型井840。 參閱第9圖，再利用該第二遮罩圖型844M作爲離子 植入遮罩在離子植入能量範圍自100至500MeV處植入p 型摻雜物離子#9 ^_成一第二P型井920。 在此實施例中，該第二N型井之側壁區742係藉離子 植入兩次來形成，特別地，用於形成該第二N型井之底部 區844之離子植入能量與用於形成該第二N型井之該等側 壁區742之離子植入能量係彼此相同或相類似，使得該底 部區844與該等側壁區742在垂直方向中充分地重疊，藉 此完成該第二N型井840。 同時，該第二N型井840之底部區844及該第二p型 井920係藉一遮罩圖型844M來界定，簡化了該方法。 在此實施例中，用於在不同植入能量處執行離子植入 兩次來形成該第二N型井之該等側壁區742之理由係如下 所述。當在具D2深度之深部區之中形成第二N型井之底 部區844時，也就是說，倘若當用於形成底部區844之離 子植入能量爲高之時，該等側壁區742不會連續地從該基 片之表面到達具有D2深度之區，也就是說，該等側壁區 742僅會形成在靠近於從該基片上之表面算起之具有D2深 度之區，若該等側壁區742係僅藉一次在離子植入量等於 或相類似於用於形成該底部區844之離子植入能量處予以 離子植入而形成的話。所以，爲了防止此一不連續之現象 ，用於形成該第二N型并之該等側壁區742之離子植入係 34 ~請先閱讀背面之注意事項—魂寫本頁) .裝. 線 經濟部智慧財產局員X消費合作社印製 t Γ 通This paper size applies to China National Standard (CNS) A4 specification (210X 297 mm) A7 __ '_B7___. 5. Description of the invention (/) Two N-type wells 440. In order to implant the N-type doped ions 442 obliquely, the semiconductor substrate 200 is obliquely carried on an ion implantation device (not shown), so that the dopant ions are relatively perpendicular to the substrate The incident angle Θ of 200 is implanted into the surface of the substrate 200. Here, the incident angle 0 can range from 5 to 30 degrees, and the incident angle is defined by the width wl of the overlapping region between the bottom region 444 and the sidewall regions 342, and the doping ion's emission range (RP : Determined from the distance from the surface of the substrate to a region having a maximum doping concentration). In other words, the angle of incidence Θ is calculated by the following formula ⑴: ~ Please read the precautions on the back #write this page) Binding-Booked in equation ⑴, 0 represents the angle of incidence, wl represents the bottom The width of the overlapping region between the region 444 and the sidewall regions 342, and Rp represents the emission range of the dopant. According to the present invention, the optimal Rp range of the triple well is from 1.8 to 1.8 microns, and the optimal overlap width wl ranges from 0.2 to 0.8 microns. Therefore, by substituting each of Rp and wl of equation ⑴, the most suitable levels. It can be understood that it is better to implant the dopant ions at an incident angle ranging from 5 to 30 degrees. As described above, because in this embodiment, the N-type dopant ions 443 are implanted obliquely, the bottom region 444 of the second N-type well may extend laterally beyond the third mask pattern 444M. Outside the area, therefore, in the bottom area 444 and the side wall areas 342 of the second N-type well ------ 11_____ This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ) Printed by A 7 _ B7 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. The width wl of the overlap between the description of the invention (^) will increase, thereby completely electrically isolating the first P-type well 210 from the The second P-well 520 formed by the following steps (see FIG. 5). Therefore, a short circuit between the two wells 210 and 520 is prevented, and different voltages can be applied to the two wells. Referring to FIG. 5, the P-type dopant ion 519 is implanted by using a third mask pattern defining the bottom region 444 of the second N-type well as an ion implantation mask to complete a second P-type well. 520. As described above, by forming the triple well structure according to the embodiment of the present invention, the width w1 of the overlap region between the bottom region 444 and the side wall regions 342 merged with the second type can be maximized, so it can be completely electrical The two wells are isolated from each other to prevent a short circuit between the first P-well 210 and the second P-well 520. At the same time, the bottom region 444 of the second N-type well and the second P-type well 520 can be formed using a mask pattern 444M. This allows to omit the step of forming a mask pattern such as a photoresist pattern, thereby simplifying the process and reducing manufacturing costs. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs in this embodiment of the present invention, in forming the first P-well 210 ', the first N-well 330, and the sidewall regions 342 of the --N-well Thereafter, a bottom region 444 of the second N-type well and the second P-type well are formed. However, the order of the steps may be changed, that is, after the bottom region of the second N-type well and the second P-type well 520 are formed, the first P-type well 210 may be formed, the first N The well 330 and the sidewall regions 342 of the first N-well, and the second P-well 520 may be formed before the bottom region 444 of the second N-well is formed. Second embodiment This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) A7 B7 V. Description of the invention (/ 0) Refer to Figure 6 for a definition of the first N-type well and the second N-type The first mask pattern 642M of the sidewall regions of the well is formed on a pad oxide film of a semiconductor substrate having a first P-well 610, and the N-type dopant ion 641 uses the first mask Mask pattern 642M is used as an ion implantation mask and is inserted at an ion implantation energy ranging from 0.2 to 1.0 OMeV (million electron volts) to form first N-type wells 630 'each having a depth of D1 and the The sidewall regions 642 'of the second N-type well. Next, as shown in Fig. 7, the N-type dopant ion 741 uses the first mask pattern 642M as an ion implantation mask and changes the ion implantation energy to a range of 1.0 to 1.8 MeV. Implanted to form a first N-well 730 'and a sidewall region 742' of the second N-well each having a D2 measure. As a result, a first N-type well 730 including a first N-type and 630 'with a D1 depth and a first N-type well 730' with a D2 depth and a second N-type well with a D1 depth are completed. The sidewall regions 6424 and the sidewall regions 742 of the second N-well of the sidewall regions 742 'of the second N-well having a depth of D2. Next, the first mask pattern 642M is removed by a general method. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, refer to Figure 8, a second mask pattern that defines the bottom area of the second N-type well. 844M is formed on the pad oxide film 605. Then, the second mask pattern 844M is used as an ion implantation mask. The ion implantation energy range is from 1.0 to 1.8 MeV. 843 forms a bottom region 844 of the second N-well. Therefore, the maximum ejection range Rp of the side wall regions 742 of the second N-type well is equal to the maximum ejection range of the bottom region 844, so that these sides _________L3___ This paper size applies the Chinese National Standard (CNS) A4 specification ( 2 丨 0X297 mm) A7 B7 V. Description of the Invention (Η) The wall region 742 fully overlaps the bottom region 844 in a vertical direction not shown in FIG. 8, thereby completing a second N-type well 840. Referring to FIG. 9, the second mask pattern 844M is used as an ion implantation mask to implant a p-type dopant ion # 9 at an ion implantation energy range from 100 to 500 MeV into a second P-type well. 920. In this embodiment, the sidewall region 742 of the second N-type well is formed by ion implantation twice. In particular, the ion implantation energy used to form the bottom region 844 of the second N-type well and the The ion implantation energies of the sidewall regions 742 forming the second N-type well are the same or similar to each other, so that the bottom region 844 and the sidewall regions 742 fully overlap in the vertical direction, thereby completing the second N-type well 840. At the same time, the bottom region 844 of the second N-type well 840 and the second p-type well 920 are defined by a mask pattern 844M, which simplifies the method. In this embodiment, the reason for performing ion implantation twice at different implantation energies to form the sidewall regions 742 of the second N-type well is as follows. When the bottom region 844 of the second N-type well is formed in the deep region with the D2 depth, that is, if the ion implantation energy used to form the bottom region 844 is high, the sidewall regions 742 do not Will continuously reach the area with D2 depth from the surface of the substrate, that is, the side wall areas 742 will only be formed near the area with D2 depth from the surface on the substrate, if the side walls Region 742 is formed only once by ion implantation at an ion implantation amount equal to or similar to the ion implantation energy used to form the bottom region 844. Therefore, in order to prevent this discontinuity, the ion implantation system 34 used to form the second N-type and the sidewall regions 742 ~ Please read the precautions on the back-soul write page). Member of the Intellectual Property Bureau of the Ministry of Economic Affairs, X Consumer Cooperative, printed t Γ 通
I 規 公 A7 B7 五、發明説明（/>) 在不同之離子植入能量執行兩次。 ^^--------U衣II ί. 1*1 (請先閲讀背面之注意事項再^寫本頁) 因此，若可充分地在垂直方向中重疊該等側壁區742 及該底部區844使得該第一導電型之第一井610及第二井 920可完全予以隔離且該等側壁區742可從該基片之表面 延伸至例如D2之深度，其中將透過離子植入一次來形成 該底部區844時，則較佳地，透過一次離子植入一次，利 用一離子植入能量相等或相類似於用於形成該底部區844 之離子植入能量來形成該等側壁區742。 同時，若需要的話，可執行兩次或更多次之離子植入 〇 第三實施例 經濟部智慧財產局員工消費合作社印製 參閱第10圖，一第一P型井610，一第一· N型井730 及一第二N型井之諸側壁區742係透過相同於第二實施例 之第6圖及第7圖中所^繪之步驟來形成，接著，一界定 該第二N型井之底部區之遮罩圖型1044M係形成於一襯墊 氧化膜605之上。N型摻雜物離子1043係利用該遮罩圖型 1044M作爲離子植入遮罩，在垂直相對於該基片700之入 射角0處予以植入，結果，形成了橫向及縱向重疊該等側 壁區742之底部區1044，藉此完成一第二N型井1040。 參閱第11圖，再利用一界定該第二N型井之底部區 1044之遮罩圖型i〇44M來植入P型摻雜物離子1119，藉此 形成一第二P型井1120。 根據此實施例，該第二N型井之該等側壁區742係透 過兩次或更多次在不同離子植入能量處之離子植入來形成Regulation I A7 B7 V. Description of the invention (/ &); Performed twice at different ion implantation energies. ^^ -------- U clothing II ί. 1 * 1 (Please read the precautions on the back before writing this page) Therefore, if you can fully overlap these side wall areas 742 and the The bottom region 844 allows the first well 610 and the second well 920 of the first conductivity type to be completely isolated and the side wall regions 742 can extend from the surface of the substrate to a depth such as D2, where the ion is implanted once When the bottom region 844 is formed, it is preferable to form the sidewall regions 742 through an ion implantation once and using an ion implantation energy equal or similar to the ion implantation energy used to form the bottom region 844. . At the same time, if necessary, two or more ion implantations can be performed. The third embodiment is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Refer to FIG. The sidewall regions 742 of the N-type well 730 and a second N-type well are formed through the same steps as those depicted in FIGS. 6 and 7 of the second embodiment. Next, a second N-type well is defined. The mask pattern 1044M in the bottom area of the well is formed on a pad oxide film 605. The N-type dopant ion 1043 uses the mask pattern 1044M as an ion implantation mask, and is implanted at an angle of incidence 0 perpendicular to the substrate 700. As a result, lateral and vertical overlaps of the sidewalls are formed. The bottom area 1044 of the area 742 completes a second N-well 1040. Referring to FIG. 11, a mask pattern i04M that defines a bottom region 1044 of the second N-type well is used to implant P-type dopant ions 1119, thereby forming a second P-type well 1120. According to this embodiment, the sidewall regions 742 of the second N-well are formed by ion implantation at two or more different ion implantation energies.
A7 B7 五、發明説明（/i) ，而該底部區1044係藉傾斜方向地植入摻雜物離子來形成 ，使得該等側壁區742與該底部區1〇44在一寬廣區域上垂 直地橫向地相互重疊。因此，可完全地電氣隔離該第一 P 型井610及該第二P型井1120。 同時，例如在該第一及第二實施例中，該第二N型井 之底部區1044及第二P型井1120係利用一遮罩圖型 1044M同時地形成，因而簡化了整個方法且及降低了製造 成本。 . 第四實施例 參閱第12圖，一界定第二N型井之底部區之例如光 阻圖型之遮罩圖型1244M係形成於一半導體基片1200之 上，該半導體基片具有一襯墊氧化物膜1205、一第一 P型 井210、一第一 N型井1230、及一第二N型井之諸側壁區 :接著，利用該遮罩圖型1244M作爲離子植入遮罩，藉此 形成該第二N型井之底部區1244。 此處，該遮罩圖型1244係形成以部分地或完全地暴露 出該半導體基片1200中形成至一預定深度之該等側壁區 1242，使得該底部區1244充分地重疊在該側壁區1241，結 果，完成一含有該等側壁區1242及該底部區1244之第二 N型井240。 接著，若該遮罩圖型1244M與該半導體基片1200間 之黏著力》較佳地，該光阻圖型1244M之烘乾係執行於一 範圍自180度至230度攝氏度之溫度處，特別地，大約200 度攝氏度，若該烘乾係執行於一極高之溫度處，則該光阻 尽紙張尺度適用中國國家榇準（ CNS ) A4規格（210X297公釐） - (請先閱讀背面之注意事項>^寫本頁) -裝' 訂 經濟郜智慧財產局員工消費合作社印製 圖型1244M會變形。 一用以形成諸間隔物之電介質膜（未圖示）係形成在具 有遮罩圖型1244M之半導體基片1200之整個表面上。 較佳地，利用一氧化物膜作爲電介質膜，同時，若其 中該遮罩圖型1244M係形成光阻時，假如該氧化物膜形成 於局溫處之時，則會發生一種收縮弄糊之光阻圖型。因此 ，較佳地，該氧化物膜形成於一低溫處。較佳地，使用電 漿增強之化學氣相沈澱法(PECVD)，藉該法可形成一氧化 物膜於一低溫處’較佳地，該沈澱法之溫度係設定在範圍 自攝氏180至250度。 接著，如第13圖中所示，異方向性蝕刻法係執行於具 有該電介質膜之半導體基片之整個表面上，而形成具有一 預定寬度w2於該遮罩圖型1244M之該等側壁處之諸間隔 物 1320S 〇 經濟部智慧財產局員工消費合作社印製 此處，該氧化物膜間隔物1320S ‘之寬度w2係根據該 遮罩圖型1244M之厚度及由該遮罩圖型1244M所暴露之半 導體基片之暴露寬度d。例如，當該遮罩圖型1244M之厚 度4500埃（A)而藉該遮罩圖型1244M所暴露之半導體基片 之暴露寬度d爲數百微米時，較佳地在該遮罩圖型1244M 上所形成之氧化物膜具有範圍自1000至4000埃之厚度； 接著，異方向性地蝕刻具有厚度範圍自1000至4000埃之 氧化物膜，及形成各具有寬度W2範圍自1000至4000埃 之氧化物膜間隔物1320S於該遮罩圖型1244M之該等側壁 處。 本紙張尺度適用中國國家標準（CNS > A4规格（210X297公釐） A7 _____B7_____ 五、發明説明（丨ί) 此處，該氧化物膜間隔物1320S之寬度W2應足以覆 蓋由該遮罩圖型1244Μ所暴露之第二Ν型井之側壁區1242 ，而僅暴露出該等側壁區1242間之半導體基片1200之區 〇 接著，利用該遮罩圖型1244Μ及該等間隔物1320S作 爲離子植入遮罩來植入Ρ型摻雜物離子1319而形成一第二 Ρ型井1320。 根據此實施例.，其中該等側壁區1242與該第二Ν型 井之底部區1244重疊之區的寬度wl可自動地由該等氧化 物膜間隔物1320S之寬度w2所確定。 換言之，在形成藉寬度w2來暴露該第二N型井之側 壁區1242而足以形成該氧化物膜間隔物於其內之遮罩圖型 1244M之後，N型摻雜物係植入以形成由一預定寬度wl來 …重疊該第二N型井之該等側壁區1242的第二N型井之底 部區1244 〇 同時，藉自行對齊之方式來形成該氧化物膜間隔物 1320S，該第二P型井1320可僅形成於該第二N型井1240 之內。所以，可有效地防止該第一 P型井1210與該第二P 型井1320間之短路。 同時，有如上述第一至第三實施例中，因爲該第二N 型井之底部區1244與該第二P型井320可同時地僅利用一 遮罩圖型1244M來形成，所以製程將簡化而製造成本會降 低。 第五實施例 本紙張尺度適用中國國家標準（CNS ) A4規格（210χ：297公釐） 五、發明説明（fu — -- 口 ^閱第14圖，一暴露其中將形成第二p型井142〇之 區之第—遮罩圖型142〇M係形成於—半導體基片14〇〇之 上’ j半導體基片1_係完全地由一襯墊氧化物膜刚 所覆^且具有一第一P型井141〇 , 一第一 N型井143〇及 一第一 N型井之諸側壁區1442。較佳地，該第一遮罩圖型 1420M係形成以完全地覆蓋該第二N型井之該等側壁區 1442。 接著，利用該第一遮罩圖型1420M爲離子植入遮罩來 植入P型摻雜物離子1419以形成該第二p型井142〇於該 半導體基片1400之區域內’其中該區域係由該第二N型井 之該等側壁區1424所界定。 參閱第15圖，在形成該第二p型井1420之後，係執 行一減少該第一遮罩圖型1420M之大小的步驟，當該第― 遮罩圖型1420M係形成光阻時，異方向性蝕刻係接著執行 於該光阻圖型1420M之上以減少其大小，該異方向蝕刻係 藉一電漿蝕刻法或利用一般淸除浮渣之方法來執行。 經濟部智慧財產局員工消費合作社印製 由虛線所表示之原來的第一遮罩圖型1420M係減少至 由實線所示之第二遮罩圖型1544M，該第二遮罩圖型 1544M界定一第二N型井之底部區，該第二遮罩圖型 1544M係形成使得該第二N型井之該等側壁區1442部分地 完全地暴露。 倘若其中該第二遮罩圖型1544M係作爲一第二光阻圖 型且係藉減少其爲一第一光阻圖型之第一遮罩圖型1420M 之大小來形成時，該等處理條件係調整使得該第二光阻圖 ---^__12____ 本紙張尺度適用中國國家標準（CNS )八4規格（210X297公酱) " A7 _____ B7_ 五、發明説明（q) 型之厚度爲大約2500埃。 接著，利用該第二遮罩圖型1544M作爲離子植入遮罩 來植入N型摻雜物離子1543而形成該第二N型井之底部 區1544。如第15圖中所示，該第一遮罩圖型1420M所減 少之寬度w2確定一重疊區之寬度wl，其中該第二N型井 之底部區1544重疊著該第二N型井之側壁區1542。 也就是P，在此實施例中，在形成一遮罩圖型1420M 且接著利用該遮罩.圖型1420M來形成該第二P型井1420 之後，該第二遮罩圖型1420M之側邊係減少而形成較寬於 第二P型井之第二N型井之底部區1544。因此，該第二N 型井1540係藉充分地重疊該第二N型井之底部區1544與 該第二N型井之側壁區1542而完成。所以，透過一簡化之 方法，可有效地防止該第P型井1410與該第二P型井1420 間之短路。 如上述，一第二導電型之第二井之底部區，其包封一 第一導電型之第二井且分離該第一導電型之第二井使得不 同之電壓可施加至該第一導電型之第一及第二井者，係利 用相同於第一導電型之第二井之遮罩來形成。同時，該第 二導電型之第二井之底部區係完全地連接於等側壁區。所 以，一具有增進特性之三重井結構可透過一簡化之方法予 以有效地形成。 〔元件符號〕 100 基片 110 第一 P型片 112 N型摻雜物區 114閘極氧化物膜 本紙張尺度適用中國國家標準（.CNS ) A.4規格（2ΐ〇χ297公釐） A7 ___ B7 五、發明説明（？ Π 116 閘極 118 Ρ型摻雜物區 120 第二Ρ型井 122 Ν型摻雜物區 124 閘極氧化物膜 126 閘極 128 Ρ型摻雜物區 130 第一 Ν型井 132 Ρ型摻雜物區 134 閘極氧化物膜 136 閘極 138 Ν型摻雜物區 140 第二Ν型井 142 側壁區 144 底部區. 144 ‘底部區 200 半導體基片 205 襯墊氧化物膜 209 Ρ型摻雜物離子 210 第一 Ρ型井 210Μ 第一遮罩圖型 330 第一 Ν型井 341 Ν型摻雜物區 342 側壁區 342Μ 第二遮罩圖型 440 第二Ν型井· 443 Ν型摻雜物離子 444 底部區 444Μ 第三遮罩圖型 519 Ρ型摻雜物離子 520 第二Ρ型井 600 半導體基片 605 襯墊氧化物膜 610 第一 Ρ型井 630 ‘第一Ν型井 641 Ν型摻雜物離子 642 側壁區 642 第一遮罩圖型 730 第一 Ν型井 730 ‘第一Ν型井 741 Ν型摻雜物離子 742 側壁區 742 ‘側壁區 840 第二Ν型井 843 Ν型摻雜物離子 844 底部區 844Μ :第二遮罩圖型 919 Ρ型摻雜物離子 本紙張尺度適用中國國家標準（CNS ) Α4規格（210 X 297公釐） A7 B7 五、發明説明uy) 920 第二P型井 1043 N型摻雜物離子 1044M 遮罩圖型 1120 第二P型井 1205襯墊氧化物膜 ' 1230 第一 N型井 1242 側壁區 1244M 遮罩圖型 1320 第二P型井 1400 半導體基片 1410 第一 P型井 1420 第二P型井 1424 第一 N型井 1442 側壁區 1542 側壁區 1544 底部區 1040 第二N型井 1044 底部區 1119 P型摻雜物離子 1200 半導體基片 1210 第一 p型井 1241 側壁區 1244 底部區 1319 P型摻雜物離子 1320S 氧化物膜間隔物 1405 襯墊氧化物膜 1419 P型摻雜物離子 1420M 第一遮罩圖型 1430 側壁區 1540 第二N型井 1543 N型摻雜物離子 1544M :第二遮罩圖型 經濟部智慧財產局員工消費合作社印製 _22 本紙張尺度適用中國國家標準（CNS ) A4規格（.210X297公釐）A7 B7 5. Description of the invention (/ i), and the bottom region 1044 is formed by implanting dopant ions in an oblique direction, so that the side wall regions 742 and the bottom region 1044 are perpendicular to each other over a wide area. Horizontally overlap each other. Therefore, the first P-well 610 and the second P-well 1120 can be completely electrically isolated. Meanwhile, for example, in the first and second embodiments, the bottom region 1044 of the second N-type well and the second P-type well 1120 are simultaneously formed using a mask pattern 1044M, thereby simplifying the entire method and and Reduced manufacturing costs. Fourth Embodiment Referring to FIG. 12, a mask pattern 1244M, such as a photoresist pattern, that defines the bottom area of the second N-type well is formed on a semiconductor substrate 1200. The semiconductor substrate has a substrate. Pad oxide film 1205, a first P-well 210, a first N-well 1230, and a side wall of a second N-well: then, using the mask pattern 1244M as an ion implantation mask, This forms a bottom region 1244 of the second N-type well. Here, the mask pattern 1244 is formed to partially or completely expose the sidewall regions 1242 formed to a predetermined depth in the semiconductor substrate 1200, so that the bottom region 1244 sufficiently overlaps the sidewall region 1241. As a result, a second N-type well 240 including the sidewall regions 1242 and the bottom region 1244 is completed. Then, if the adhesion between the mask pattern 1244M and the semiconductor substrate 1200 is better, the drying of the photoresist pattern 1244M is performed at a temperature ranging from 180 degrees to 230 degrees Celsius, especially Ground, about 200 degrees Celsius, if the drying is performed at a very high temperature, the photoresistance paper size applies to China National Standard (CNS) A4 (210X297 mm)-(Please read the back Precautions > ^ Write this page)-Binding 'Order Economy 郜 Intellectual Property Bureau Staff Consumer Cooperatives Printed Drawing 1244M will be deformed. A dielectric film (not shown) for forming the spacers is formed on the entire surface of the semiconductor substrate 1200 having a mask pattern 1244M. Preferably, an oxide film is used as the dielectric film. At the same time, if the mask pattern 1244M is used to form a photoresist, if the oxide film is formed at a local temperature, a kind of shrinkage will occur. Photoresistive pattern. Therefore, preferably, the oxide film is formed at a low temperature. Preferably, a plasma enhanced chemical vapor deposition method (PECVD) is used, by which an oxide film can be formed at a low temperature. 'Preferably, the temperature of the precipitation method is set in the range from 180 to 250 degrees Celsius. degree. Next, as shown in FIG. 13, the anisotropic etching method is performed on the entire surface of the semiconductor substrate having the dielectric film to form a predetermined width w2 at the sidewalls of the mask pattern 1244M. The spacers 1320S are printed here by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The width w2 of the oxide film spacers 1320S 'is based on the thickness of the mask pattern 1244M and exposed by the mask pattern 1244M. The exposed width d of the semiconductor substrate. For example, when the mask pattern 1244M has a thickness of 4500 angstroms (A) and the exposed width d of the semiconductor substrate exposed by the mask pattern 1244M is several hundred micrometers, it is preferable to use the mask pattern 1244M. The oxide film formed thereon has a thickness ranging from 1000 to 4000 angstroms. Next, the oxide film having a thickness ranging from 1000 to 4000 angstroms is etched anisotropically, and each having a width W2 ranging from 1000 to 4000 angstroms is formed. An oxide film spacer 1320S is at the sidewalls of the mask pattern 1244M. This paper size applies to Chinese national standards (CNS > A4 size (210X297 mm) A7 _____B7_____ V. Description of the invention (丨 ί) Here, the width W2 of the oxide film spacer 1320S should be sufficient to cover the pattern of the mask The sidewall region 1242 of the second N-type well exposed at 1244M, and only the region of the semiconductor substrate 1200 between the sidewall regions 1242 are exposed. Then, the mask pattern 1244M and the spacers 1320S are used as ion implantation. A mask is used to implant P-type dopant ions 1319 to form a second P-type well 1320. According to this embodiment, where the sidewall regions 1242 overlap the bottom region 1244 of the second N-type well The width wl can be automatically determined by the width w2 of the oxide film spacers 1320S. In other words, it is sufficient to form the oxide film spacers on the side wall region 1242 of the second N-type well formed by the width w2. After the inner mask pattern 1244M, the N-type dopant is implanted to form a predetermined width w1 ... forming a bottom region 1244 of the second N-type well that overlaps the sidewall regions 1242 of the second N-type well. At the same time, the oxygen is formed by self-alignment. The film spacer 1320S, the second P-type well 1320 may be formed only in the second N-type well 1240. Therefore, the interval between the first P-type well 1210 and the second P-type well 1320 can be effectively prevented At the same time, as in the first to third embodiments, the bottom region 1244 of the second N-type well and the second P-type well 320 can be formed using only a mask pattern 1244M at the same time, so the manufacturing process It will be simplified and the manufacturing cost will be reduced. Fifth embodiment The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210χ: 297 mm) 5. Description of the invention (fu — --- ^ See Figure 14 and expose it The first-mask pattern 14200M forming the area of the second p-type well 1420 is formed on-the semiconductor substrate 1400 '. The semiconductor substrate 1_ is completely composed of a pad oxide film. It has just been covered and has a first P-type well 1410, a first N-type well 1430, and sidewall regions 1442 of a first N-type well. Preferably, the first mask pattern 1420M is formed To completely cover the sidewall regions 1442 of the second N-type well. Next, the first mask pattern 1420M is used for ion implantation. Mask to implant P-type dopant ions 1419 to form the second p-type well 142 within the region of the semiconductor substrate 1400, where the region is defined by the sidewall regions 1424 of the second N-type well Referring to FIG. 15, after the second p-type well 1420 is formed, a step of reducing the size of the first mask pattern 1420M is performed. When the first-mask pattern 1420M forms a photoresist, different steps are performed. Directional etching is then performed on the photoresist pattern type 1420M to reduce its size. The non-directional etching is performed by a plasma etching method or by using a general method for removing scum. The Consumers Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the original first mask pattern 1420M indicated by the dotted line to reduce to the second mask pattern 1544M indicated by the solid line, which is defined by the first mask pattern 1544M In the bottom area of a second N-type well, the second mask pattern 1544M is formed so that the sidewall regions 1442 of the second N-type well are partially exposed. If the second mask pattern 1544M is used as a second photoresist pattern and is formed by reducing the size of the first mask pattern 1420M which is a first photoresist pattern, these processing conditions The adjustment is made to make the second photoresistance map --- ^ __ 12____ This paper size is applicable to the Chinese National Standard (CNS) 8-4 specifications (210X297 male sauce) " A7 _____ B7_ V. Description of the invention (q) type thickness is about 2500 Aye. Next, the second mask pattern 1544M is used as an ion implantation mask to implant N-type dopant ions 1543 to form a bottom region 1544 of the second N-type well. As shown in FIG. 15, the reduced width w2 of the first mask pattern 1420M determines the width w1 of an overlapping area, wherein the bottom area 1544 of the second N-type well overlaps the side wall of the second N-type well Area 1542. That is, P, in this embodiment, after forming a mask pattern 1420M and then using the mask. Pattern 1420M to form the second P-type well 1420, the side of the second mask pattern 1420M The system decreases to form a bottom region 1544 of the second N-type well that is wider than the second P-type well. Therefore, the second N-type well 1540 is completed by sufficiently overlapping the bottom region 1544 of the second N-type well and the side wall region 1542 of the second N-type well. Therefore, by a simplified method, a short circuit between the P-type well 1410 and the second P-type well 1420 can be effectively prevented. As mentioned above, the bottom area of a second well of the second conductivity type encloses a second well of the first conductivity type and separates the second well of the first conductivity type so that different voltages can be applied to the first conductivity The first and second wells of the type are formed by using the same mask as the second well of the first conductivity type. At the same time, the bottom region of the second well of the second conductivity type is completely connected to the equal sidewall region. Therefore, a triple well structure with enhanced characteristics can be effectively formed by a simplified method. [Element Symbol] 100 substrate 110 first P-type wafer 112 N-type dopant region 114 gate oxide film The paper size is applicable to Chinese National Standard (.CNS) A.4 specification (2ΐ × 297 mm) A7 ___ B7 V. Description of the invention (? Π 116 Gate 118 P-type dopant region 120 Second P-type well 122 N-type dopant region 124 Gate oxide film 126 Gate 128 P-type dopant region 130 First N-type well 132 P-type dopant region 134 Gate oxide film 136 Gate 138 N-type dopant region 140 Second N-type well 142 sidewall region 144 bottom region. 144 'bottom region 200 semiconductor substrate 205 pad Oxide film 209 P-type dopant ion 210 First P-type well 210M First mask pattern 330 First N-type well 341 N-type dopant region 342 Side wall region 342M Second mask pattern 440 Second N Type well · 443 N-type dopant ion 444 Bottom region 444M Third mask pattern 519 P-type dopant ion 520 Second P-type well 600 Semiconductor substrate 605 Liner oxide film 610 First P-type well 630 'First N-type well 641 N-type dopant ion 642 sidewall region 642 first mask pattern 730 One N-type well 730 'first N-type well 741 N-type dopant ion 742 sidewall region 742' sidewall region 840 second N-type well 843 N-type dopant ion 844 bottom region 844M: second mask pattern 919 P-type dopant ions The paper size is applicable to Chinese National Standard (CNS) A4 size (210 X 297 mm) A7 B7 V. Description of the invention uy) 920 Second P-type well 1043 N-type dopant ion 1044M Mask Type 1120 Second P-well 1205 liner oxide film '1230 First N-well 1242 Side wall area 1244M Mask pattern 1320 Second P-well 1400 Semiconductor substrate 1410 First P-well 1420 Second P-well 1424 First N-type well 1442 Side wall region 1542 Side wall region 1544 Bottom region 1040 Second N-type well 1044 Bottom region 1119 P-type dopant ion 1200 Semiconductor substrate 1210 First p-type well 1241 Side wall region 1244 Bottom region 1319 P-type Dopant ion 1320S oxide film spacer 1405 liner oxide film 1419 P-type dopant ion 1420M first mask pattern 1430 sidewall region 1540 second N-type well 1543 N-type dopant ion 1544M: second Mask Pattern Intellectual Property Bureau, Ministry of Economy _22 consumer cooperative work printed in this paper scale applicable Chinese National Standard (CNS) A4 size (.210X297 mm)