A7 B7 404013 4797pif.doc/002 五、發明說明（丨） 本發明爲主張於1998年7月13日申請之韓國專利 申請案第98-28912號，其內容全部於此處倂入參考。 本發明是有關於一種半導體的製造方法，且特別是有· 關於一種自動對準接觸窗的形成方法。 . 由於積體電路元件的積集度逐漸增加，因此，圖案尺 寸也愈來愈小。因此，使用的曝光光源波長也愈來愈短， 從 g-line (436nm)及 i-line (365nm)到波長的 KrF 雷射 (248nm)。然而，微影解析度卻沒有跟著積體電路的積_ 度而提高。尤其是在動態隨機存取記億體(DRAM)元件的 記憶胞排列區（cell array region)需要嚴謹的設計規範，因 此，任何輕微的對位偏差都不能接受。依此，採用自動對 準接觸窗的方法。 ^ 然而，自動對準接觸窗的技術還存在一些問題。因爲 微影解析度的限制，使得以自動對準接觸窗的製程在同一 平面上，形成位元線接觸窗以及形成儲存節點接觸窗變得 非常困難。也就是說，由於相鄰的圖案太接近，而無法獲 得想要的接觸窗圖案。比如說，相鄰的接觸窗可能連在一 起。 現在已揭露一種方法來克服上述的問題，其形成結合 位元線接觸窗及儲存節點接觸窗之放大的接觸窗圖案，並 利用光阻圖案及閘極線爲蝕刻罩幕。例如Y.Kohyama等人 所揭露的形成自動對準接觸窗的方法’ ”A Fully Printable Self-alligned and Planarized Stacked Capacitor DRAM Cell Technology for 1Gbit DRAM and Beyond”。 'Ml —I-1 — — — — — — — — ·1111111 ^ ».ΙΙΙΙΊ — ! : - * C請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 404013 A7 4797pif.doc,O02 __B/_ 五、發明說明（1) 第1圖及第2A、2B圖分別以上視圖及剖面圖圖解說 明了上述文獻資料之自動對準接觸窗技術。在第1圖中， 在半導體基底上定義條形主動區11。閘極線與該條形主動 區正交。由氧化層組成的層間介電層18覆蓋閘極線。自 動對準接觸窗罩幕20(即光阻圖案）相同於主動區11，但位 置則沿閘極方向位移半個間距。 第2A圖顯示，在半導體基底（未顯示）上形成元件隔 離區10。複數個閘極線形成於含隔離區10之半導體基底 材上。閘極線由多晶矽層12、矽化金屬層（W.Si)13、氮化 石夕（SiN)硬罩幕層1 4、以及間隙壁1 6組成。層間介電層1 8 沉積在該結果結構上，並利用化學機械硏磨法（CMP)加以 平坦化。在層間介電層18上形成自動對準接觸窗罩幕20。 利用自動對準接觸窗罩幕20，蝕刻層間介電層18至 閘極線間的半導體基底以形成複數個自動對準接觸窗開口 22。假如氧化層18相對於氮化矽（SiN)硬罩幕層14以及間 隙壁16的蝕刻選擇比不佳，則氮化矽（SiN)硬罩幕層14及 間隙壁16會產生不欲發生的蝕刻。特別是閘極12及13 上方的_氮化砍層.變薄（如標記23)，此導致在後續形成之接 觸窗22的塡充材料與閘極12及13間發生漏電流（leakage current) ° 爲解決這個問題，可形成非常厚之氮化矽硬罩幕。然 而，由於增厚氮化矽硬罩幕層，之後的層間介電層沉積將 變得困難，此歸因於閘極電極構形之高的高寬比（aspect ratio)。空孔（void)可能會在層間介電層內形成，而且此空 5 本纸張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） , n ----------------------訂-----^---- r -- (請先閱，讀背面之注意事項再填寫本頁) 404013 4797pif.doc/002 A7 B7 ---- 五、發明說明（：？） 孔可能會在於記憶胞（cel 1)間造成橋接。 本發明爲基於前述問題完成’本發明的 A的自的是在提供 一種形成自動對準接觸窗的方法’該方法的5 叫在自動對進培 觸窗的蝕刻過程中，使氮化矽層免於被蝕刻。. 爲了要保護氮化矽硬罩幕層及間隙壁不被軸刻，可以 沉積多晶矽層在其上。因爲多晶矽層對於後續形成的氧化 層之蝕刻選擇比優於氮化矽硬罩幕層對於後續形成的氧化 層之蝕刻選擇比。因此’在自動對準接觸窗的蝕刻過程中， 氣化砂硬罩幕層未被独刻’而且防止閘極電極與後續形成 的自動對準接觸窗墊間之漏電流。此外，因爲多晶砂層對 於氧化層具有較佳的選擇比，所以多晶矽層形成較薄。因 此’氮化砂硬罩幕層的厚度可以減少，進而降低整個閘極 電極構形的高度。 爲達成本發明上述及其他優點與目的，在半導體基底 上形成一元件隔離區。接著，在此結果結構上形成閘極氧 化層’以使後續形成的閘極構形與半導體基底絕緣。接著， 依序在閘極氧化層上形成閘極層'第一閘極罩幕層、及第 二閘極罩幕層。使用閘極電極的圖案化光阻層，蝕刻堆疊 層之選定部份以形成複數個閘極電極構形。在每一個閘極 構形的雙側壁形成側壁間隙壁。 . 沉積由氧化層所組成的絕緣層以覆蓋間隔的閘極構 形。使用自動對準罩幕圖案，蝕刻選定部分的絕緣層以形 成自動對準接觸窗開口，該自動對準接觸窗開P曝露出閘 極电極構形間的部份半導體基底。在這自動對準式的蝕刻 (請先閱1*·背面之注意事項再填寫本頁) I I I----—訂--------- 經濟部智慧財產局員工消費合作社印製 卜紙張尺度適用家標準（CNS〉A4規格⑵Q x 297公楚r A7 404013 4797pif、.d〇c/002 五、發明說明（f) 過程中，第二罩幕層保護其下的第一罩幕層。在結果的接 觸窗開口內塡入導體材料，如摻雜化的多晶砂，而且平坦 化以形成自動對準接觸窗墊（self-aligned contact pads；)。 更特別地’閘極電極層的組成是多晶砂層與例如是砂 化鎢的矽化金屬層的堆疊層，厚度分別約1000埃。第一 罩幕層的組成是一氮化砂層，厚度約500至1000埃。爲 了保護第一罩幕層。第二罩幕層是由一種材料組成，該材 料比氮化矽層對絕緣層（氧化物）更具有較佳的蝕刻選擇比 以保護氮化矽層。例如，可以形成多晶矽層。多晶矽層被 形成較薄由於多晶矽層具有佳的蝕刻選擇比。因此，氮化 砂層可以形成較薄，比較於上述的傳統方法，其形成的氮 化矽層厚度至少要15〇〇埃。側壁間隙壁的組成是氮化矽 層，其厚度約500埃。 興化絕緣層的丨几積是局街度電繁（high density plasma. HDP)儀。在目前的蝕刻下，高密度電漿沉積儀有沉積出需 求層的好處。因此，結果氧化層具有優良的塡充特性，而 沒有任何空孔形成。 …一另外，在第二罩幕層上進—步形成一第三罩幕層。此 第二罩幕層的組成是咼溫氧化層（high temperature HT〇)。這局溫氧化層對於矽化鎢層有佳的選擇比。在這 例子裡，閘極電極構形的形成如下。利用閘極圖案化光阻 =，蝕刻第三罩幕層、第二罩幕層、及第一罩幕層。利用 政圖案化高溫氧化層爲罩幕，蝕刻矽化鎢層及多晶矽層以 开^成閘極構形。 (請先閱讀背®·之注意事項再填寫本頁) i 裝--------訂-:—! —----At 經濟部智慧財產局員工消費合作社印製 7 經濟部智慧財產局員工消費合作社印製 404013 A7 4797pii、.cioc/002 β7 五、發明說明（夕） 在自動對準接觸窗的蝕刻過程中，爲了保護半導體基 底，在氧化絕緣層形成前，可先沉積一厚約1Ό0埃的氮化 砂層。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖示之簡單說明： \第1圖係一半導體基底的俯視平面圖； 、第2Α及2Β圖係第1圖中沿Α-Α’線的剖面圖； 、、第3Α至3Η圖係一半導體的剖面圖，該圖顯示根據本發 明的自動對準接觸窗之製作步驟。 圖示標記說明： 10、100 :元件隔離區 11:主動區 12、 102 :多晶矽層 13、 103 :矽化金屬層 14、 104 :氮化矽層（第一閘極罩幕層） 1 6、1 12 :間隙壁 . 1 8、1 1 4 :氧化絕緣層 20、116 :自動對準接觸窗罩幕 22、118 :自動對準接觸窗 23 :遭蝕刻的氮化矽層及間隙壁 106 :高溫氧化層 108 :光阻圖案 8 本紙張尺度適用申國國家標準（CNS)A4規格（210 x 297公釐） (請先閲讀背®-之注意事項再填寫本頁) ' ---------訂··-------- 經濟部智慧財產局員工消費合作社印製 404013 Δ7 Α7 4797pir.doc/002 β7 五、發明說明（) 110 :閘極構形 120 :接觸窗墊 實施例： 本發明根據附圖而被更完整地描述，該圖顯示本發明 的較佳實施例。然而，本發明可以用不同方式實施，而不 應該限制在本實施例的詮釋中。再者，提供此實施例是爲 了讓本揭露可以完備，並可以完全地傳達本發明的技藝。 在附圖中，爲了詮釋，其層與區域厚度是被誇大的。有些 描述也應該被瞭解，當描述有一層在另一層或基底之上表 示有一層在另一層或基底之正上方，或者中間可能有隔 層。相反的，當描述有一層在另一組成上表示中間沒有隔 層。另外，在此描述及圖解的每一實施例也包括其互補式 導電型。 第3A至3H圖係一半導體的剖面圖，該圖顯示根據本 發明的自動對準接觸窗之製作步驟。第3A至3 B圖是沿 著位元線而類似於第2A及2B圖的剖面圖。參照第3A 圖顯示，在一半導體基底的預定區域上形成元件隔離區100 以定義出主動及非主動區域。元件隔離區100是利用鈾刻 半導體基底的製程至一預定深度以形成一渠溝(trench)，在 渠溝中塡入一絕緣材料並平坦化。傳統的矽區域氧化技術 可以被採用。進行雜質離子植入法（impurity ion implantation)形成一井區（well region)及調整電晶體的起始 電壓（threshold voltage). 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注音？事項再填寫本頁) --裳·-------.訂..--------^ 404013 4797pif.doc/002 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（q ) 在閘極氧化層（未顯示）形成之後’依序在閘極氧化層上 形成閘極層102及103、第一閘極罩幕層104、第二閘極 罩幕層105及可選擇製作的（0Ptional)高溫氧化層1〇6。閘 極電極層102和103的組成是多晶砂層102與例如是矽化 鎢的矽化金屬層103。比如，各層的厚度約100〇埃。第一 閘極罩幕層104的組成是氮化矽層，該層對於後續形成的 層間絕緣層具有蝕刻選擇比。傳統上’氮化矽硬罩幕層的 形成厚度至少約1500埃。然而’根據本發明’第一氮化 矽硬罩幕層104的形成比傳統的方法薄，因爲有第二硬罩 幕層105的存在，而該層對氧化絕緣層的蝕刻選擇比優於 第一硬罩幕104。此外，第一閘極罩幕層104也是後續的 接觸窗墊平坦化過程之鈾刻中止層（etching stopper)。因 此，第一閘極罩幕層104的厚度可以根據後續平坦化的均 勻度（uniformity)，來調整，比如約爲500至1〇〇〇埃的厚 度。 第二閘極罩幕層10 5用來保護自動對準蝕刻過程中其 下之第一閘極罩幕層104。比如，該第二閘極罩幕層105 可由多晶矽組成，厚度約300至500埃。在高溫氧化層106 上形成儲存節點光阻圖案108。該高溫氧化層106是用來 狻得對於矽化鎢103充分的飽刻選擇比。比如，該高溫氧 化層1〇6形成約爲300到500埃的厚度。 在第3B圖中，利用光阻圖案1〇8，蝕刻高溫氧化層1〇6、 第二閘極罩幕層105及第一極罩幕層1〇4。之後，用傳統 的燒燼(ashing)及剝離(stripping)法移除光阻圖案1〇8。 10 本紙張尺㈣时關家辟(CNS)A4 ^ (210 X 297 請 先 閱. 讀 背 再 填I 5裝 本 · 頁 -訂 % A7 B7 404013 4797pit'.doc/002 五、發明說明（i) 利用圖案化的高溫氧化層106 '第二閘極罩幕層105及 第一閘極罩幕層104 ’触刻砂化鎢103及多晶砂1〇2而形 成複數個閘極構形Π0，顯示在第3C圖中。.接著，雜質 離子植入閘極電極構形Π0間的半導體基底。 在第3D圖中，在閘極電極構形110雙側壁形成絕緣間 隙壁該絕緣間隙壁112的組成是氮化矽。該絕緣間 隙壁112是利用沉積氮化矽層至約5〇0埃厚，之後再回蝕 而成。在回蝕的過程中，高溫氧化層106也同時被移除。 爲了在自動對準式的蝕刻過程中保護半導體基底，在 結果結構上沉積一厚約1 〇〇埃的氮化砂層。 在第3 E圖中，由氧化層組成的層間絕緣層114被沉積 去塡充閘極電極構形110間的間隙。爲了避免空孔的形成， 高密度電漿沉積儀被採用來沉積層間絕緣層114。高密度 電漿沉積儀有在目前的蝕刻下沉積出需求層的優點，藉以 獲得佳的沉積輪廓。 另一個避免空孔的方法是降低閘極電極構形no的高 度。根據本發明，第一閘極罩幕層形成較薄，因爲對氧化 絕緣層具較佳蝕刻選擇比的第二閘極罩幕層的存在。 以第二罩幕層105爲終止點，利用化學機械硏磨法將 層間絕緣層114平坦化。而超過閘極電極構形110之上的 層間絕緣層114之厚度可由時間蝕刻法（time-etching)控 制。 在第3F圖中，在結果結構上形成自動對準接觸窗圖案 1 16。以自動對準接觸窗罩幕116及第二罩幕層105爲罩 (請先閱讀背面之注意事項再填寫本頁) I -----I--訂-----— II 1 . 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公t ) A7 B7 404013 ，4797pii、.doc/002 五、發明說明（1 ) 卜 幕，蝕刻層間絕緣層114及氮化矽層的選定部份以形成複 數個自動對準接觸窗118，該複數個自動對準接觸窗丨18 曝露出顯示於第3G圖中之間隙壁間的基底。因爲組成爲 多晶矽的第二罩幕層1 05對組成爲氧化層的層間絕緣層有 佳的蝕刻選擇比，所以第一罩幕層及間隙壁U2不會 被蝕刻。 · 接著，移除自動對準接觸窗圖案116，而在自動對準接 觸窗開口 118中沉積入導電材料。比如，可沉積厚度約4000 至6000埃的摻雜化的多晶矽。在第3H圖顯示，利用第一 罩幕層1〇4爲蝕刻中止層’將摻雜化的多晶矽及第二罩幕 層105平坦化以形成接觸窗墊U0。平面化是利用化學機 械硏磨技術，而使用的硏漿(slurry)對於氮化矽具有蝕刻選 擇比。 ^ - < - — I! I--I I 11 I I I ' — — — — — I— --— — — — — 1 (請先閱，讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（cns)a4規^A7 B7 404013 4797pif.doc / 002 V. Description of the Invention (丨) The present invention is a Korean Patent Application No. 98-28912 filed on July 13, 1998, the entire contents of which are incorporated herein by reference. The present invention relates to a method for manufacturing a semiconductor, and more particularly, to a method for forming an automatic alignment contact window. As the integration degree of integrated circuit components is gradually increasing, the pattern size is also getting smaller and smaller. Therefore, the wavelength of the exposure light source used is getting shorter and shorter, from g-line (436nm) and i-line (365nm) to the wavelength of KrF laser (248nm). However, the lithographic resolution does not increase with the product of the integrated circuit. Especially in the dynamic random access memory (DRAM) device memory cell array region (cell array region) requires rigorous design specifications, therefore, any slight misalignment is unacceptable. Based on this, the method of automatically aligning the contact window is adopted. ^ However, there are still some problems with the technique of automatic contact window alignment. Due to the limitation of the lithographic resolution, it is very difficult to form the bit line contact window and the storage node contact window on the same plane with the process of automatically aligning the contact windows. That is, because adjacent patterns are too close, the desired contact window pattern cannot be obtained. For example, adjacent contact windows may be connected together. A method has been disclosed to overcome the above problems, which forms an enlarged contact window pattern combining a bit line contact window and a storage node contact window, and uses a photoresist pattern and a gate line as an etching mask. For example, the method for forming an auto-aligned contact window disclosed by Y. Kohyama et al. '"A Fully Printable Self-alligned and Planarized Stacked Capacitor DRAM Cell Technology for 1Gbit DRAM and Beyond". 'Ml —I-1 — — — — — — — — · · 1111111 ^ ».ΙΙΙΙΊ —!:-* CPlease read the notes on the back before filling out this page) Printed on paper by Employees’ Cooperatives, Bureau of Intellectual Property, Ministry of Economic Affairs Standards are applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 404013 A7 4797pif.doc, O02 __B / _ 5. Description of the invention (1) Figure 1 and 2A Figures 2 and 2B respectively illustrate the above-mentioned documents and the technology of automatic alignment of the contact window. In FIG. 1, a stripe active region 11 is defined on a semiconductor substrate. The gate line is orthogonal to the strip active area. An interlayer dielectric layer 18 composed of an oxide layer covers the gate lines. The auto-alignment contact window screen 20 (ie, the photoresist pattern) is the same as the active area 11, but the position is shifted by half a distance along the gate direction. FIG. 2A shows that an element isolation region 10 is formed on a semiconductor substrate (not shown). A plurality of gate lines are formed on a semiconductor substrate including the isolation region 10. The gate line is composed of a polycrystalline silicon layer 12, a silicided metal layer (W.Si) 13, a silicon nitride (SiN) hard cover curtain layer 14, and a spacer 16. An interlayer dielectric layer 18 is deposited on the resulting structure and planarized by chemical mechanical honing (CMP). An auto-aligned contact window mask 20 is formed on the interlayer dielectric layer 18. By using the automatic alignment contact window curtain 20, the semiconductor substrate between the interlayer dielectric layer 18 and the gate lines is etched to form a plurality of automatic alignment contact window openings 22. If the etching selection ratio of the oxide layer 18 relative to the silicon nitride (SiN) hard cover curtain layer 14 and the spacer 16 is not good, the silicon nitride (SiN) hard cover curtain layer 14 and the spacer 16 will produce unwanted effects. Etching. In particular, the _nitride cut layer above the gates 12 and 13 becomes thin (such as mark 23), which results in leakage current between the filling material of the contact window 22 and the gates 12 and 13 which are formed later. ° To solve this problem, a very thick silicon nitride hard mask can be formed. However, due to the thickened silicon nitride hard mask layer, subsequent interlayer dielectric layer deposition will become difficult due to the high aspect ratio of the gate electrode configuration. A void may be formed in the interlayer dielectric layer, and this empty 5 paper size applies to the Chinese National Standard (CNS) A4 specification (210 x 297 mm), n --------- ------------- Order ----- ^ ---- r-(Please read first, read the notes on the back before filling in this page) 404013 4797pif.doc / 002 A7 B7 ---- 5. Explanation of the invention (:?) The hole may cause a bridge between the memory cells (cel 1). The present invention is based on the foregoing problem. The invention of A of the present invention is to provide a method for forming an auto-aligned contact window. The method 5 is called the process of making a silicon nitride layer during the etching process of an automatic counter-contact touch window. Free from being etched. In order to protect the silicon nitride hard cover curtain layer and the spacer wall from being carved by a shaft, a polycrystalline silicon layer can be deposited thereon. This is because the polycrystalline silicon layer has a better etching selection ratio for the subsequent oxide layer than the silicon nitride hard mask curtain layer for the subsequent oxide layer. Therefore, during the etching process of the auto-aligned contact window, the hardened gas mask layer is not etched alone, and the leakage current between the gate electrode and the subsequently formed auto-aligned contact window pad is prevented. In addition, because the polycrystalline sand layer has a better selection ratio to the oxide layer, the polycrystalline silicon layer is formed thinner. Therefore, the thickness of the 'nitrided sand hard mask' layer can be reduced, thereby reducing the height of the entire gate electrode configuration. To achieve the above and other advantages and objectives of the present invention, an element isolation region is formed on a semiconductor substrate. Next, a gate oxide layer 'is formed on the resulting structure to insulate the gate structure formed later from the semiconductor substrate. Next, a gate layer, a first gate cover curtain layer, and a second gate cover curtain layer are sequentially formed on the gate oxide layer. Using a patterned photoresist layer of the gate electrode, a selected portion of the stacked layer is etched to form a plurality of gate electrode configurations. Side wall spacers are formed on the double side walls of each gate configuration. Deposit an insulating layer composed of an oxide layer to cover the spaced gate configuration. Using the auto-aligned mask pattern, the selected portion of the insulating layer is etched to form an auto-aligned contact window opening, which exposes a portion of the semiconductor substrate between the gate electrode configurations. In this automatic alignment type etching (please read 1 * · Notes on the back before filling this page) II I -------- Order --------- Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs Standards for papermaking are applicable to household standards (CNS> A4 size ⑵Q x 297) Chu A7 404013 4797pif, .d〇c / 002 5. Description of the invention (f) During the process, the second cover protects the first cover under it Curtain layer. A conductive material, such as doped polycrystalline sand, is inserted into the resulting contact window opening, and flattened to form self-aligned contact pads; more specifically, the gate The composition of the electrode layer is a stacked layer of a polycrystalline sand layer and a silicided metal layer such as sanded tungsten, each having a thickness of about 1000 angstroms. The composition of the first cover layer is a nitrided sand layer, about 500 to 1000 angstroms. The first mask layer. The second mask layer is composed of a material that has a better etching selectivity than the silicon nitride layer to the insulating layer (oxide) to protect the silicon nitride layer. For example, it can be formed Polycrystalline silicon layer. The polycrystalline silicon layer is formed thinner because the polycrystalline silicon layer has good etching options Therefore, the nitrided sand layer can be formed thinner than the conventional method described above. The thickness of the formed silicon nitride layer is at least 1 500 angstroms. The composition of the sidewall spacer is a silicon nitride layer with a thickness of about 500 angstroms. Xinghua's insulation layer is a high-density plasma (HDP) instrument. Under the current etching, the high-density plasma deposition instrument has the advantage of depositing the required layer. Therefore, the oxide layer has excellent results. Filling characteristics without any void formation.… In addition, a second covering layer is further formed on the second covering layer. The composition of this second covering layer is a high temperature oxide layer. HT〇). This local temperature oxidation layer has a good selection ratio for the tungsten silicide layer. In this example, the gate electrode configuration is formed as follows. The gate patterned photoresist is used to etch the third mask layer, the first The second cover layer and the first cover layer. The patterned high-temperature oxide layer is used as the cover, and the tungsten silicide layer and the polycrystalline silicon layer are etched to form the gate structure. (Fill in this page) i Install -------- Order-:-! —---- At Economy Printed by the Intellectual Property Bureau employee consumer cooperative 7 Printed by the Ministry of Economic Affairs Intellectual Property Bureau employee consumer cooperative 404013 A7 4797pii, .cioc / 002 β7 V. Description of the Invention (Even) In order to protect the semiconductor substrate during the automatic alignment of the contact window during the etching process Before the formation of the oxide insulating layer, a nitrided sand layer having a thickness of about 1 .0 angstrom may be deposited. In order to make the above and other objects, features, and advantages of the present invention more obvious and understandable, a preferred embodiment is given below, In conjunction with the attached drawings, the detailed description is as follows: Brief description of the figure: Figure 1 is a top plan view of a semiconductor substrate; Figures 2A and 2B are cross-sectional views along line A-A 'in Figure 1 Figures 3A to 3D are cross-sectional views of a semiconductor, which shows the manufacturing steps of the automatic alignment contact window according to the present invention. Description of icons: 10, 100: element isolation area 11: active area 12, 102: polycrystalline silicon layer 13, 103: silicided metal layer 14, 104: silicon nitride layer (first gate cover curtain layer) 1 6, 1 12: spacer wall. 1 8, 1 1 4: oxidized insulation layer 20, 116: automatic alignment of contact window cover curtain 22, 118: automatic alignment of contact window 23: etched silicon nitride layer and spacer 106: high temperature Oxide layer 108: Photoresist pattern 8 This paper size applies to China National Standard (CNS) A4 specification (210 x 297 mm) (Please read the precautions on Back®- before filling this page) '' ------ --- Order ·· -------- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 404013 Δ7 Α7 4797pir.doc / 002 β7 V. Description of the invention () 110: Gate configuration 120: Contact window pad Examples: The invention is described more fully with reference to the accompanying drawings, which show a preferred embodiment of the invention. However, the present invention can be implemented in different ways and should not be limited to the interpretation of this embodiment. Furthermore, this embodiment is provided in order to make the present disclosure complete and to fully convey the technology of the present invention. In the drawings, the thicknesses of layers and regions are exaggerated for explanation. Some descriptions should also be understood, when describing a layer above another layer or substrate means that one layer is directly above another layer or substrate, or there may be a spacer in the middle. In contrast, when one layer is described on the other, it means that there is no middle layer. In addition, each embodiment described and illustrated herein also includes its complementary conductivity type. Figures 3A to 3H are cross-sectional views of a semiconductor, which shows the manufacturing steps of an automatic alignment contact window according to the present invention. 3A to 3B are cross-sectional views similar to FIGS. 2A and 2B along the bit line. Referring to FIG. 3A, it is shown that an element isolation region 100 is formed on a predetermined region of a semiconductor substrate to define active and inactive regions. The element isolation region 100 is a process in which a semiconductor substrate is engraved to a predetermined depth to form a trench, and an insulating material is inserted into the trench and planarized. Traditional silicon area oxidation techniques can be used. Impurity ion implantation is used to form a well region and adjust the threshold voltage of the transistor. This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ) (Please read the phonetic on the back? Matters before filling out this page) --Shang · -------. Order ..-------- ^ 404013 4797pif.doc / 002 A7 B7 Ministry of Economy Wisdom Printed by the Consumer Cooperative of the Property Bureau V. Invention Description (q) After the gate oxide layer (not shown) is formed, the gate layers 102 and 103 and the first gate cover curtain layer 104 are sequentially formed on the gate oxide layer , The second gate shield curtain layer 105, and optionally (0Ptional) high-temperature oxide layer 106. The gate electrode layers 102 and 103 are composed of a polycrystalline sand layer 102 and a silicide metal layer 103 such as tungsten silicide. For example, the thickness of each layer is about 100 Angstroms. The composition of the first gate shield curtain layer 104 is a silicon nitride layer, which has an etching selectivity for an interlayer insulating layer to be formed later. Traditionally, the 'silicon nitride hard mask' is formed to a thickness of at least about 1500 angstroms. However, according to the present invention, the formation of the first silicon nitride hard mask layer 104 is thinner than the conventional method because of the existence of the second hard mask layer 105, and the etching selectivity ratio of this layer to the oxide insulating layer is better than that of the first method. A hard hood curtain 104. In addition, the first gate shield curtain layer 104 is also a etch stopper for subsequent contact pad flattening processes. Therefore, the thickness of the first gate shield curtain layer 104 can be adjusted according to the uniformity of subsequent planarization, such as a thickness of about 500 to 1000 angstroms. The second gate cover curtain layer 105 is used to protect the first gate cover curtain layer 104 under the auto-alignment etching process. For example, the second gate shield layer 105 may be made of polycrystalline silicon and has a thickness of about 300 to 500 angstroms. A storage node photoresist pattern 108 is formed on the high-temperature oxide layer 106. The high-temperature oxide layer 106 is used to obtain a sufficient saturation selectivity for the tungsten silicide 103. For example, the high-temperature oxidation layer 10 is formed to a thickness of about 300 to 500 angstroms. In FIG. 3B, the photoresist pattern 108 is used to etch the high-temperature oxide layer 106, the second gate shield layer 105, and the first gate shield layer 104. After that, the photoresist pattern 108 is removed by a conventional ashing and stripping method. 10 copies of this paper, Guan Jia Pi (CNS) A4 ^ (210 X 297 Please read first. Read the back and fill in I 5 Packs · Pages-Order% A7 B7 404013 4797pit'.doc / 002 5. Description of the invention (i ) The patterned high-temperature oxide layer 106 'the second gate cover curtain layer 105 and the first gate cover curtain layer 104' is used to etch the tungsten tungsten 103 and polycrystalline sand 102 to form a plurality of gate configurations. , Shown in FIG. 3C .. Next, impurity ions are implanted into the semiconductor substrate between the gate electrode configurations Π0. In FIG. 3D, an insulating gap wall 112 is formed on both sides of the gate electrode configuration 110. The composition is silicon nitride. The insulating spacer 112 is formed by depositing a silicon nitride layer to a thickness of about 5000 angstroms, and then etched back. During the etchback process, the high-temperature oxide layer 106 is also removed at the same time. In order to protect the semiconductor substrate during the auto-aligned etching process, a nitride sand layer having a thickness of about 100 angstroms is deposited on the resulting structure. In Fig. 3E, an interlayer insulating layer 114 composed of an oxide layer is deposited. Remove the gap between the gate electrode configuration 110. In order to avoid the formation of voids, a high-density plasma deposition instrument was used. Used to deposit the interlayer insulating layer 114. The high-density plasma deposition apparatus has the advantage of depositing the required layer under the current etching, so as to obtain a good deposition profile. Another method to avoid voids is to reduce the gate electrode configuration. Height. According to the present invention, the first gate cover curtain layer is formed thinner because of the existence of the second gate cover curtain layer which has a better etching selection ratio for the oxide insulating layer. With the second cover curtain layer 105 as the termination point, The chemical-mechanical honing method is used to planarize the interlayer insulating layer 114. The thickness of the interlayer insulating layer 114 exceeding the gate electrode configuration 110 can be controlled by time-etching. In FIG. 3F, in the result, The structure forms an auto-aligned contact window pattern 1 16. The auto-aligned contact window cover 116 and the second cover layer 105 are used as the cover (please read the precautions on the back before filling this page) I ----- I --Order ------ II 1. The paper size printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs applies to the Chinese National Standard (CNS) A4 (210 X 297 g) A7 B7 404013, 4797pii, .doc / 002 V. Description of the invention (1) The curtain, the etching layer insulation The selected portions of the layer 114 and the silicon nitride layer form a plurality of self-aligned contact windows 118, which expose the substrate between the gap walls shown in Figure 3G. Because the composition is The second mask layer 105 of polycrystalline silicon has a good etching selection ratio to the interlayer insulating layer composed of an oxide layer, so the first mask layer and the spacer U2 will not be etched. · Then, the automatic alignment contact window is removed. Pattern 116, and a conductive material is deposited in the auto-aligned contact window opening 118. For example, doped polycrystalline silicon can be deposited to a thickness of about 4000 to 6000 Angstroms. Figure 3H shows that the doped polycrystalline silicon and the second mask layer 105 are planarized by using the first mask layer 104 as an etching stop layer 'to form a contact window pad U0. The planarization uses chemical mechanical honing techniques, and the slurry used has an etching selectivity for silicon nitride. ^-<-— I! I--II 11 III '— — — — — — — — — — — — — 1 (Please read, read the notes on the back before filling out this page) Intellectual Property Bureau, Ministry of Economic Affairs The paper size printed by the employee consumer cooperative is applicable to the Chinese National Standard (cns) a4 ^