TW463069B - Image display device and method - Google Patents

Abstract

Provided is an image display device and method including a display board 101 with regular ratio of width and height; a horizontal scan circuit 201-1, ... 201-4 of signal voltage of every display pixel which inputs every corresponding horizontal pixel lines according to the clock signal of the picture signal that is input; a vertical scan circuit 301 for selecting horizontal pixel lines; and a control circuit 401 for providing the clock signal to the horizontal scan circuit 201-1, ... 201-4. The control circuit 401 includes a frequency division unit which uses the first and second ratio to divide the reference clock signal; the output for selecting the reference clock signal combined during the horizontal scanning and divided by the first ratio; and an image display device 1 of selection unit from the frequency division unit divided by the second ratio.

Description

46306 9 Central Standard of the Ministry of Economic Affairs, Printing of Cooperative Consumer Cooperatives A7 B7 V. Description of the invention (]) [Technical Field to which the Invention belongs] The present invention relates to the ratio (rate) of horizontal X and vertical Y to be input for sequential sampling, That is, an image display method of an image signal in an effective area of an aspect ratio X / Y to perform image display. [Knowledge technology] The display device, which represents a liquid crystal display device, effectively uses its characteristics of thinness, light weight, and low power consumption, and is used as a display device in various fields such as a personal computer or a word processor, and as a television. Or the display device of the car guide (navigation) system, and also used as a projection type display device. Among them, the active matrix liquid crystal display device formed by electrically connecting switching (switching) elements to each display pixel can be performed in a grand manner because it can realize a good display image without crosstalk between adjacent pixels. Research and development ... In particular, in recent years, display equipment with an effective aspect ratio of 4/3 has gradually shifted towards horizontal scanning lines with aspect ratios of 16/9 that can visually recognize large screens. Display device with extended effective display area. In a liquid crystal display device having an effective display area with an aspect ratio of 16/9, several methods are known when displaying an image signal having image information with an aspect ratio of 4/3. For example, the video signal Video with an aspect ratio of 4/3 shown in Figure 13 is sequentially sampled across the aspect ratio according to a predetermined sampling clock. The effective display of the entire II domain of 6/9 is displayed as shown in the figure. (B) The method shown in this paper is in accordance with the Chinese National Standard (CNS) A4 (210X29 * 7mm). {Please read the two notes before filling this page} Order 4 63 06 9 Central Ministry of Economic Affairs A7 B7 printed by MOU employee consumer cooperative V. Invention Description (2). According to this method, although no special circuit structure is needed, the aspect ratio of the video signal Video with an aspect ratio of 4/3 cannot be faithfully reproduced, and it will become the horizontal scanning line direction as shown in (b). Extending (stretching) the image. As other methods, as shown in (c) or (d), the effective display area with an aspect ratio of 16/9 is divided into a display area with an aspect ratio of 4/9, and the aspect ratio is 12 / 9 (4/3) display r * area * and display the video signal Video with the image information of the aspect ratio 4/3 in the display area of the aspect ratio 12/9 (4/3). However, in this case, in the sampling period corresponding to the display area of 12/9 (4/3), if it is the NTS C method, at least for the horizontal scanning period (1 H), 0.8 H is required, so corresponding The sampling period in the display area with an aspect ratio of 4/9 becomes 0.2H or less. For this reason, previously, image processing technology such as frame (frame) memory was used to sequentially sample and display according to the image signal of the image processing performed in advance. For this reason, it was not possible to reduce the cost of the device. . [Problems to be Solved by the Invention] As to the problems described above, for example, a method disclosed in Japanese Patent Laid-Open No. 8-289232 has been proposed. It is shown in Fig. 13 (c) or 13 (d). The effective area (area) of the aspect ratio 16/9 is divided into the first display area and width of the aspect ratio 12/9 (4/3). The second display area with an aspect ratio of 4/9, and the image information with the aspect ratio of 4/3 is displayed. When the image signal Video is in the first display area, the paper standard applies the Chinese National Standard (CNS) A4 Specifications (210X297mm) -5- (Please read the precautions on the back before you ^: the next page j Order 463069 Central Printing Bureau of the Ministry of Economic Affairs of the Bayer Consumer Cooperative Press A7 £ 7 ___ V. Description of the invention (3) To be sampled corresponding The first sampling clock for the video signal Video in the first display area and the sampling clock for sampling the other signals Video corresponding to the second display area are different, that is, if the display has a wide width When the sampling signal when the video signal Video of the aspect ratio 1 6/9 video is in the effective display area of the aspect ratio 1 6/9 is CK, the first display area uses the normal sampling clock CK 3 / 4 times the sampling clock for sampling, and the second display area uses 3/2 times the sampling clock for sampling clock CK Sampler. When such a sampling clock is to be generated (formed), the circuit structure shown in Figure 14 is used to divide the high frequency signal oscillated by the frequency generator (generator) V0C by 1 / n to form the sampling clock. However, in this method, the frequency of the signal VO C which becomes the reference (reference) is extremely high, so that it is easily affected by external circuits. Therefore, not only the formed sampling clock will become unusable. At the same time of stability, it will increase power consumption and cause inconvenience such as generating unnecessary electromagnetic waves. The present invention was invented to cope with the above-mentioned problems. The object is to provide an inexpensive and highly accurate To display an image display method and an image display device having image information having a different aspect ratio from the display screen, and the desired aspect ratio "[a mechanism for solving problems]. The present invention is an image display The device is mainly equipped with: Youyou (please read the note $ item on the back before filling ^ this page)

This paper size is applicable to China National Standard (CNS) A4 (210X297 mm)-6-Printed by the Central Laboratories of the Ministry of Economic Affairs and Consumer Cooperatives 4 63 069 A1 _ B7 V. Description of the invention (4) Number display pixels A display panel having a plurality of horizontal pixel lines formed with a predetermined aspect ratio; and outputting a signal voltage corresponding to each display pixel of each horizontal pixel line according to a clock signal input from an image signal A horizontal scanning circuit; selecting a vertical scanning circuit for the horizontal pixel lines; and a control circuit for supplying the clock signal to the horizontal scanning circuit, characterized in that the control circuit is provided with: a frequency division mechanism for The first ratio and the second ratio are used to divide the reference (reference) clock signal; and a selection mechanism for selecting the aforementioned reference clock signal combined in the horizontal scanning period and the first ratio signal from the aforementioned frequency division mechanism The output of the frequency-divided output and the frequency-divided output from the aforementioned frequency-dividing mechanism are divided by the second ratio. The invention is also an image display method, which is mainly provided with a plurality of horizontal pixel lines formed by a plurality of display pixels, and for a display panel having a predetermined aspect ratio, it is based on the input image signal. The clock signal is used to form a predetermined image and each display pixel displayed on each horizontal pixel line, which is characterized in that the reference clock signal is divided by a predetermined first ratio and a second ratio, and is selectively used in The output of the base clock signal and the output divided by the aforementioned first ratio and the output divided by the aforementioned second ratio during a horizontal scanning period. According to the present invention, it is possible to provide an image display method for displaying image information having an aspect ratio different from that of a display screen at low cost and with a desired aspect ratio from a desired aspect ratio by using the structure described above, and Image _ display device β f Please read the notes on the back before filling out this page) This paper size is applicable to China National Standards (CNS) Α4 specifications (210 × 297 public envy) 4 63 06 9 a? _____B7____ 5. Description of the invention (5) [Embodiments of the invention] Hereinafter, a liquid crystal display device according to an embodiment of the present invention will be described with reference to the drawings. '' The liquid crystal display device 1 is shown in FIG. 1, and is configured to have a display area 1 0 3 with a diagonal of 6 inches and an aspect ratio of 16/9, and is realized by an image signal Video corresponding to the NTSC method. The display states shown in Figures 1 (b) and (c). The liquid crystal display device 1 includes: a liquid crystal panel 101; four X driving circuits 20 1 — 1, 20 for sampling a video signal Video electrically connected to the liquid crystal panel 101 to supply a desired voltage 1-2, 201-3, 201-4; one Y driving circuit 301 for supplying the scan-and-hang pulse; and a control circuit section 401. The workload of the Central Bureau of Standards of the Ministry of Economic Affairs < < Cooperative printed LCD panel 1 0 1 is shown in FIGS. 1 and 2, and the array substrate 110 and the counter substrate 150 are individually twisted by the alignment films 181 and 183 to maintain the orientation. (Twisted nematic.) Type of liquid crystal layer 1 8 5 and a sealant. (Not shown) to adhere to each other, and on the outer surface of each substrate 110, 1 50, individual polarized light (polarized polarization) Light) plates 1 9 1 and 1 9 3 form polarized light axes that are orthogonal (intersect perpendicularly). The array substrate 110 is configured with 480x3 signal lines Xi (i = 1, 2, ..., 1 4 4 0) and 2 4 0 scan lines.

Yj (j = 1, 2, ..., 240) is slightly orthogonal. In the vicinity of the intersection of each signal line X j and each scanning line Y j, the scanning line Y j itself is used as a gate electrode and a gate insulating film is used. 1 2 2 An amorphous layer is used for the active layer 1 2 3 High quality silicon film, and then cover the channel protection film 8-This paper size applies the Chinese National Standard (CNS) A4 specification (21〇 × 297 mm) 4 63 069__B7_ V. Description of the invention (6) 1 2 3, to be connected to An active layer 1 2 3 has a drain (electrical) electrode 12 5 extending from the signal line X i and an inverse stagger thin film transistor formed by the source (electrical) electrode of the active layer 1 2 3 12 1 (hereinafter abbreviated as TFT) > The source electrode 126 of the TFT 121 is connected to a pixel electrode formed by I.T.O (Indium Tin Oxide). The array substrate 1 1 0 is provided with a slightly reduced scanning line. An auxiliary capacitor line C j (j = 1, 2, ..., 240) arranged in parallel and having an area overlapping with the pixel electrode 1 3 1 is formed by the pixel electrode 13 1 and the auxiliary capacitor line C j The auxiliary capacitor C s is formed. The counter substrate 150 has a TFT 1 2 1 formed on the array. The substrate 1 1 0 is used to shield the signal line X i and the figure. The gap between the electrodes 1 3 1 and the scanning line Y j and the pixels. The matrix-shaped light-shielding layer 1 5 3 used between the electrodes 1 3 1 and the red light-emitting layer arranged between the light-shielding layers 1 5 3 in order to achieve color display. (R), green (G), and blue (B) are composed of three primary colors (device) layer 1 5 5 and are provided with a counter electrode formed by I. T. 0. Economy Printed by the Central Bureau of Standards, Shellfish Consumer Cooperative, please read the notes on the back before filling in this I) As mentioned above, the display area 1 0 3 of the above-mentioned liquid crystal panel 1 0 1 includes red (R), There are 480 display pixels of one horizontal pixel line made up of green (G) and blue (B) display pixels, and there are 240 such horizontal pixels arranged. The control circuit 40 1 supplies the horizontal clock signal XCK, the horizontal start signal XS T and the video signal Video to the X driving circuit 20 1-1, 201-2, 201-3, 201-4 and the Y driving circuit 3 0 1 Each of the vertical clock signal Y.CK and the vertical start signal YST is output. This paper size applies Chinese national standard (CNS > A4 specification (210 × 297mm) -9- 4 63 〇S 9 A7 __ B7 V. Description of the invention (7) X drive circuit 2 0 1 _ 1 is shown in Figure 3 In order to include a shift register S / R which is composed of a forward and reverse circuit in which the horizontal start signal XST is sequentially transmitted according to the horizontal clock signal XCK and which is in a 12 0 (stage) segment, and according to the shift The output of the bit register S / R sequentially samples the video signal Video sampling transistor S TF T sampling circuit 2 1 1 and latches held by the sampling signal voltage Vsig sampled by the sampling circuit 2 1 1 The circuit 2 2 1 and the buffer circuit 2 3 1 are constituted, and the X driving circuit 2 0 1 — 2, 20 1 — 3, 2 0 1_ — 4 is also the same because of the same structure, so its description is omitted * Y driving circuit 3 0 1 is a shift register S / R composed of a 2 4 0 stage inverting circuit for sequentially transmitting the vertical start signal Y ST according to the vertical clock signal YCK / as shown in FIG. It is composed of 3 1 1 as a buffer circuit for the output of scanning pulses. Printed and controlled by the Central Consumers' Bureau of the Ministry of Economic Affairs, Consumer Work Cooperative. Circuit 4 0 1 Series As shown in Fig. 5, a horizontal clock control (circuit) section 4 1 1 which can output different horizontal clock signals XCK according to a screen switching signal SEL input from the outside is provided. This horizontal clock control circuit section 4 1 1 is provided with A control signal forming section 421 that forms the control signals A, B, and C based on the switching signal SEL, and a reference (reference) clock signal CKr ef with a frequency (fck) of 1 4 MHz based on the horizontal and vertical synchronization signals H / Vsync. 'For example, a clock oscillation (generation) circuit 431 constituted by a PLL circuit, etc., and a horizontal clock forming section 4 4 1 (refer to FIG. 6), and the horizontal clock forming section 4 4 1 is controlled by the control signals A, B, and C, and the reference Clock; CK ref ft, and the inverted reference clock reversed (inverted) by the inverter -10-This paper size applies to China ’s poor families {CNS) A4 size (210X297 mm) 4 63 ί: Brush Α7 .___ Β7 ___ V. Description of the invention (8) Controlled by the signal ICK ref "The horizontal clock forming unit 411 ° control signal A will be described in detail with reference to Fig. 6 at one end of the NOR (reverse OR) gate 4 6 4 and the other Enter 1 on the other side The output of the flip-flop 4 4 3, as for the output of the NO gate 46 4, will be introduced at one end of the NAND gate (reverse) gate 4 6 6. The control signal B is input to one end of the OR gate 4 6 5, and the other end is the inverter 4 6 9 with the output of the third flip-flop 4 4 5 and the output of the OR gate 4 6 5 , Will be introduced at the other end of the NAND gate 4 6 6. The first flip-flop 4 4 3 is controlled based on the output of NAND 閛 4 6 6 and the reference clock signal CK r e f, and its output is introduced as a signal D to one end of the NOR gate 4 5 5. The control signal A is input to one of the NAND gates 4 6 7 by the central government's quasi- bureau of the Ministry of Economic Affairs and the consumer cooperative, and the control signal B is input to the NAND gate 4 6 by the inverter 4 6 2 The other end of 7, and the output of the first flip-flop 4 4 3 is input to the other end of the NAND gate 4 6 7. The second flip-flop 4 4 5 is based on the NAND gate 4 6 7 The output and the reference clock signal CK re are controlled, and its output is introduced as a signal E to one end of the NOR gate 4 5 7. In addition, the third flip-flop 4 4 7 is controlled according to the output of the first flip-flop 4 4 3 and the inverted (reverse) clock signal I CK ref, and the output is used as the signal F to be output to 0R. One of the gates 451, 453. -OR gate 4 5 1 is controlled according to the above-mentioned signal F and control signal B-11-(#Read the note on the back ^^ item and fill in this ¾) $ The standard of $ ^ is applicable to China National Kneading Car (CNS) A4 specification (210X297 mm) 4 63 069 A? B7 Printed by the Central Laboratories of the Ministry of Economic Affairs of the Ministry of Economic Affairs and Consumer Cooperatives. 5. The description of the invention (9), and the NOR gate 4 5 5 is based on the signal D from the first flip-flop 443 and An output from the OR gate 451 outputs a signal G. The NOR gate 468 is controlled by the control signal B input by the inverter 462 and the control signal C input by the inverter 4 6 3, and the OR gate 4 5 3 is controlled by the signal F and from the NOR gate 4 The output of 6 8 is controlled. The NOR gate 4 5 7 takes the output of the OR gate 4 5 3 and the signal E from the second flip-flop 4 4 5 as inputs to output the signal. As for EXOR (mutual exclusion, or 〃> gate 459 is based on the signals G and Η to output the clock signal XC κ »the control signal A is used to control the output period of the horizontal clock signal XCK output from the horizontal clock formation unit 441." The control signals B, (: are used to control the frequency of the horizontal clock signal XCK output from the horizontal clock formation unit 4 41. That is, as shown in FIG. 7, the horizontal clock formation unit 44 1 is used as a control signal. When B and C are both at the low (L) 'level, and when the control signal B is at the L level and the control signal C is at the high (Η) level, the frequency of the reference clock signal CKr e ί (f Ck) The horizontal clock signal XCK with a frequency of 2/3 (2 fck / 3.). And the horizontal clock forming section 4 4 1 when the control signal B is at the Η level and the control signal C is at the L level, A horizontal clock signal XCK having a frequency (f Ck) equal to the frequency (f ck) of the reference clock signal CKr ef will be output. The horizontal clock forming unit 4 4 1 will control the signals B and C when they are at a high level. Will output 1/2 of the frequency (f ck) of the reference clock signal CKr ef (f.ck/2 (please read the Please fill in this page to fill in this page.) The size of the paper is GM China National Standard (CNS) A4 (210X297 mm). -12-Printed by the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4 63 069 a? Β7 V. Invention Note (1〇)) The horizontal clock signal xck ^ and the frequency (fck) of the reference clock signal CKref is calculated based on the horizontal frequency (f Η) X horizontal points. To display the NTSC signal, the horizontal frequency ( (ίΗ) is 15.734 KHz, and in the horizontal points of this embodiment, the display pixels of red (R), green (G), and blue (B) are individually composed of 4 80, and during each horizontal scanning period The effective image signal is about 8/1 0, so it will be [480 (8/10)]. That is, the frequency (fck) of the reference clock signal CKref will be {(fH) x [480 (8 / 10)]} X (3/2), so here, it will be set to 1 4 Μ。 Z. Moreover * When PAL signal is to be received, it will be at a horizontal frequency corresponding to the PAL signal ( f Η), and then change the number of horizontal points that should be used for display to adjust the clock signal (CK). The liquid crystal display device 1 will move according to the above structure. First, for the entire display area 1 0 3 of the liquid crystal display device 1, the image information having an aspect ratio of 16/9 or the image information having an aspect ratio of 4/3 is displayed as shown in FIG. 13 (b). The NTS C mode video signal Video will be described. The control circuit section 4 0 1 clock oscillation circuit 4 3 1 generates (oscillates) a reference clock signal CK ref of 1 4 MHz as shown in FIG. 8 and makes the reference The clock signal CK r ef and the inverted reference clock signal I CKr e are output to the horizontal clock forming unit 44 1 »This paper size is applicable to the China Solid State Standard (CNS) Α4 specification (2 丨 0X297 mm) 13-

Printed by the Central Government Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives 63 069 A? _______B7_ V. Description of the invention (n) In the control signal forming section 4 2 1 input the reference clock signal CKref, the switching signal SEL and the horizontal / vertical synchronization signal H / V sync, and output the horizontal start signal XST according to the input, and output the control signals A, B, and C to the horizontal clock forming section 441. And based on this input, the horizontal clock forming unit 441 makes the reference clock signal CKr e inputted by frequency division into a 1/3 frequency division signal of 1/3, and uses the first flip-flop 4 4 3 as a signal. D to output. This signal D causes the ratio of the L level and the Y level to be 1: 2. The second flip-flop 4 4 5 makes the signal D output a signal E with a clock delay according to the reference clock signal CKr e f. The third flip-flop 44 7 causes the signal D to output a signal F delayed by 1/2 clock according to the reference clock signal CKr e f. • NOR gate 4 5 5 is controlled by the output of signal D and OR gate 4 5 1 according to control signal B and signal F, and divides the reference clock signal CK ref into 1/3, and outputs the sum of L level and The effect of the 准 level is a signal ½ delayed in phase compared to the signal G which forms a 1: 1 ratio. As for the EXOR gate 459, the reference clock signal CKr ef is divided by 2/3 according to the signals G and Η, so that it is controlled to be 2/3 (2 fck / 3) of the frequency (f Ck) of the reference clock signal CKr ef. ), And output a horizontal clock signal XCK * with an effect ratio of L level and Η level which will become a 2: 1 ratio, and the video signal Video inputted according to this horizontal clock signal XC KK can be performed in a horizontal scanning period ( 1 Η) for each color {please read the notes on the back and fill in the special page) The paper size is in accordance with the Chinese standard (CNS) Α4 specification (2〗 0X297 mm) -14- Ministry of Economy Printed by the Central Bureau of Prototypes and Shellfish Consumer Cooperatives

^ 3 069 a? ________B7___ V. Description of the invention (12) Sample 4 8 0 and reproduce the image information of the aspect ratio 1 6/9 in the display area 1 of the liquid crystal display device 1 103. Next, the display area 103 is divided into a first display area A having an aspect ratio of 12/9 (4: 3) and a second display area having an aspect ratio of 4/9 as shown in FIG. 13 (c). In the display area B, a description will be given of the state of an NT SC video signal Video displaying image information with an aspect ratio of 4/3 in the first display area. In this case, as shown in FIG. 9, first, a video signal Video corresponding to the first display area A of the aspect ratio 4/3 is sampled during a period of 0.8 mm within a horizontal scanning period (1H). And during the period of 0.2 Η, the video signal Video corresponding to the second display area B of the aspect ratio 4/9 is sampled. However, in this embodiment, the video signal Video is set to perform black display in the second display area. First, the control signal forming unit 4 2 1 outputs the control signals B and C which are set to be raised in the period of 0.8H in accordance with the screen switching signal SEL, thereby outputting the frequency C of the reference clock signal CK ref. fck) is a horizontal clock signal XCK of 1/2 frequency (i ck / 2). That is, the horizontal clock forming unit 4 4 1 is the first reference clock signal CKr ef inputted by frequency division as%, and the first phase shifted by 180 °) {the frequency division signal from the first flip-flop 4 4 3 Output as signal D. The second flip-flop 4 4 5 is because the control signal A and the control signal B are both at the L level, so the signal E at the high level is often output. In addition, the third flip-flop 447 will output the delayed signal D according to the reference clock signal CKr ef (please read the precautions on the back before filling in this page) The paper size is generally Chinese National Standard (CNS) A4 (210X297 mm) ) -15 · Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 4 63 069 a? ___B7_ _V. Description of the invention (13)) {Signal F of the clock. The NOR gate 4 5 5 is controlled by the output of the signal D and 0 R gate 4 5 1 according to the control signal B and signal F, and the phase of the output signal D is shifted by a signal G of 180 °. NOR gate 4 5 7 is based on the signal of the level of signal B, C and the output of OR gate 4 5 3 of signal F, and the signal E is controlled, and often outputs the signal of level L. The EXOR gate 4 5 9 divides the reference clock signal CKr ef by 1/2 according to the signals G and Η, and is controlled to be 1/2 of the frequency (fck) of the reference clock signal CK ref · (f ck / 2), and output a horizontal clock signal XCK with a ratio of the effects of L level and H level of 1: 1. During a period of 0.2H within a horizontal scanning period (i), video signals Video corresponding to the second display area B of the aspect ratio 4/9 are sequentially sampled. As described above, the frequency of the horizontal clock signal XCK is switched within a horizontal scanning period (1 H), and the first display area A with an aspect ratio of 4/3 can be added without disturbing the aspect ratio. Display video signal Video with image information of 4/3 aspect ratio. As explained above, according to the liquid crystal display device 1 of this embodiment, without using expensive memory, and only by appropriately changing the frequency of its horizontal clock signal XCK, as shown in Figures 13 (b), (c) The display status is shown. Moreover, the reference clock signal CK ref is due to its unique structure, which can make it sufficiently slower than a known person, so it is difficult to be affected by external circuits, so that it can form a stable horizontal time. The clock signal KCK can be achieved more Low power consumption. And, because its frequency is reduced, (please read the precautions on the back before filling in this card). The size of the paper is common Chinese National Standard (CNS) A4 specification (210X29 * 7 mm).扃 Printed by the Consumer Cooperative Cooperative 4 63 069 a? _________B7_ V. Description of the invention (14) It can suppress the generation of unnecessary electromagnetic waves. Next, other embodiments of the present invention will be described with reference to the drawings. The liquid crystal display device 1 of this embodiment is configured so as to realize the display state shown in Fig. 13 (d) in addition to the above embodiment. For this reason, as shown in FIG. 10, the liquid crystal display device 1 is inserted with a changeover switch 5 0 1 controlled by a switching (switching) signal SE from the control circuit 4 0 1 to the X driving circuit 2 0 1 — Between 1 and X drive circuit 2 0 1-2 and it is configured that for X drive circuit 2 0 1 _ 2 can be switched to X drive circuit 2 0 1 _ 1 and the flip-flop output of the final bonus stage is used as the start In the case of the signal XST, and in the case where an operation is generated in accordance with the start signal XST 2 input from the control circuit 401. With this structure, the control circuit 4 0 1 is configured to output the first and second start signals XST1, XST2, and the switching signal SE »This liquid crystal display device 1 can operate according to the above-mentioned structure. As follows "First, the display area 1 of the liquid crystal display device 1 as a whole will be described in order to display image information having an aspect ratio of 16/9 or an image having an aspect ratio of 4/3 as shown in FIG. 13 (b). NTSC video signal Video. The flip-flop output of the final (stage) stage of the X drive circuit 2 0 1 — 1 is set to be able to be input to the X drive circuit 2 0 according to the switching signal SE output from the control circuit section 401. 1 -2. In other words, each X driving circuit 20 1_1, 2 0. 1 — 2, 20 1-3, 20 1 — 4 is made into a string (cascade) connection. The paper standard is in accordance with the Chinese national standard (CNS M4 Yuege). (210X297mm) -17- 4 63 Delete a? B7 Printed by the Central Bureau of Standards, Ministry of Economic Affairs, Shellfish Consumer Cooperative, V. Description of Invention (15) State "Same as the above embodiment, the control circuit 4 0 1 is According to the 14MHz reference clock signal CKref shown in FIG. 8, it is controlled to be a frequency (2fck / 3) of 2/3 of the frequency (fck) of the reference clock signal CK ref and outputs the effects of the L level and the chirp level. The horizontal clock signal XCK, with a ratio of 2: 1. According to the video signal Video input according to the horizontal clock signal, it will sample 4 8 0 'for each color within a horizontal scanning period (1 H), and In the display area 1 0 3 of the liquid crystal display device 1, the image information of the aspect ratio 16/9 will be reproduced. Next, the width of the display area 10 0 30% will be described, as shown in FIG. 13 (c). The first display area A with an aspect ratio of 12/9 (4: 3), and the second display® domain B with an aspect ratio of 4/9, and displays an aspect ratio of 4 / In the case of the NTS C video signal of the image information 3 in the case of the first display area A ", in this case, it is also set to the X drive circuit 2 01-2 in accordance with the control circuit section 4 0 1 The switching signal SE is output so that the flip-flop output of the final stage of the X driving circuit 2 0 1-1 can be input as the start signal XST *, that is, each X driving circuit 2 0 1-1, 201-2, 201 — 3, 201 — 4 to form a string (ladder) connection. In the same way as the above-mentioned embodiment, the control circuit section 4 0 1 first outputs the frequency (f ck) of the reference clock signal CKr ef. Horizontal clock signal XCK with 1/2 frequency (fck / 2) to one level {Please read the notes on the back before filling this page)

.1T This paper size is applicable to China Solid State Standards (CNS) A4 (210X297 mm) • 18- B7 Printed by the Consumer Cooperatives of the Central Samples Bureau of the Ministry of Economic Affairs 5. Description of the invention (16) Within the scanning period (1H) During 0 · 8H, the video signal Video corresponding to the first display area A with an aspect ratio of 4/3 can be sampled. Then, for the remaining 0.2H period, a horizontal clock signal XCK having a frequency (fck) equal to the frequency (fck) of the reference clock signal CKref will be output. Therefore, within a horizontal scanning period (1 H), sampling corresponding to all pixels is completed. As described above, the video signal Video * having the image information of the aspect ratio 4/3 can be displayed in the first display area A of the aspect ratio 4/3 without disturbing the aspect ratio. Next, the first display area A with an aspect ratio of 4/9 as shown in FIG. 13 (d) and the first display area A with an aspect ratio of 1 2/9 (4: 3) will be described. 2 Display area B, and display the NT SC video signal Video with the image information of the aspect ratio 4/3 in the second display area B. In this case, it is set to input the second horizontal start signal XS T to the X driving circuit 2 0 1-2 according to the switching signal SE output from the control circuit section 4 0 1 and the control circuit section 4 0 1. 2. In the same way as the above-mentioned embodiment, the control circuit section 40 1 shown in FIG. 12 firstly outputs the horizontal clock signal XCK of the frequency (fck / 2) of the frequency (f ck) of the reference clock signal CKr ef. The video signal Video corresponding to the second display area B of the aspect ratio 4/3 can be sampled during a period of 0.8 mm within a horizontal scanning period (1 mm). The X drive circuit 2.0 1. _2., 20} — 3, 201 _ 4, will be based on the second horizontal start signal XST 2 and the paper size of the horizontal clock letter, using the Chinese national standard (CNS} A4 specification (210X297 public) ) -19- Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4-6 3 06- A7 ___'______ B7 _ V. Description of Invention (17) XCK samples the video signal Video corresponding to the second display area B. Then During the remaining 0 · 2H period, the control circuit will output a horizontal clock signal χ (: K · × drive circuit 201-1) which is equal to the frequency (fck) of the reference clock signal CK ref. The signal XST1 and the horizontal clock signal XC CK are used to sample the image signal corresponding to the first display area A. Therefore, within a horizontal scanning period (1 H), sampling corresponding to all pixels can be completed. Thus, The video signal Video with the image information of the aspect ratio 4/3 can be displayed in the second display area 8 of the aspect ratio 4/3 since the aspect ratio is disturbed. As explained above, the basis The liquid crystal display device of this embodiment can be implemented in addition to the above In addition to the embodiment, the display state shown in FIG. 13 (d) can also be realized. In the above-mentioned embodiments, although the NT SC video signal Video is used as an example. For explanation, it is also possible to display various signals. Of course, the effective display area can be subdivided appropriately and displayed at various display positions. When the effective display area is divided, different types of video signals Video can be combined to display different images in individual In the liquid crystal display device (1) of the above embodiment, although an active matrix type display device electrically connecting a TFT to each pixel is described as an example, it is used as a switching (exchange) element. Μ I Μ (Metal Insulator Metal) can also be used. 0 This paper size is in accordance with China National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling in this page)

-20- 4 63 069 a? ______B7 _ V. Description of the invention (18) [Effects of the invention] According to the image display device and the image display method of the present invention, it can be made inexpensively and with high precision and with the expectations Aspect ratio to display image information with an aspect ratio different from the display screen. [Brief Description of the Drawings] FIG. 1 is a schematic structural diagram of a liquid crystal display device according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of a part of the liquid crystal panel of FIG. FIG. 3 is a schematic structural diagram of the X driving circuit section of FIG. 1. FIG. 4 is a schematic structural diagram of the Y driving circuit section of FIG. 1. FIG. 5 is a schematic structural diagram of a control circuit section of FIG. 1. FIG. 6 is a schematic configuration diagram of a horizontal clock forming section of a control circuit section. Figure 7 is a diagram illustrating the relationship between the frequency of the control signal and the horizontal clock signal XCK. "Figure 8 is a waveform diagram of a horizontal clock signal formed in the horizontal clock forming section. 9 is a waveform chart for forming other horizontal clock signals in the horizontal clock forming section. FIG. 10 is a schematic structural diagram of a liquid crystal display device according to another embodiment of the present invention. FIG. 11 is a schematic structural diagram of a control circuit section of FIG. 10. Fig. 12 is a waveform chart for forming a 7jc flat clock signal in the horizontal clock forming section. This paper is based on China National Sample Rate (CNS) A4 (210XW7mm) -21- '4 63 069 A7 A 7 B7 V. Description of the invention (19) Figure 13 is a diagram for explaining various display states. Please refer to Figure 14 for a schematic diagram of a conventional horizontal clock forming section for forming a horizontal clock signal. [Explanation of symbols] 1: LCD display device 103: Display area 201 — 1, 201-2, 201-3, 201-4 X drive circuit 301: Y drive circuit 401: Control circuit (part) 411: Horizontal Attention to clock formation

I order

The Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs of the People's Republic of China The paper size is applicable to the Chinese family standards (CNS > A4 size (210X297 mm) -22-

Claims (1)

Announcement image 4 63 〇69 Sf C8 I _____J D8 VI. Patent application scope 1 type of image display device, which mainly includes: It has a plurality of horizontal pixel lines formed by a plurality of display pixels, and has a predetermined width High-ratio display panel: A horizontal scanning circuit that outputs a signal voltage corresponding to each display pixel of each horizontal pixel line according to the clock signal input from the image signal is selected. The vertical scanning circuit for the horizontal pixel line is selected. ; And a control circuit for supplying the aforementioned clock signal to the aforementioned horizontal scanning circuit, which is characterized by «the aforementioned control circuit is provided with: a frequency dividing mechanism for dividing the frequency by a predetermined first ratio and a second ratio (reference) Clock signal use: and selection mechanism for selecting the aforementioned reference clock signal combined with the output of the frequency-dividing unit divided by the first ratio from the aforementioned frequency-dividing unit during a horizontal scanning period, and Used for output divided by the second ratio. 2. The image display device according to item 1 of the scope of patent application, wherein the aspect ratio of the aforementioned display panel is 16/9. Printed by the Central Government Bureau of the Ministry of Economic Affairs of the Industrial and Consumer Cooperatives (please read the notes on the back of the poem before filling out this page) 3. The image display device described in item 2 of the scope of patent application, where When the aspect ratio is 4/3, the first ratio of the frequency division mechanism is set to 1/2. 4. The image display device according to item 2 of the scope of patent application, wherein when the aspect ratio of the video signal is 16/9, the second ratio of the frequency dividing mechanism is set to 2/3 . 5. The image display device as described in item 1 of the scope of patent application, the paper size of which is based on the Chinese National Rolling Ratio (CNS) A4 format (210X M7 mm) 463069 A8 B8 C8 D8 Printed by Bureau Shell Consumer Cooperatives 6. The aforementioned frequency division mechanism in the patent application park performs frequency division based on the establishment and reduction of the aforementioned reference clock signal "6. Please refer to the figure described in item 1 of the patent scope The image display device, wherein the aforementioned frequency dividing mechanism includes: a frequency dividing unit that divides the aforementioned reference clock signal to 1/3 as the first 1/3 frequency dividing signal; and divides the aforementioned first 1/3 frequency dividing The phase of the signal is delayed by 2 times the period of the reference clock signal as the delay portion of the second 1/3 frequency-divided signal; and the side wave is constructed from the first and the second 1/3 frequency-divided signals. This and the lower sides form each other to form a detection output section of the aforementioned 2/3 frequency-divided signal. 7 types of image display methods, mainly including horizontal pixel lines formed by multiple display pixels with multiple branches, and for display panels with a predetermined aspect ratio * will be based on the clock signal from the input image signal Those who form predetermined display images and display pixels on each horizontal pixel line are characterized by: dividing the reference clock signal by a predetermined first ratio and a second ratio, and using selective stacking at a level The base clock signal combined with the output divided by the first ratio and the output divided by the second ratio during the scanning period. 8. The image display method according to item 7 of the scope of patent application, wherein the aspect ratio of the aforementioned display panel is 16/9. 9. The image display method as described in item 8 of the scope of the patent application, wherein when the aspect ratio of the aforementioned video signal is 4/3, the aforementioned first ratio is set to 1/2 / * 10. The image display method described in item 8 of the patent scope, (please read the precautions on the back before filling this page) This paper size is not suitable for the rubbing rate of China and China (CNS Washing (210X297mm) • 24- AS Ββ C8 D8 Central Standards Bureau of the Ministry of Economic Affairs β: Industrial and consumer cooperatives printed 463 069 々, the scope of patent applications where the second ratio of the aforementioned aspect ratio of the image signal is 16/9 is set to 2/3 · 1 1. The image display method described in item 7 of the scope of the patent application 'wherein the edge is built up and lowered according to the aforementioned reference clock signal. 12. The image display method described in the scope of item 7 of the patent application' which is divided down The reference clock signal is divided into 1/3 as the first 1/3 frequency-divided signal, and the phase of the aforementioned first 1/3 frequency-divided signal is delayed by 2 times the period of the reference clock signal as the second 1/3 frequency division signal, and from the first and second 1/3 frequency division signals Build each other while lowering each other to form the aforementioned 2/3 frequency-divided signal. This paper uses the Chinese National Standard (CNS) A4 specification (210X297 mm) {Please read the "Cautions on the back side" before filling in this Jf ) -25-