4621 1 4 A74621 1 4 A7
經濟部智慧財產局員工消費合作社印製 五、發明說明（） g_-l務明領域： 本發明係關於半導體製程之方法，特別有關於製作銅 雙嵌製程中介層窗及溝渠之方法。 發明背景： 積體電路製程目的之一係使晶片内元件的體積縮 小’以提高元件積集度及降低生產成本，此外，元件的性 吨表現更是重要的課題，其影響因素除了電晶體元件本身 之線路設計外’元件的金屬内連接溝渠以及溝渠間的介層 窗都是影響元件速度表現的主要因素，此肇因於溝渠之電 阻值R ’與金屬内連線間會有電容C存在，如同熟悉相關 技術之人士所共知，RC值愈低表示時間延遲愈小。因此 目前金屬内連線已有使用銅製程取代鋁製程之趨勢，亦 即以銅金屬回填於介層窗及溝渠之製程方式取代傳統之 館轴刻製程方式。所以，利用銅雙嵌製程中介層窗及溝 渠產生金屬内連線以提高元件執行速度’毋庸置疑地， 已經成為目前半導體產業共同追求的目標。 首先，請參閲第1Α及1Β圖之習知技術中介層窗形成 於溝渠之前的截面示意圖。於部份積體電路（未圖示）上 沈積第一介電層10，第一介電層10埋設有導體區域15, 而且導體區域15上表面與第一介電層10上表面共平面。 隨後按照標準半導體製程依序形成第一氮化矽層π、第二 介電層12、第二氮化矽層13及第三介電層14，接著先行 蚀刻產生介層窗1 6，並以第一氮化矽層11為蝕刻終止 2 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐)一 -------------f,--------訂---------線 ·-- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作杜印製 A7 t5/ 五、發明說明（） 層，再形成溝渠1 7並停止在第二介電層1 2。此製程方法 的缺點為形成介層窗1 6時，必須連續#别二層材料，亦 即，第二介電層12、第二氮化矽層Η及第二介電層14。 由於蝕刻的介層窗丨6深度過大，當必須回填犧牲層於介 層窗1 6以保護已形成之介層窗1 6輪廓特’會因不容易填 滿而形成缺陷致使無法完整保護蝕刻輪廓’產生後續蝕刻 溝渠17時破壞介層窗16輪廓之問題《 參閱第2Α及2Β圖之習知技術中溝渠形成於介層窗之 前的截面示意圖。如同第1Α及1Β圖所述之製程’其差別 在於先行產生溝渠24，並以第二氮化矽層22為蝕刻停止 層，隨後形成介層窗25並停止在第一氮化矽層20。此製 程方法的缺點為形成介層窗25時，若覆蓋在溝渠24的光 阻對介電層的選擇比不夠高，會於蝕刻介層窗25時破壞 已形成的溝渠24輪廓，而且在形成介層窗25時，由於已 經產生第二介電層21上表面與第三介電層23上表面之階 梯高度（step height)’容易使得光阻塗佈不均勻且聚焦深 度（depth of focus)控制不易，造成曝光顯影偏差，敌使線 寬無法有效縮小。 因此’上述之先行同時覆蓋複數層介電層，之後再形 成介層窗及溝渠’衍生介層窗深度過大、蝕刻輪廓較差i 聚焦深度控制不易及曝光顯影等諸多製程問題。 最後’請參閱第3…B圖之習知技術中利用鑲嵌硬 式罩幕形成介層窗及溝渠方法之截面示意圖。於部份積體 電路（未圖示）上沈積第一介電層3〇，笛 .^ a " 罘一介電層3 0埋 3 良紙張尺度適用中國國家標準（CNS)A4規格（2】0 X 297公釐） II I--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 4 4Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention () g_-l Fields of the Invention: The present invention relates to a method for semiconductor processes, and particularly to a method for manufacturing interlayer windows and trenches in a copper dual-embedded process. Background of the Invention: One of the goals of the integrated circuit manufacturing process is to reduce the volume of components in the wafer to increase the degree of component accumulation and reduce production costs. In addition, the performance of components is an important issue, and its influencing factors are in addition to transistor components. The internal metal connection trenches of the components outside the circuit design and the interlayer windows between the trenches are the main factors affecting the speed performance of the components. This is due to the existence of a capacitance C between the resistance value R 'of the trench and the metal interconnects. As everyone familiar with the related technology knows, the lower the RC value, the smaller the time delay. Therefore, the current metal interconnect has a tendency to use copper instead of aluminum, that is, to replace the traditional hall-shaft engraving process with copper metal backfilling in the interlayer windows and trenches. Therefore, the use of copper dual-embedded interposer windows and trenches to generate metal interconnects to increase component execution speed is undoubtedly a common goal pursued by the current semiconductor industry. First, please refer to the cross-sectional diagrams of the conventional interposer window before the trench is formed in the conventional technology shown in FIGS. 1A and 1B. A first dielectric layer 10 is deposited on a partial integrated circuit (not shown). The first dielectric layer 10 is embedded with a conductor region 15, and the upper surface of the conductor region 15 is coplanar with the upper surface of the first dielectric layer 10. Subsequently, a first silicon nitride layer π, a second dielectric layer 12, a second silicon nitride layer 13 and a third dielectric layer 14 are sequentially formed according to a standard semiconductor process, and then a dielectric window 16 is formed by etching, and The first silicon nitride layer 11 is the termination of etching. 2 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). ------------- f, ---- ---- Order --------- line ·-(Please read the notes on the back before filling this page) Duty printing of A7 t5 by the Intellectual Property Bureau of the Ministry of Economic Affairs ) Layer, form trench 17 again and stop at second dielectric layer 12. The disadvantage of this process method is that when forming the dielectric window 16, two different layers of materials must be continuous, that is, the second dielectric layer 12, the second silicon nitride layer Η, and the second dielectric layer 14. Because the depth of the etched interposer window 6 is too large, when the sacrificial layer must be backfilled to protect the interposer window 16 which has been formed, the contours of the interposer window 16 will be formed due to the difficulty of filling, and the etch contour cannot be completely protected. 'Problem in destroying the contour of the via window 16 when the trench 17 is subsequently etched.' Refer to the conventional technique of FIGS. 2A and 2B for a schematic cross-sectional view of a trench formed before the via window. The difference in the process as described in FIGS. 1A and 1B is that the trench 24 is generated in advance, and the second silicon nitride layer 22 is used as an etch stop layer, and then a via window 25 is formed and stopped on the first silicon nitride layer 20. The disadvantage of this manufacturing method is that when the dielectric window 25 is formed, if the selection ratio of the photoresist covering the trench 24 to the dielectric layer is not high enough, the contour of the formed trench 24 will be destroyed when the dielectric window 25 is etched, and the formation of the At the time of the interlayer window 25, since the step height of the upper surface of the second dielectric layer 21 and the upper surface of the third dielectric layer 23 has been generated, it is easy to make the photoresist coating uneven and the depth of focus. It is not easy to control, causing deviations in exposure and development, and the enemy's line width cannot be effectively reduced. Therefore, 'the above-mentioned first covers a plurality of dielectric layers at the same time, and then forms vias and trenches.' Derived vias have too large depths, poor etch contours, control of focus depth, and many process problems such as exposure and development. Finally, please refer to the cross-sectional schematic diagram of the method of forming interstitial windows and trenches by using the inlaid hard mask in the conventional technique shown in Figs. 3 ... B. A first dielectric layer 30 is deposited on a part of the integrated circuit (not shown). ^ A " 罘 a dielectric layer 3 buried 3 good paper size applicable to China National Standard (CNS) A4 specifications (2 ] 0 X 297 mm) II I -------- Order --------- Line (Please read the precautions on the back before filling this page) 4 4
五、發明說明（ 經濟部智慧財產局員工消費合作社印製 設有導體區域34’而且導體區域34上表面與第一介電層 匕〇上表面共平面，之後按照標準半導體製程依序形成第： 氮化矽層3卜第—介電層32及—鑲嵌硬式罩幕”如氮化 :夕·層，接著僅蝕刻鑲嵌硬式罩幕33.，其開口寬度與介層窗 5開口見度相同’隨後沈積第三介電層36並圖案化第三 介電層36’最後連續蚀刻形成溝渠”及介層窗〜此製 程方法的缺點為，雖然不必如第1A及1B圖所示連續蝕刻 三層材料，但仍須餘刻第二介電層32及第三層介電Μ， 因此硬式罩幕3 3厚度必須足夠大。 所以，傳統的介層窗及溝渠之製程方法至少包含下列 缺點： 1 _因連績蝕刻過厚的介電材料而產生太深的介層窗，限制 了回填犧牲層以保護介層窗之能力。 2. 製程中形成的介電層間階梯高度會導致光阻塗佈不均 勻α 3, 介電層間的階梯高度會影響聚焦深度之調控產生後續曝 光顯影之偏差’不利於縮小元件線寬。 因此’本發明提供一回填低介電常數材料於介層窗， 作為銅雙嵌製程中介層窗及溝渠的犧牲層並具有隨著光 阻圖案同時去除之特點，有助於形成及連結多重金屬内連 線圖案，達成改善上述缺失之功效並因應未來元件線寬曰 益縮小之殷切需求。 發明目的及概诚 本紙張尺度適用中國國家標準（CNS)A4規格（210 >= 297公釐） ----------------------訂---------線---I ί靖先閱讀背面之注f事項再填寫本頁) 46 21 4 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 本發明之目的係提供一新式銅雙嵌制浐 叉欣I杠，回填以低介 電常數材料於.介.層窗之製程方法，作為铜橄山法 丨F 4扣又耿製程中介層 窗及溝渠的犧牲層且可與光阻圖案同時去除’此外，介層 窗及溝渠配合個別的介電層依序分開蝕刻形成，而且具^ 平坦化之表面使得聚焦深度易於控制，有助於形成及連結 多重金屬内連線圖案。 本發明之較佳實施例中’介層窗及溝渠之形成步驟 至少包含：（1)提供一半導體基材，於半導體基材上沈積 第一介電層，並於第一介電層埋設導體區域，此導體區 域上表面與第一介電層上表面共平面；（2)形成氮化矽層 於導體區域及第一介電層上；（3)以化學氣相沈積法 (chemical vapor deposition ; CVD)沈積第二介電層於氮 化矽層上；（4)形成第一光阻圖案於第二介電層上以定義 介層窗’（5)實施非等向性蚀刻以轉移第一光阻圖案於第 一介電層’並以氮化矽層為蝕刻終止層，再移除第一光 阻圖案以形成介層窗；（6)自旋塗佈犧牲層以填滿介層窗 及均句分布至第二介電層表面；（7)施以平坦化製程例如 化學機械研磨（chemical mechanical polishing;CMP)或 回袖（etch back)多餘的部份犧牲層至曝露第二介電層， 以形成平坦化表面；（8)以CVD沈積第三介電層於平坦 化表面’用以作為蝕刻溝渠之介電層；（9)形成第二光阻 圖案於第三介電層上以定義溝渠；（1〇)實施非等向性蝕 刻以轉移第二光阻圖案於第三介電層而形成溝渠，並停 止在第二介電層；及（11)同時移除該第三介電層上之 本紙張尺度適用令國國家標準（CNS)A4規格（210 X 297公楚） -----1IJ1111I — ---I----訂 ίιιιιιι - 1 ϊ I (請先閱讀背面之注意事項再填寫本頁〕 4 62114 經濟部智慧財產局員工消費合作社印製 A7 _B7_ 五、發明說明（） 第二光阻圖案及介層窗内之犧牲層以形成介層窗及溝 渠之雙嵌結構。 S-4圖式簡單說明： 第1A及1B圖依據習知技術中介層窗形成於溝渠之前的截 面不意圖， 第2A及2B圖依據習知技術中溝渠形成於介層窗之前的截 面示意圖； 第3 A及3 B圖依據習知技術中利用鑲嵌硬式罩幕形成介層 窗及溝渠方法之截面示意圖； 第4圖依據本發明沈積氮化矽層及第二介電層於具有元件 _ (未標示）之基材的截面示意圖； 第5圖依據本發明之實施非等向性蝕刻於第二介電層以形 成介層窗之截面示意圖； 第6圖依據本發明之實施自旋塗佈犧牲層於介層窗内及第 二介電層表面之截面示意圖； 第7圖依據本發明之實施平坦化製程以移除多餘部份犧牲 滑之截面示意圖； 第8圖依據本發明之於平坦化表面沈積第三介電層之截面 示意圖； 第9圖依據本發明之以第二光阻圖案定義溝渠之截面示意 圖； 第1 0圖依據本發明之實施非等向性蝕刻於第三介電層以 轉移第二光阻圖案而形成溝渠之截面示意圖：及 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------------------訂------------- (請先閱讀背面之注意事項再填寫本頁) 4 經濟部智慧財產局員工消費合作社印製 621 1 4 A7 _B7_ 五、發明說明（） 第1 1圖依據本發明之剥除殘留犧牲層以及第二光阻圖案 之截面示意圖。 5-5圖號對照說明： 10 第 —' 介 電 層 11 第 一 氮 化 矽 層 12 第 二 介 電 層 13 第 二 氮 化 矽 層 14 第 三 介 電 層 15 導 體 區 域 16 介 層 窗 17 溝 渠 20 第 一 氮 化 矽 層 2 1 第 二 介 層 22 第 二 氮 化 矽 層 23 第 -- 介 電 層 24 溝 渠 25 介 層 窗 30 ，第 — 介 電 層 3 1 第 一 氮 化 矽 層 32 第 二 介 電 層 33 鑲 嵌 硬 式 罩 幕 34 導 體 區 域 35 介 層 窗 36 第 三 介 電 層 37 溝 渠 40 第 一 介 電 層 42 氮 化 矽 層 44 第 二 介 電 層 46 導 體 區 域 50 介 層 窗 60 犧 牲 層 70 平 坦 化 表 面 80 第 介 電 層 90 第 二 光 阻 圖 案 100 溝渠 7 ---------------------訂·-------- {請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 4 6 2114 4 6 2114 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（） 5-6發明詳細說明： 鑑於上述發明背景所述之關於銅雙嵌製程中形成介 層窗及溝渠存在諸多問題有待克服，本發明將針對相關缺 失提供有效的解決方法。茲以圖示輔助說明，並詳述完整 的製作鋼雙嵌製程中介層窗及溝渠之方法。 首先’清參閱第4圖沈積氮化妙層及第二介電唐於具 有元件（未標示）之基材的截面示意圖。提供一半導體基 材’於半導體基材上沈積第一介電層4〇，並於第一介電層 40埋设導體區域46，此導體區域46上表面與第一介電層 40上表面共平面。另外，導體區域46之材料為銅（Cu)或 祐（A丨）’通常可為閘極區 '源極、汲極、或金屬内連線 (interconnect metal) - 仍請參閱第4圖，以本發明之較佳實施例而言，首先， 以化學氣相沈積法（chemical vapor depositi〇n;CVD)沈積 一氮化矽層42於第一介電層40及導體區域46上，其厚 度約300至1〇〇〇埃，其係作為導體區域46之銅擴散阻障 層’接著’仍以CVD沈積第二介電層44於氮化矽層42 上，其厚度約3000至7000埃，隨後，形成第一光阻圖案 (未圖示）於第二介電層44上以定義介層窗。其中，第二介 電層44之材料是氧化矽（siliC0I1 oxide;Si〇x)或氟矽玻璃 (fluorinesilicate glass;FSG)’氮化矽層42也可以碳化矽層 取代，因為碳化矽亦是銅擴散阻障層之良好材料。 參閱第5圖之實施非等向性蝕刻於第二介電層以形成 介層窗之截面示意圖。施以非等向性蝕刻以轉移第一光阻 8 本紙張尺度適用中關家標準（CNS)A4規格（210 X 297公爱) ' I - - ------11 — —"·^--- I I I 訂-II —-- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作杜印製 4621)4 A7 ____ B7 五、發明說明（） 圖案於第二介電層44’並以氮化矽層42為蝕刻終止層， 再移除第一光阻圖案以形成介層窗50»本步驟中可選擇蝕 刻或不蝕刻氮化矽層42，若不蝕刻而留待後續製程施行蝕 刻之優點為可避免導體區域46遭受破壞。本步驟使用的 蚀刻溶液為〇4!；'8、<^4、（2>1?3、仏、八1：及（30之混合氣體。 參閱第6圖之實施自旋塗佈犧牲層於介層窗内及第二 介電層表面之截面示意圖。自旋塗佈犧牲層60以填滿介 層窗30及均勻分布至第二介電層44表面，該犧牲層6〇 之厚度約為4000至8000埃且具有可與光阻圖案同時剥除 之特性。以本發明之較佳實施例而言，係使用低介電常數 之有機材料作為犧牲層’例如FLARE或是SiLK等有機材 料1 «作為形成介層窗50及溝渠之犧牲層。此外，flare 或是SiLK等有機材料對第二介電層44或氮化矽層42具 有相當好的蝕刻選擇比，因此，對第—介電層4〇、氮化矽 層42及已形成之介層窗50輪廓有較佳保護效果。同時， 此兩種有機材料在400Ϊ至450t高溫下，仍保有原材料之 良好特性，亦即可抵抗後續沈積第三介電層時之高溫。而 丑，易以自旋塗佈方式得到均勻一致化之表面，使得基材 表面具有平坦化構形（topography)。 參閱第7圖之實施平坦化製程以移除多餘部份犧牲層 之截面示意圖•施以平坦化製程例如化學機械研磨（cmp) 或回蝕（etch back)移除多餘部份犧牲層6〇至曝露第二介 電層44 ’以形成平坦化表面7〇。 參閱第8圖之於平坦化表面沈積第三介電層之截面示 本紙張尺度適用中國國家標準（CNS)A4規格（210χ (請先閱讀背面之注意事項再填寫衣頁) I - .線 9 4 經濟部智慧財產局員工消費合作社印製 4 五、發明說明（ 意圖。以CVD沈積第=八+ a n B弟—；丨電層8〇於平坦化表面7〇，用以 作為蝕刻溝渠之介電層，t ；s * & ^ 电臂其厍度約3000至7000埃，其中， 第三介電層80之材料县备& 打针疋氧化矽（Si〇x)或氟矽玻璃（FSG)。 參閱第 9圖之 第一光阻圖案定義溝渠之截面示意 圖。形成第二光阻圖亲〇η、λΜ Α 闽菜9〇於弟三介電層8〇上以定義溝渠 圖案，由於第三介電居+ τ 电臂80已具有平坦化表面，因此可獲 得較佳溝渠之第二光阻圖案9〇。 參閱第I 〇圖之實施非等向性蝕刻轉移第二光阻圖案 以形成溝渠之截面示意圖。實施非等向性姓刻以轉移該第 光阻圖水90於第二介電層8〇而形成溝渠⑽，並以犧 牲層60為停止層。 參閱第1 1圖之剥除殘留犧牲層以及第二光阻圖案之 截面示意圖。同時移除該第三介電層8〇上之第二光阻圖 案90及介層冒50内之犧牲層6〇以形成介層窗5〇及溝渠 100之雙嵌結構。本步驟之優點為第二光阻圖案9〇與犧牲 層60 —起去除，亦即簡化了製程步驟且不會殘留在元件 内部，影響元件執行速度。剥除第二光阻圖案9〇及犧牲 層60之灰化氣體為氧（〇2)。 综上所述’本發明所揭露之製作銅雙嵌製程中介層窗 及溝渠的方法至少包含以下優點： 1_介層窗與溝渠係各自分開蚀刻形成，使得回填犧牲層之 能力較佳，亦即不易產生缺陷，構成較佳保護介層窗之 效果以獲得較好的蝕刻輪廓a 2.形成介層窗與溝渠之製程中，光阻塗佈係於平坦化表面 10 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------枣--------訂---------線 (請先閱讀背®之注意事項再填寫本頁} 4 62114 A7 _B7_ 五、發明說明（） 進行，所以可獲得均勻平坦之光阻圖案，有利於曝光顯 影。 3 .不會產生介電層間的階梯高度，使得聚焦深度容易調 控，因此可定義較佳之光阻圖案層。 4.形成於介層窗内之犧牲層對介電層的蝕刻選擇比夠高， 足以保護已成型之介層窗輪廓。 本發明以較佳實施例說明如上，僅用於藉以幫助瞭解 本發明之實施，非用以限定本發明之精神，而熟悉此領域 技藝者於領悟本發明之精神後，在不脫離本發明之精神範 圍内，當可作些許更動潤飾及等同之變化替換，其專利保 護範圍當視後附之申請專利範圍及其等同領域而定。 ---------------------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）V. Description of the Invention (The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed a conductor region 34 'and the upper surface of the conductor region 34 is coplanar with the upper surface of the first dielectric layer, and then formed in accordance with the standard semiconductor process in order: Silicon nitride layer 3—dielectric layer 32 and—inlaid hard mask ”“ Nitride: Xi · Layer, and then only etch inlaid hard mask 33. Its opening width is the same as that of the dielectric window 5 ” Subsequently, a third dielectric layer 36 is deposited and patterned. The third dielectric layer 36 'is finally etched to form trenches and dielectric windows. The disadvantage of this process is that although it is not necessary to etch three layers continuously as shown in Figures 1A and 1B. Materials, but the second dielectric layer 32 and the third dielectric M must be etched, so the thickness of the hard mask 33 must be large enough. Therefore, the traditional manufacturing method of the dielectric window and trench includes at least the following disadvantages: 1 _Deep dielectric window due to continuous etching of excessively thick dielectric materials, limiting the ability to backfill the sacrificial layer to protect the dielectric window. 2. The step height of the dielectric layer formed during the process will cause photoresist coating Uneven α 3, between dielectric layers The height of the step will affect the adjustment of the focus depth, which will cause deviations in subsequent exposure and development. It is not conducive to reducing the line width of the component. Therefore, the present invention provides a backfilling low dielectric constant material in the interlayer window as a copper double-embedded interlayer window and trench. The sacrificial layer also has the characteristics of being removed simultaneously with the photoresist pattern, which helps to form and connect multiple metal interconnect patterns, achieves the improvement of the above-mentioned defects, and meets the demand for the reduction of the line width of components in the future. The paper size of this paper applies the Chinese National Standard (CNS) A4 specification (210 > = 297 mm) ---------------------- Order ----- ---- Line --- I read the note f on the back before filling out this page) 46 21 4 A7 B7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (The purpose of this invention is to provide a The new copper double-embedded yoke fork I bar is backfilled with a low dielectric constant material in the process of the dielectric layer window, as the copper olive method 丨 F 4 buckle and the sacrificial layer of the interposer window and trench in the manufacturing process and can be Simultaneous removal with photoresist patterns' The electrical layers are sequentially and separately formed, and the planarized surface makes it easy to control the depth of focus, which helps to form and connect multiple metal interconnect patterns. In the preferred embodiment of the present invention, the formation of interlayer windows and trenches The steps at least include: (1) providing a semiconductor substrate, depositing a first dielectric layer on the semiconductor substrate, and burying a conductor region in the first dielectric layer; the upper surface of the conductor region and the upper surface of the first dielectric layer are in common; Plane; (2) forming a silicon nitride layer on the conductor region and the first dielectric layer; (3) depositing a second dielectric layer on the silicon nitride layer by chemical vapor deposition (CVD); (4) forming a first photoresist pattern on the second dielectric layer to define a dielectric window '(5) performing anisotropic etching to transfer the first photoresist pattern on the first dielectric layer' and using silicon nitride The layer is an etch stop layer, and then the first photoresist pattern is removed to form a dielectric window; (6) spin-coating a sacrificial layer to fill the dielectric window and uniformly distribute to the surface of the second dielectric layer; (7) Flattening process such as chemical mechanical polishing (CMP) Or etch back an excess part of the sacrificial layer to expose the second dielectric layer to form a planarized surface; (8) deposit a third dielectric layer on the planarized surface by CVD to serve as a medium for etching the trench (9) forming a second photoresist pattern on the third dielectric layer to define a trench; (10) performing anisotropic etching to transfer the second photoresist pattern to the third dielectric layer to form a trench, And stopped on the second dielectric layer; and (11) at the same time remove the paper size on the third dielectric layer to apply the national standard (CNS) A4 specification (210 X 297) Chu ---- -1IJ1111I — --- I ---- Order ίιιιιιι-1 ϊ I (Please read the notes on the back before filling out this page) 4 62114 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 _B7_ V. Description of Invention () Second The photoresist pattern and the sacrificial layer in the via window form a dual-embedded structure of the via window and the trench. S-4 is a simple explanation: Figures 1A and 1B are not intended according to the cross section of the interposer window formed before the trench according to the conventional technology, and Figures 2A and 2B are schematic cross sections of the trench before the interlayer window according to the conventional technology; 3A and 3B are schematic cross-sectional views of a conventional method for forming a dielectric window and a trench using an inlaid hard mask; FIG. 4 is a diagram of depositing a silicon nitride layer and a second dielectric layer in accordance with the present invention. (Not shown) a schematic cross-sectional view of a substrate; FIG. 5 is a cross-sectional view of an anisotropic etching on a second dielectric layer to form a dielectric window according to the present invention; FIG. 6 is a spin coating according to the present invention A schematic cross-sectional view of a sacrificial layer in a dielectric window and a surface of a second dielectric layer; FIG. 7 is a schematic cross-sectional view of a planarization process according to the present invention to remove unnecessary portions of sacrificial slip; A schematic cross-sectional view of the third dielectric layer deposited on the surface of the substrate; Figure 9 is a schematic cross-sectional view of the trench defined by the second photoresist pattern according to the present invention; Figure 10 is an anisotropic etching on the third dielectric according to the present invention. Layer to transfer Schematic cross-section of the trench formed by the second photoresist pattern: and 6 paper sizes are applicable to China National Standard (CNS) A4 (210 X 297 mm) ----------------- ---- Order ------------- (Please read the notes on the back before filling out this page) 4 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 621 1 4 A7 _B7_ V. Invention Explanation () FIG. 11 is a schematic cross-sectional view of a stripped residual sacrificial layer and a second photoresist pattern according to the present invention. 5-5 drawing number comparison description: 10th-'dielectric layer 11 first silicon nitride layer 12 second dielectric layer 13 second silicon nitride layer 14 third dielectric layer 15 conductor area 16 dielectric window 17 trench 20 first silicon nitride layer 2 1 second dielectric layer 22 second silicon nitride layer 23 first-dielectric layer 24 trench 25 dielectric window 30, first — dielectric layer 3 1 first silicon nitride layer 32 first Two dielectric layers 33 Inlaid hard cover 34 Conductor area 35 Dielectric window 36 Third dielectric layer 37 Trench 40 First dielectric layer 42 Silicon nitride layer 44 Second dielectric layer 46 Conductor area 50 Dielectric window 60 Sacrifice Layer 70 Flattened surface 80 First dielectric layer 90 Second photoresist pattern 100 Ditch 7 --------------------- Order · -------- {Please read the notes on the back before filling this page.) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 4 6 2114 4 6 2114 Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by Fei Cooperative A7 B7 V. Description of the invention (5) Detailed description of the invention: In view of the above-mentioned background of the invention, there are many problems to be solved in the formation of interlayer windows and trenches in the copper dual-embedded process to be overcome. Provide effective solutions. The illustrations are provided as an aid to the description, and a detailed method for manufacturing interlayer windows and trenches in a steel dual-embedded process is detailed. First, refer to FIG. 4 for a schematic cross-sectional view of a nitride layer and a second dielectric layer on a substrate with an element (not labeled). A semiconductor substrate is provided. A first dielectric layer 40 is deposited on the semiconductor substrate, and a conductor region 46 is buried in the first dielectric layer 40. The upper surface of the conductor region 46 is coplanar with the upper surface of the first dielectric layer 40. . In addition, the material of the conductor region 46 is copper (Cu) or aluminum (A 丨), which can usually be the gate region's source, drain, or interconnect metal-still refer to FIG. 4 to For a preferred embodiment of the present invention, first, a silicon nitride layer 42 is deposited on the first dielectric layer 40 and the conductor region 46 by a chemical vapor deposition method (CVD). 300 to 1000 angstroms, which is the copper diffusion barrier layer of the conductor region 46, and then a second dielectric layer 44 is still deposited on the silicon nitride layer 42 by CVD, with a thickness of about 3000 to 7000 angstroms, and then A first photoresist pattern (not shown) is formed on the second dielectric layer 44 to define a dielectric window. Wherein, the material of the second dielectric layer 44 is silicon oxide (SiOx) or fluorine silicate glass (FSG). The silicon nitride layer 42 may also be replaced by a silicon carbide layer, because silicon carbide is also copper. Good material for diffusion barrier layer. Refer to FIG. 5 for a schematic cross-sectional view of performing anisotropic etching on the second dielectric layer to form a dielectric window. Anisotropic etching was used to transfer the first photoresist. 8 This paper size applies the Zhongguanjia Standard (CNS) A4 specification (210 X 297 public love). 'I-------- 11 — — " · ^ --- Order III-II --- (Please read the notes on the back before filling out this page) Consumption Cooperation by Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Du printed 4621) 4 A7 ____ B7 V. Description of Invention () The second dielectric layer 44 'uses the silicon nitride layer 42 as an etch stop layer, and then the first photoresist pattern is removed to form a dielectric window 50. In this step, the silicon nitride layer 42 can be etched or not etched. The advantage of etching and leaving the etching for subsequent processes is that damage to the conductor region 46 can be avoided. The etching solution used in this step is 〇4 !; '8, < ^ 4, (2 > 1? 3, 仏, 11 :, and (30). Refer to FIG. 6 for the spin-coating sacrificial layer. A schematic cross-sectional view in the dielectric window and the surface of the second dielectric layer. The sacrificial layer 60 is spin-coated to fill the dielectric window 30 and uniformly distributed to the surface of the second dielectric layer 44. The thickness of the sacrificial layer 60 is about It is 4000 to 8000 angstroms and can be stripped at the same time as the photoresist pattern. In the preferred embodiment of the present invention, an organic material with a low dielectric constant is used as the sacrificial layer, such as an organic material such as FLARE or SiLK. 1 «As a sacrificial layer for forming the interlayer window 50 and the trench. In addition, organic materials such as flare or SiLK have a relatively good etching selection ratio for the second dielectric layer 44 or the silicon nitride layer 42. The electrical layer 40, the silicon nitride layer 42 and the formed interlayer window 50 have a better protection effect. At the same time, these two organic materials still have the good characteristics of the raw materials at a high temperature of 400Ϊ to 450t, and can also resist The high temperature during the subsequent deposition of the third dielectric layer, which is ugly and can be easily obtained by spin coating. Uniform surface, so that the substrate surface has a topography. See Figure 7 for a schematic cross-sectional view of the planarization process to remove the excess sacrificial layer. • Flattening process such as chemical mechanical polishing (cmp) ) Or etch back to remove the excess portion of the sacrificial layer 60 to expose the second dielectric layer 44 ′ to form a planarized surface 70. See FIG. 8 for the deposition of a third dielectric layer on the planarized surface. The cross section shows that the paper size is in accordance with Chinese National Standard (CNS) A4 specifications (210χ (please read the precautions on the back before filling in the clothing page) I-.line 9 4 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 (Intent. Deposition of the eighth + an B-by CVD; electric layer 80 on the flattened surface 70, used as a dielectric layer for etching trenches, t; s * & 3000 to 7000 angstroms, among which, the material of the third dielectric layer 80 is made of silicon oxide (SiOx) or fluorosilicon glass (FSG). See the first photoresist pattern in FIG. 9 to define the cross section of the trench. Schematic diagram to form a second photoresist map 〇η, λΜ Α Min 90 defines a trench pattern on the third dielectric layer 80. Since the third dielectric + τ electric arm 80 already has a flat surface, a second photoresist pattern 90 of a better trench can be obtained. The implementation of the figure I0 is a schematic cross-sectional view of transferring a second photoresist pattern to form a trench. An anisotropic engraving is performed to transfer the photoresist pattern water 90 on the second dielectric layer 80 to form a trench. ⑽, and the sacrificial layer 60 is used as the stop layer. Refer to the cross-sectional schematic diagram of the stripped residual sacrificial layer and the second photoresist pattern in FIG. 11. At the same time, the second photoresist pattern on the third dielectric layer 80 is removed. 90 and the sacrificial layer 60 in the via 50 are formed to form a double-embedded structure of the via 50 and the trench 100. The advantage of this step is that the second photoresist pattern 90 and the sacrifice layer 60 are removed together, that is, the manufacturing process is simplified and does not remain inside the component, which affects the speed of component execution. The ashing gas for stripping the second photoresist pattern 90 and the sacrificial layer 60 is oxygen (02). In summary, the method for making a copper double-embedded interposer window and trench disclosed in the present invention includes at least the following advantages: 1_ The interlayer window and the trench are separately formed by etching, so that the ability to backfill the sacrificial layer is better, and That is, it is not easy to produce defects, which constitutes a better effect of protecting the interlayer window to obtain a better etching profile a 2. In the process of forming the interlayer window and trench, the photoresist coating is applied on a flat surface 10 Standard (CNS) A4 specification (210 X 297 mm) -------------- Jujube -------- Order --------- Line (please first Read the notes on Back® and fill in this page again} 4 62114 A7 _B7_ 5. The description of the invention () is carried out, so that a uniform and flat photoresist pattern can be obtained, which is conducive to exposure and development. 3. There will be no step height between dielectric layers, It makes the focus depth easy to adjust, so a better photoresist pattern layer can be defined. 4. The sacrificial layer formed in the dielectric window has a high enough etching selection ratio for the dielectric layer to protect the contour of the formed dielectric window. The above description of the preferred embodiment is only used to help understand the implementation of the present invention. It is not intended to limit the spirit of the present invention, but those skilled in the art who understand the spirit of the present invention can make minor modifications and equivalent changes without departing from the spirit of the present invention. The scope of patent protection should be Depends on the scope of the attached patent application and its equivalent fields. --------------------- Order --------- line (Please read first Note on the back, please fill in this page again.) The paper printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs is compliant with China National Standard (CNS) A4 (210 X 297 mm).