457L6iJ_________ 五、發明說明（υ 發明領域 本案係為一種均勻蝕刻深溝渠構造之方法’尤指應用 於深溝渠電容製作過程中均勻蝕刻深溝渠構造之方法。 發明背景 在晶圓（Wafer)上敍刻孔洞已為半導體製程中普遍應 用之技術手段’尤其在動態隨機存取記憶體（DRAM)中深溝 渠電容（Deep Trench Capacitor)之製造上，請參見第一 圖（a) (b) (c) (d) ’其係於晶圓上形成深溝渠之習用技術手 段，其中第一圖（a)係表示出於一矽基板10上依序形成一 氮化矽層1 1、一氧化矽層1 2以及一光阻層1 3後，再以一微 影製程來對該光阻層1 3定義出複數個開口 1 3 1 ，而第一圖 (b)則表示出依序對該等開口丨3 1中所露出之氮化矽層11與 氧化矽層1 2進行蝕刻，用以形成製作深溝渠構造所需之罩 幕（mask)開口 ，在第一圖（c)即表示出將殘餘之光阻層13 去除後所完成之軍幕（mask)開口，此時再利用罩幕（mask) 開口對矽基板1 0進行蝕刻動作，最後便形成如第一圖（d ) 中所示之深溝渠構造，而可進一步提供給後續電容製程運 用。 而在深溝渠蝕刻過程中，圖案負載效應（p a t ΐ e r η loading effect)係為相當常見之現象。而此圖案負載之 差異，將導致晶圓（Wafer)中央與邊緣之蝕刻產生不均勻457L6iJ_________ 5. Description of the invention (υ Field of the invention This case is a method for uniformly etching deep trench structures' especially applied to a method for uniformly etching deep trench structures during the production of deep trench capacitors. Background of the invention engraving on wafers (Wafer) Holes have been a commonly used technology in semiconductor manufacturing processes, especially in the manufacture of deep trench capacitors in dynamic random access memory (DRAM), see the first figure (a) (b) (c) (d) 'It is a conventional technical means for forming deep trenches on a wafer, wherein the first figure (a) shows that a silicon nitride layer 1 1 and a silicon oxide layer 1 are sequentially formed on a silicon substrate 10 After 2 and a photoresist layer 1 3, a plurality of openings 1 3 1 are defined for the photoresist layer 13 by a lithographic process, and the first figure (b) shows the openings to the openings in sequence 丨The silicon nitride layer 11 and silicon oxide layer 12 exposed in 3 1 are etched to form a mask opening required for making a deep trench structure. The first picture (c) shows that the remaining The mask opening after the photoresist layer 13 is removed. The silicon substrate 10 is etched with a mask opening, and finally a deep trench structure as shown in the first figure (d) is formed, which can be further provided for subsequent capacitor process applications. In the deep trench etching process The pattern loading effect (pat ΐ er η loading effect) is a quite common phenomenon, and the difference in pattern loading will cause uneven etching of the center and edge of the wafer.
第4頁 457581 五、發明說明（2) 之現象丨晶 人藉由調整 氣體流量等 制，有些時 内，特別是 急遽減小’ 需維持甚或 (Critical 為7微米）， 積。但是， 小，而加深 負載效應更 過程中產生 方便且有效 即為本案發 雖然吾 出以及 材之限 範圍 亦隨之 吾人仍 鍵尺寸 一般約 表面 離減 使上述 在蝕刻 提供一 效應， 圓邊緣之姓刻寬度經常大於所欲線寬， 製程參數，例如：反應室壓力、功率輸 ’可得到某些程度之改善。但是因為器 候並無法將此效應改善至吾人可接受之 當元件尺寸日益縮小，深溝渠間之距離 但為了符合記憶體所需之電容量需求， 增大定義該深溝渠所用之光罩圖案之關 Dimension，簡稱CD)與深溝渠之深度（ 措以於該深溝渠完成後能提供足夠大之 關鍵尺寸（CD )增加將造成深溝渠間之距 溝渠之沐度將使触刻時間更加延長，而 形嚴重’因而導致在邊緣區域之深溝渠 深溝渠電容間短路之製程缺陷》因此， 之方法來控制深溝渠银刻過程中之負載 展之主要目的。 發明概述 本案係為一種均勻钱刻深溝渠構造之方法，其包含下 f驟.提供一基板；於該基板上形成一罩幕層；去除該 二之一邊緣區域内之該罩幕層；於該罩幕層上定義出複 ^蝕刻開口；以及利用該等蝕刻開口對該基板進行一蝕 二作，藉由已去除該邊緣區域之該罩幕層之影響，進而 運成均勻蝕刻出複數個深溝渠構造。Page 4 457581 V. Phenomenon of Invention (2) 丨 By adjusting the system of gas flow, etc., in some cases, especially the sharp decrease, it is necessary to maintain or even (Critical is 7 microns), the product. However, it is small, and the process of deepening the load effect is more convenient and effective. It is the case of this case. Although the scope of the material and the limit of the material is also accompanied by the size of the bond, the surface is generally reduced, so that the above provides an effect in etching. Round edges The engraved width is often larger than the desired line width. Process parameters, such as reaction chamber pressure and power output, can be improved to some extent. However, because the device can not improve this effect to our acceptable when the component size is shrinking, the distance between deep trenches, but in order to meet the memory capacity requirements, increase the definition of the mask pattern used in the deep trench. Dimension (referred to as CD) and the depth of the deep trench (measured to provide a large enough critical dimension (CD) after the completion of the deep trench will increase the distance between the trench and the trench will increase the time of the engraving, "The seriousness of the shape causes the shortcomings in the short-circuit between the deep trench and the deep trench capacitor." Therefore, the main purpose of the method to control the load development in the process of silver engraving of deep trench. A method for trench construction, including the following steps: providing a substrate; forming a mask layer on the substrate; removing the mask layer in the edge area of the two; and defining a complex etch on the mask layer Openings; and using the etching openings to perform one etching operation on the substrate, and by removing the effect of the mask layer in the edge area, the substrates are uniformly etched to form a complex substrate. A deep trench structure.
4 6 '7 5 8 t 五、發明說明（3) 根據上述構想’均勻蝕刻深溝渠構造之方法中該基板 係為一妙基板。 根據上述構想’均勻蝕刻深溝渠構造之方法中該罩幕 層係包含’一氮化矽層’形成於該矽基板上；以及一氧化 矽層’形成於該氮化矽層上。 根據上述構想’均勻蝕刻深溝渠構造之方法中該罩幕 層更包含一抗反射層，形成於該氧化矽層上。 根據上述構想，均勻蝕刻深溝渠構造之方法中去除該 基板邊緣區域内之該罩幕層以及定義出複數個蝕刻開口之 =驟係包含：於該罩幕層上形成一光阻層；對該基板邊緣 區域上之光阻層進行一邊緣串珠移除（Edge Bead Removal ’ EBR)製程以及對該光阻層進行微影製程，用以 去除基板邊緣區域内以及該等蝕刻開口上方之光阻層；以 及對該罩幕層進行蝕刻，進而去除該基板邊緣區域内之該 罩幕層以及定義出複數個蝕刻開口。 根據上述構想’均勻蝕刻深溝渠構造之方法中去除該 基板邊緣區域内之該罩幕層以及定義出複數個蝕刻開口之 ^驟係包含：於該罩幕層上形成一光阻層；對該基板邊緣 區域上之光阻層進行一晶圓邊緣曝光（Wafer Edge Exposition)製程以及對該光阻層進行微影製程，用以去 除基板邊緣區域内以及該等蝕刻開口上方之光阻層；以及 對該罩幕層進行蝕刻，進而去除該基板邊緣區域内之該罩 幕層以及定義出複數個蝕刻開口。 根據上述構想，均勻蝕刻深溝渠構造之方法中所完成4 6 '7 5 8 t V. Description of the invention (3) According to the above-mentioned method, the substrate is a wonderful substrate in the method of uniformly etching a deep trench structure. According to the above-mentioned method of the method of uniformly etching a deep trench structure, the mask layer includes a silicon nitride layer formed on the silicon substrate; and a silicon oxide layer is formed on the silicon nitride layer. According to the above method, in the method of uniformly etching a deep trench structure, the mask layer further includes an anti-reflection layer formed on the silicon oxide layer. According to the above-mentioned concept, in the method of uniformly etching the deep trench structure, removing the mask layer in the edge region of the substrate and defining a plurality of etching openings = step includes: forming a photoresist layer on the mask layer; The photoresist layer on the substrate edge area is subjected to an edge bead removal (EBR) process and a photolithography process is performed on the photoresist layer to remove the photoresist layer in the edge area of the substrate and above the etching openings. And etching the mask layer, thereby removing the mask layer in the edge region of the substrate and defining a plurality of etching openings. According to the above-mentioned method of uniformly etching the deep trench structure, the steps of removing the mask layer in the edge region of the substrate and defining a plurality of etching openings include: forming a photoresist layer on the mask layer; Performing a wafer edge exposure (Wafer Edge Exposition) process on the photoresist layer on the substrate edge region and performing a lithography process on the photoresist layer to remove the photoresist layer in the substrate edge region and above the etching openings; and The mask layer is etched, thereby removing the mask layer in the edge region of the substrate and defining a plurality of etching openings. According to the above idea, completed in the method of uniformly etching the deep trench structure
a t) 7 5 8 1 五、發明說明（4) 之該等深溝渠構造係提供後續之深溝渠電容之製作。 根據上述構想，均勻蝕刻深溝渠構造之方法中該基板 邊緣區域係約為晶圓周緣向圓心内縮約1公釐（m m)之區 域。 簡單圖式說明 本案得藉由下列圖式及詳細說明，俾得一更深入之了 解： 第一圖（a ) ( b) ( c ) (d ):其係於晶圓上形成深溝渠之習用技 術手段之製程示意圖。 第二圖（a) ( b) ( c ) (d ):其係於晶圓上形成深溝渠之本案較 佳實施例之製程示意圖。 本案圖式中所包含之各元件列示如下： 氮化矽層1 1 光阻層1 3 矽基板2 0 罩幕層21 氧化矽層2 1 2 開口 231 矽基板1 0 氧化矽層1 2 開口 1 3 1 邊緣區域2 0 1 氮化矽層2 11 光阻層2 3 較佳實施例說明a t) 7 5 8 1 V. The deep trench structure of the description of the invention (4) provides the subsequent production of deep trench capacitors. According to the above-mentioned concept, in the method of uniformly etching the deep trench structure, the edge region of the substrate is a region of about 1 mm (m m) that is reduced from the wafer periphery to the center of the circle. Simple diagram description This case can get a deeper understanding through the following diagrams and detailed descriptions: First picture (a) (b) (c) (d): It is the custom of forming deep trenches on wafers Process schematic diagram of technical means. The second figure (a) (b) (c) (d): It is a schematic diagram of the process of the preferred embodiment of the present invention in which a deep trench is formed on a wafer. The components included in the drawings in this case are listed below: Silicon nitride layer 1 1 Photoresist layer 1 3 Silicon substrate 2 0 Mask layer 21 Silicon oxide layer 2 1 2 Opening 231 Silicon substrate 1 0 Silicon oxide layer 1 2 Opening 1 3 1 Edge region 2 0 1 Silicon nitride layer 2 11 Photoresist layer 2 3 Description of preferred embodiments
457581 五、發明說明（5) -- 巨=參見第二圖（a ) ( b ) ( c ) ( d )，其係於晶圓上形成深溝 乐之本案較佳實施例，其中第二圖（a)係表示出於一矽基 板2 0上依序形成—罩幕層2丨（本實施例包含有一氮化矽層 、.二氧化矽層21 2)以及一光阻層23後，再以一微影製 ，來對j光阻層23定義出複數個開口231 。而罩幕層21亦 可更包含一形成於氧化矽層212之上之抗反射層（圖中未顯 二出）。曰並且以邊緣串珠移除（Edge Bead Rem〇val ，EBR) 製程或是晶圓邊緣曝光（Wafer Edge Exp〇si1；i〇n)製程來 除去該基板20邊緣區域201上之該光阻層23。而在本實施 例中，該邊緣區域2〇1為晶圓周緣向内約}公釐之區 域，可視晶圓圖案負載效應而調整。而第二圖（b)則表示 出依^序對該等開口231與該邊緣區域2〇1中所露出之罩幕層 2j (、氮化矽層2 1 1與氧化矽層2丨2 )進行蝕刻，用以形成製作 冰溝渠構造所需之罩幕（1^31〇。第二圊（c)即表示出將殘 餘之光阻層23去除後所完成之罩幕（mask)形狀，此時再利 用此罩幕（mask)對矽基板20進行蝕刻動作，最後便形成如 第二圖（d )中所示之深溝渠構造，而可進一步提供給後續 深溝渠電容製程運用。 而在上述本案所揭露之深溝渠蝕刻過程中，由於吾人 利用邊緣串珠移除（Edge Bead Rem〇val ，EBR)製程或是晶 圓邊緣曝光（Wafer Edge Exposition)製程來除去該基板 邊緣區域2 0 1之罩幕層2 1 ，使得晶圓邊緣之反應環境改 變至與晶圓中央區域之反應環境相類似，進而使晶圓 (Wafer)中央與邊緣之蝕刻效應均勻化，避免在晶圓457581 V. Description of the invention (5)-Giant = see the second figure (a) (b) (c) (d), which is the preferred embodiment of the present case to form a deep groove on the wafer, where the second figure ( a) indicates that the mask layer 2 is formed sequentially on a silicon substrate 20 (this embodiment includes a silicon nitride layer, a silicon dioxide layer 21 2), and a photoresist layer 23, and then A lithography system is used to define a plurality of openings 231 for the j photoresist layer 23. The mask layer 21 may further include an anti-reflection layer formed on the silicon oxide layer 212 (not shown in the figure). The photoresist layer 23 on the edge region 201 of the substrate 20 is removed by an Edge Bead Removal (EBR) process or a wafer edge exposure (Wafer Edge Exposi1; iOn) process. . However, in this embodiment, the edge region 201 is an area inwardly about} millimeters from the wafer periphery, which can be adjusted according to the wafer pattern loading effect. The second figure (b) shows the openings 231 and the mask layer 2j (the silicon nitride layer 2 1 1 and the silicon oxide layer 2 2) exposed in the edge region 201 in order. Etching is performed to form a mask (1 ^ 31 °) necessary for the fabrication of the ice trench structure. The second step (c) indicates the shape of the mask completed after the residual photoresist layer 23 is removed. When this mask is used, the silicon substrate 20 is etched, and finally a deep trench structure as shown in the second figure (d) is formed, which can be further provided to the subsequent deep trench capacitor manufacturing process. In the deep trench etching process disclosed in this case, because I used the Edge Bead Removal (EBR) process or the Wafer Edge Exposition process to remove the cover of the substrate edge region 201 The curtain layer 2 1 makes the reaction environment at the edge of the wafer to be similar to the reaction environment at the center of the wafer, so that the etching effect at the center and edge of the wafer is uniformized, avoiding the wafer
457581 五、發明說明（6) (W a f e r )邊緣因圖案負載效應過大而產生深溝渠電容間短 路之製程缺陷產生，進而可有效控制深溝渠蝕刻過程中之 負載效應，達成本案發展之主要目的。 本案發明得由熟習此技藝之人士任施匠思而為諸般修 飾，然皆不脫如附申請專利範圍所欲保護者。457581 V. Description of the invention (6) (W a f r) The process defect of the short trench between capacitors in the deep trench caused by the pattern load effect is too large, which can effectively control the load effect in the process of deep trench etching and achieve the main purpose of the development of the case. The invention in this case can be modified by people who are familiar with this technique, but they can all be protected as intended by the scope of patent application.
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