TW451476B - Manufacturing method of integrated circuit capacitor having self-aligned contact structure - Google Patents

Abstract

The present invention discloses a method to form capacitor, which is suitable for high density DRAM circuit. The method comprises: form a silicon dioxide layer on the integrated circuit wafer having devices. Form a contact window in the silicon dioxide layer, whose top portion is larger than the bottom portion. Then form a polysilicon layer on the sidewall and bottom portion of the contact window, form a silicon dioxide side wall layer on the polysilicon layer to leave a center hole in the contact window. Next, fill polysilicon into this center hole for forming a center cylinder, and the bottom portion of the contact window electrically contacts the polysilicon layer. Then etch the side wall layer of silicon dioxide, deposit a silicon dioxide dielectric capacitor layer on the substrate to cover the polysilicon cylinder and polysilicon layer. A polysilicon layer is then formed on the second silicon dioxide layer to form the second capacitor plate. In the first embodiment of the present invention, a semi-spherical grain (HSG) polysilicon layer is formed on the polysilicon layer to form the first capacitor plate for increasing the capacitance.

Description

451476 V. Description of the Invention (1) [Field of Invention 1] The present invention relates to a method for manufacturing a capacitor in an integrated circuit, and more particularly, to a capacitor suitable for use in a dynamic random access memory circuit. [Background of the Invention] In a dynamic random access memory (dram) circuit, a capacitor having a sufficient amount of valley is a key element. As the size of the dram circuit shrinks, it becomes more difficult to make a dram capacitor with sufficient capacitance to be allocated to each DRAM memory cell (cei 1) in the space. U.S. Patent No. 6,049,101 describes a method for making a DRAM capacitor. The capacitor opening is first formed above the base node position, and then a conductive material is formed in the capacitor opening and electrically connected to the node position. This capacitor is made of a structure containing conductive materials and insulating materials. [Summary of the Invention] The main purpose of the present invention is to reveal the formation of a capacitor structure that increases the capacitance in the integrated circuit area. The vector method β. In order to achieve the above purpose According to the present invention, a first silicon dioxide layer is formed on an integrated circuit wafer on which components and node positions are formed. A contact window is formed in the first silicon dioxide layer to expose a portion of a node position. The top of the contact window is larger than its bottom. Form self-aligned contacts in the substrate through contact windows

v »5l6-565 1TWF.ptd page 4 451476 V. Description of the invention (2) The contactor is on the side wall of the contact window.卩 Forms a polycrystalline silicon layer. Next, a silicon dioxide sidewall layer is formed on the polycrystalline silicon layer, so as to leave a central hole in the contact window. The central hole is connected to a α ^ There is polycrystalline silicon to form a central pillar, and at the bottom of the contact window, it is electrically connected to the polycrystalline stone layer 4 * y ± m JQ & & ** The electric contact is made by the electric current. Then the side wall layer of the dioxide is etched with the gas phase hydrofluoric acid, leaving a polycrystalline stone pillar in the contact window and a polycrystalline silicon layer on the side and bottom of the contact window. Then, a first capacitor plate is formed. Then, a second silicon dioxide layer is deposited on the substrate to cover the polycrystalline silicon pillars and the polycrystalline silicon layer in the contact window, leaving a cavity surrounding the polycrystalline silicon pillar. A polycrystalline silicon layer is formed on the second silicon dioxide layer to form a second capacitor plate. The polycrystalline silicon forming the second capacitor plate fills the side cavities. In an example only, the second silicon dioxide layer is deposited Previously, a hemispherical granular (Η%) polycrystalline silicon layer was formed on the polycrystalline silicon constituting the first capacitor plate. HSG polycrystalline silicon will increase the capacitance of the capacitor. [Simplified description of the diagram] Figure 1 Shows a cross section of a semiconductor substrate section with a first dielectric layer formed on the substrate section and a contact window formed in the first conductive layer. Figure 2. Figure 2 shows a cross-sectional view of the substrate section after the first conductive layer has been removed from the top of the first dielectric layer. Figure 3 shows that the second dielectric layer has been deposited and remains in the contact window. Sectional view of the base section of the next central hole. Figure 4 shows a cross-sectional view of the base section after the second dielectric layer has been etched in a vertical anisotropy to form a dielectric sidewall layer.

〇516-5651TWFptd Page 5 451476 V. Description of the invention (3) The fifth circle shows a sectional view of the base section after the second conductive layer has been deposited to fill the center hole of the contact window. Figure δ shows the base area of the first capacitor plate formed by the first conductive layer and the second conductive pillar on the sidewall and bottom of the contact window after the second conductive layer above the top surface of the first dielectric layer has been removed. Sectional cross section. Figure 7 shows a cross-sectional view of the base section after the dielectric sidewall layer has been etched away. Figure 8 shows a cross-sectional view of the substrate section after the third dielectric layer and the third conductive layer have been deposited to complete the capacitor.

Figure 9 shows a cross-sectional view of the base section where a HSG polycrystalline dream layer is deposited after the dielectric sidewall layer has been etched. FIG. 10 shows a cross-sectional view of a substrate section after a third dielectric layer and a third conductive layer have been deposited on a first capacitor plate having a HSG polycrystalline silicon layer deposited thereon. [Symbol description] 10 ~ semiconductor substrate; 12 ~ self-aligned contact area; 14 ~ first dielectric layer; 16 ~ contact window; 17 ~ node hole; 18 ~ first conductive layer; 2 ~~ dielectric Layer, 22 ~ + th conductive layer; 24 ~ side cavity; 26 ~ third dielectric layer; 2R third conductive layer. [Explanation of the preferred embodiment] The method of manufacturing a capacitor according to the preferred embodiment of the present invention will be described below with reference to FIG. 8. Figure 1 shows. Out—formed with elements (not shown)

^ 05I6-565iTWFptd Page 6 45 1 47 6 Description of the Invention A section view of a semiconductor substrate in 10 sections. Typically, but not necessarily, the above-mentioned device acts as a dynamic random access memory (DRAM) circuit. Using a standard deposition technique, a first dielectric layer, such as silicon dioxide or other suitable dielectric material, is formed on the semiconductor substrate 10. The thickness of the first dielectric layer is about 2000 Angstroms (A) to 1 2000 Angstroms. (A). A standard engraving technique is used to form a contact window 16 in the first dielectric layer. As shown in Fig. I, the top of the contact window is greater than its bottom. The typical diameter of the bottom of the contact window is between Angstrom and MM Angstrom.

In the substrate region, a portion of the contact window ^ exposed from the semiconductor substrate ^ forms a contact region. A self-aligned contact region 12 is then formed in the substrate by an ion implantation method. Next, as shown in FIG. I, a conductive layer 18, such as doped or undoped polycrystalline silicon, is formed on a substrate using a deposition method, such as low-pressure chemical vapor deposition (LPCVD), and covered on The contact window 16 has sidewalls and bottoms and has a thickness between about 150 angstroms and 3,000 angstroms. Then, as shown in FIG. 2, using a method such as chemical mechanical polishing, the first conductive layer 18 portion of the upper surface of the first dielectric layer 14 is removed, so that the first conductive layer is left on the sidewall and bottom of the contact window Floor.

As shown in FIG. 3, the second dielectric layer 20, such as silicon dioxide or other suitable dielectric material, is 'formed on a semiconductor substrate using a method such as LPCVD', and is thus formed on top of the first dielectric layer 14 and A second dielectric layer 20 is formed on the dead conductive layer 18 on the sidewall and bottom of the contact window M. :; 6: All the walls are not etched with vertical anisotropic etching to etch the second dielectric layer 20 to leave the dielectric sidewall layer on the first conductive layer 18 formed on the sidewall of the contact window. Vertical anisotropic etching may include a plasma enhanced anisotropic etching. Down

〇516-565] TWp.ptd Page 7 451476

V. Description of the invention (5) The anisotropic truncation removes the second dielectric layer from the upper surface of the first dielectric layer 14 and the bottom of the contact window. A central hole 17 is left in the contact window.

As shown in Fig. 5, the second conductive layer 22, such as doped or undoped polycrystalline silicon, is formed on the substrate using a deposition method such as LPCVD and has a sufficient thickness to fill the central hole 17. As shown in FIG. 5, the second conductive layer 22 and the first conductive layer 18 are in a rational and electrical contact with each other at the bottom of the contact window or at the bottom of the central hole. Next, as shown in FIG. 6, a method such as chemical mechanical polishing is used to 'remove the second conductive layer 22 above the top surface of the first dielectric layer 14' so as to leave the second conductive layer 22 in the central hole 17 to form — Second conductive post 22. As shown in Fig. 7, the dielectric sidewall layer is etched away using a method such as hydrofluoric acid (HF). The first conductive layer 18 on the sidewall and bottom of the contact window, the second conductive pillar 22 in the center of the contact window, and the side cavity 24 surrounding the second conductive pillar 22 are left. As shown previously, the second conductive pillar 22 makes mechanical and electrical contact with the first conductive layer 18 on the sidewall and bottom of the contact window. The first conductive layer 18 and the second conductive pillar 22 on the sidewall and the bottom of the contact window form a first capacitor plate.

As shown in FIG. 8, a first capacitor plate i formed by the first conductive layer 18 and the second conductive layer layer 22 is formed. As a capacitor dielectric layer, the third dielectric layer 26 ′ is formed as Silicon dioxide or similar is formed on the substrate. The third conductive material layer 2 8 ′, such as doped or undoped polycrystallite, is deposited using a method such as

LpCVD 'is then formed on the substrate to bind into the side cavity 24 and form a third conductive layer 28 on top of the third dielectric layer 26. The third conductive layer 28 forms the second or upper capacitor plate.

4 5 1 47 6 V. Description of the invention (6) Another preferred embodiment of the present invention is shown in FIG. 7, FIG. 9 and FIG. The first and second conductive layers in this embodiment must be doped or undoped polycrystalline silicon. This method walks the dielectric sidewall layer through the etching step exactly as described in the previous embodiment, as shown in FIG. As shown in Figure 9, a semi-granular (HSG) polycrystalline sand layer is formed on the polycrystalline silicon and polycrystalline silicon pillars 22 on the side walls and bottom of the window. As shown in FIG. 10, in order to form the capacitor dielectric layer 7 " ^ " electrical layer M on the first capacitor plate composed of the crystalline silicon pillars 22 and the polycrystalline silicon layer 22 on the sidewall and bottom of the contact window. , Such as dioxide or similar, and then formed on the substrate. A third conductive layer 28, such as doped or undoped polycrystalline silicon, is deposited using a method, such as LPCVD, which is then formed on the substrate to fill the side holes 24 and form a third on top of the third dielectric layer 26 Conductive layer ⑼. The third conductive layer forms a second or upper capacitor plate. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to the definition in the attached patent application park.

Claims (1)

45 1 47 6 6. The scope of the patent application layer; the car is exposed to the substrate and its side walls, and the top of the substrate is a method of forming a capacitor, including: providing a semiconductor substrate on which elements are formed; and forming a first dielectric on a semiconductor substrate. A contact window is formed in the first dielectric layer, and a contact area 'where the contact window has a bottom and a top is larger than its bottom; a wide and conductive sound is formed on the sidewall and the bottom of the contact window. The second dielectric layer a ** lL,, ^, ≦ on the first conductive layer. A dielectric sidewall layer is formed on the sidewall, and a center hole is left in the contact window to fill the first hole in the center hole. Two conductive materials are used to form a conductive center pillar, so that the contact window is completely filled by the first conductive layer, the dielectric sidewall layer, and the center pillar, wherein the center frame and the first conductive layer are in the Contacting the bottom of the contact window; removing the dielectric sidewall layer; forming a third dielectric layer on the semiconductor substrate to cover the first conductive layer and the center ridge, and leaving a side hole surrounding the center pillar; and The third dielectric A third conductive layer is formed on the layer to fill the side hole as a top capacitor plate. 2. The method according to claim 1 in the patent specification, wherein forming the first conductive layer on the sidewall and the bottom of the contact window further includes: forming the contact window in the first dielectric layer. After that, the first conductive layer is deposited on the substrate, so as to form the first conductive layer on the sidewall and bottom of the contact window on top of the first dielectric layer; and removing the first conductive layer above the top of the first dielectric layer. First conductive layer without removal ^ 05l6-5651TWF'ptd Page 10 VI. The scope of the patent application is on the side or bottom of the contact window 3. If the patent application is mechanical grinding to remove the first — to remove 'the 4. electric layer, 5. electric layer, 6. wall layer Change the second side wall and make the bottom of the touch window 7. Isotropic 8. Electrical side wall 9. Electrical layer and removed compound crystal 'and the contact window side wall as claimed in the patent application and the second conductive layer as applied The second application includes: a first dielectric layer, a dielectric layer, and a bottom; and a second dielectric application with a vertical anisotropic portion. The patent application includes etching. The patent application claims that the second conductive layer removes the dielectric sidewall silicon layer, thereby forming any of the first conductive layer in the hemispherical part of the stem. The method according to item 2, wherein the first conductive layer above the top of the chemical dielectric layer is used instead of the first conductive layer at any bottom. The method according to item 1, wherein the first conductive layer and the third conductive layer are polycrystalline silicon. The method according to item 1 of the patent scope, wherein the first dielectric layer and the third dielectric layer are silicon dioxide. The method described in the first item of the patent model garden, wherein after the contact window is formed on the dielectric side, is formed on the substrate and is formed on top of the first dielectric layer, and the contact window is etched to remove the top of the first dielectric layer. And the electrical connection layer, thereby leaving the dielectric sidewall layer. The method according to item 6, wherein the vertical anisotropic plasma etching is performed. For the method described in item 1, scorching money. The method described in item 1: is a polycrystalline stone and further includes a layer of __ which is formed into a semi-spherical particle on the substrate, the top of the first dielectric layer, and the first conductive layer in the shape of a granular compound ♦ ; With & which removes the introduction where the first guide 〇516-5651TffFptd Page 11 451476 6. The scope of the application for a patent removes the hemispherical granular polycrystalline silicon on top of the first dielectric layer without removing the first conductive layer and the central pillar of hemispherical granular polycrystalline silicon . 10. The method according to item 9 of the scope of patent application, wherein chemical mechanical polishing is used to remove the hemispherical granular polycrystalline silicon on top of the first dielectric layer without removing the first conductive layer and the central pillar. Hemispherical granular polycrystalline silicon. 11. The method according to item 1 of the scope of patent application, wherein the element formed in the semiconductor substrate forms a dynamic random access memory circuit. 12. A method of forming a capacitor, comprising: providing a semiconductor substrate on which an element is formed; forming a first dielectric layer on the semiconductor substrate, wherein the bottom of the first dielectric layer is in contact with the substrate; A contact window is formed in a dielectric layer, thereby exposing a contact area of the substrate, wherein the contact window has a bottom, a top, and a side wall, and the top is larger than the bottom; above the first dielectric layer, the side wall of the contact window Forming a first conductive layer on the bottom; removing the first conductive layer above the first dielectric layer, and leaving the first conductive layer on the sidewall Λ and the bottom of the contact window; on the first dielectric The top of the layer and the first conductive layer form a second dielectric layer; the second dielectric layer on top of the first dielectric layer and the bottom of the contact window is etched using vertical anisotropy, thereby forming a dielectric sidewall Layer and leave a center-hole in the contact window; Fill the center hole with a second conductive layer to form a conductive center W516-565m "F * ptd Page 12 451476 VI. Patent Application _ 枉, and thereby make the contact window completely filled with the first conductive layer, the dielectric sidewall layer, and the center pillar, where the center枉 is in contact with the first conductive layer at the bottom of the contact window; etching away the dielectric sidewall layer; forming a third dielectric layer on top of the first dielectric layer and leaving one side on the third dielectric layer Forming the first / conducting layer and the central pillar-shaped cavity surrounding the central pillar; and a third conductive layer and filling the cavity to serve as an upper capacitor plate. b 1 3_ The method described in item 12 of the scope of the patent application, wherein the rubber is mechanically removed to remove the first conductive layer on top of the first dielectric layer, leaving the first conductive layer on the sidewall and the bottom of the contact window. Layer ° 1 4. The method described in item 12 of the scope of the patent application, wherein the conductive layer, the second conductive layer, and the third conductive layer are polycrystalline silicon. 15. The method according to item 12 of the scope of the patent application, wherein the second dielectric layer, the second dielectric layer, and the third dielectric layer are silicon dioxide. 16. The method according to item 12 of the scope of the patent application, wherein the vertical anisotropic etching includes an anisotropic plasma etching. 17. A method according to item 12 of the scope of patent application, wherein removing the dielectric sidewall layer comprises vapor phase hydrofluoric acid etching. 18 · The method as described in item 12 of the scope of the patent application, wherein the first conductive layer and the second conductive layer are polycrystalline silicon and further include: after etching the dielectric sidewall layer, Forming a 'hemispherical granular polycrystalline spar' layer on the substrate, thereby forming a hemispherical granular polycrystalline silicon on top of the first dielectric layer, the 'conducting layer' and the central pillar; and 05! 6-5651TWF'Ptd Page 13 451476 VI. Patent application scope Remove the hemispherical granular polycrystalline silicon on top of the first dielectric layer without removing the side first conductive layer and the hemispherical shape on the center pillar Granular compound crystals. 19. The method according to item 8 of the patent application scope, wherein chemical mechanical polishing is used to remove the hemispherical granular polycrystalline silicon on top of the first dielectric layer without removing the first conductive layer and the center pillar. Hemispherical granular polycrystalline spar. 20. The method of claim 12 in which the element formed in the semiconductor substrate forms a dynamic random access memory circuit. 4516-5651TWF-pu Page 14