TW451475B - Manufacturing method of capacitor with dielectric pillar - Google Patents

Abstract

The present invention discloses a manufacturing method of capacitor. The method comprises: etching an opening in an inter-dielectric layer to expose the contact area below the inter-dielectric layer; next, forming a conductive plug at the bottom of the opening to electrically connect to the contact area; then, forming a conductive sidewall layer on the sidewall of the opening by depositing an uniform conductive layer and anisotropic etching, and defining a channel in the opening by the sidewall layer; next, filling dielectric material into the channel to form a dielectric pillar, and removing the conductive sidewall layer adjacent to the dielectric pillar for thereby exposing the lateral surface of the dielectric pillar; and finally, sequentially forming first and second capacitor plate structures in the opening and on the lateral surface of the dielectric pillar, and a capacitance dielectric layer between the first and second capacitor plate structures for thereby completing the manufacture of the capacitor.

Description

45 147 5 V. Description of the Invention (1) [Field of the Invention] The present invention relates to semiconductor manufacturing technology, and more particularly to a method for manufacturing a capacitor, which is suitable for a memory cell (DRAM cel 1) of a state random access memory. ). "&BACKGROUND; [Inventive Background] Dynamic Random Access Memory (DRAM) has been widely used in electronic components." With the evolution of process technology, the density of DRAM has also continued to increase, and more than one billion can be made in 2000. ⑽am element of memory unit (1 gb). The increase in the density of memory cells is due to the increased resolution of lithography and directional plasma etching, resulting in shrinking component sizes: the result of two daggers; however, the reduction in components will make the effective area of the capacitors two and therefore must be maintained (Or increase) the capacitance of the capacitor in the surface element is more difficult. Save 1 bit: Gu Ji Yi single chip includes a field effect transistor and a capacitor that can store 1 bit of redundant data as a memory element, cry ϊίΚϊίΠ, the base! Trench capacitors can also be sized and L-type capacitors. In order to keep the DRAM chip reasonably well-equipped, the unit's share of the chip is reduced as much as possible. Each memory size is reduced to make it; it is difficult to follow the size of the memory unit. Therefore, how can the storage capacitors in Weishui ^ hehe become more and more difficult to store the electric capacity, while maintaining a high enough storage area while maintaining a high enough storage capacity? The main method can be borrowed = the method of changing the valley structure Reach, pack

1 47 V. Description of the invention (2) A storage capacitor with three degrees of space, such as a trench or stacked two capacitors. The method of the present invention is related to the formation of a three-dimensional storage capacitor. [Summary of the Invention] The object of the present invention is per unit area. The object of the present invention is to etch out the bottom of the opening from the dielectric layer according to the present invention, and then form a channel by depositing an opening sidewall. Connect the post 'and remove its lateral surface. In order, the first and second electrical layers are formed in order to complete the electrical operation. In order to make the present invention easier to understand, the following detailed description is as follows:

One of them is to provide a storage capacitor manufacturing field with two quasi-contacts, one preferably, an open conductive plug, and a uniform conductive side. After the dielectric column, the above list of two capacitor containers is more clear.] The high capacitance is the lifting structure. In the embodiment, it is made of an exposed plug and an upper conductive wall layer, and an adjacent open middle plate structure in the channel. And other best implementations are provided and have the following contact layers and non-mains, and thereby fill a conductive side and dielectric, as well as the purpose, example, and contact area of the larger steps to store electricity for electrical isotropy The dielectric wall layer of the dielectric sidewall layer, the column transversely intersects the two features, and the electrode table includes: area. The etch back of the connection is shaped in the opening to expose the surface and the advantages. In one, at the moment, it is defined as a dielectric dielectric pillar in. It is more clear in terms of capacitance dielectric. A series of cross-sectional diagrams are used to illustrate the first preferred embodiment of the present invention.

Page 5 451475 V. Description of the Invention (3) Example The process of making a DRAM capacitor. Figures 10 to 14 are a series of cross-sectional views' for explaining the flow of manufacturing a DRAM capacitor in the second preferred embodiment of the present invention. [Symbol description] 10 ~ semiconductor substrate; 12 ~ insulating oxide; 14,16 ~ diffusion area; 18,20 ~ conductor; 2 ~ 2 oxide layer; 2 ~ 4 polycrystalline silicon layer; 2 ~ 6 metal silicide '28 ~ sidewall spacer; 30 ~ top cover layer; 32 ~ first dielectric layer; 34 ~ contact window, 36 ~ contact window sidewall; 38 ~ conductive layer; 40 ~ conductive plug; 42 ~ conductive layer; 44 ~ Channel; 46 ~ side wall layer of wire; 48 ~ dielectric layer; 50 ~ lateral surface of dielectric column '52 ~ dielectric column; 54 ~ first capacitor plate structure; 56 ~ capacitor dielectric layer; 58 ~ second capacitor plate structure . [Embodiment] A second preferred embodiment for fabricating a DRAM capacitor according to the present invention will be described below with reference to FIG. First, please refer to FIG. 1. The capacitor system of the present invention is formed on a semiconductor substrate 10. As shown in FIG. In the following description, the term "semiconductor substrate" includes components formed on a semiconductor wafer and various coatings covering the wafer; the term "substrate surface" includes all components of a semiconductor wafer. The top layer of the exit, such as the surface of the silicon wafer, the insulation layer, etc. ^ As shown in FIG. 1, an insulating oxide 12 is provided on the substrate 10 to isolate the f region, and diffusion regions 14, 16 are formed in the active region. There are a pair of wires 20 on the substrate, which form part of the AM circuit. The wire has a standard structure ‘including the oxide layer 2 2. The polymorphite layer

451475 V. Description of the invention (4) 24. Metal silicide 26. In addition, the wires 18, 20 may further include respective side wall spacer layers 28 and a protective cap layer 30. A first dielectric layer 32 is formed on the substrate 10 and the wires 18 and 20 as an internal dielectric layer (ILD), which preferably has a flattened surface. The first dielectric layer 32 generally includes at least one oxide layer, such as a borophosphosilicate glass (BPSG) layer. Next, a lithography and etching process is used to define a contact window 34 on the first dielectric layer to expose the contact area 15 underneath. The contact window 34 can be formed in a self-aligned manner. The layer 30 and the sidewall layer 28 serve as an etch stop layer to achieve the purpose of self-alignment. This etching step can be achieved by a conventional paste-etching process, such as reactive ion etching (RIE). The storage electrode of the capacitor is connected to the 15-shaped window 34 of the contact area under the opening, and the layer is deposited. A layer of conductive material 38 that fills the contact tooth M conductive layer 38 is preferably made of in-situ doped holmium, and then the conductive layer 38 is comprehensively recalled. The conductive material at the bottom of port 34 is shown in Figure 2. So!:, To leave the blessing / open-conductive plug 40 and the contact area with the bottom > The plug 40 preferably has a flat connection. The conductive plug contacting process can be removed in a successful manner by, for example, removing the conductive layer 38; the relatively vertical sidewall 36. Exit the contact window 3 4 Mostly refer to Figure 3, then connect η m, -ϊ & and the contact window. As shown in the figure, the thickness of the isocratic layer 42 on the dielectric layer 32 is not more than 4 5 1 47 5 5. Description of the invention (5) Fills the entire contact window 34, so a channel is left in the center of the contact window 34 44. The conductive layer 42 is preferably an in-situ doped polycrystalline stone. Referring to FIG. 4 ', the conductive layer 42 is etched back. ^ The conductive layer 42 is etched back using an anisotropic reactive ion etching process to directly expose the surface of the first dielectric layer 32. Finally, the sidewall 36 of the remaining conductive bank 24 is a sidewall spacer 46. S ^ Referring to FIG. 5, a second dielectric layer is deposited on the substrate and fills the entire channel 44. Suitable materials for the second dielectric layer 48 include silicon nitride and oxidative breakdown ', but any other suitable dielectric material may be used. Please refer to FIG. 6, by using chemical mechanical polishing (CMp) or etch-back, the second dielectric layer 48 above the first dielectric layer 32 is removed, leaving only the part located in the channel 44, so that the remaining The dielectric material is formed within the contact window. Please refer to FIG. 7. Using selective etching, remove part (or all) of the conductive sidewall layer 46 to expose the dielectric pillars in the contact window as shown in FIG. 7. The electric pillar 50 is located substantially at the center of the contact window, and is supported by the conductive plug 40 below. It has a lateral outer surface 52 and a certain distance from the side wall 36 of the contact window. The cross-sectional shape of the dielectric pillar 50 may be a circle or a shape other than a circle. In a preferred embodiment of the present invention, the conductive sidewall layer 46 is removed by an etching method having an etching selectivity to the dielectric pillar 50 to expose most of the lateral surface 52 of the dielectric pillar 50. This etching step can be achieved by wet etching or dry etching. Among them, dry contact etching is preferred. When the dielectric pillar 50 contains silicon oxide, this step should have etching selectivity for silicon oxide; when the dielectric pillar 50

Page 8 451475, description of the invention (6) When silicon nitride is included, this step should have silicon nitride with etching selectivity. In addition, it is preferable that this etching step also has an etching selectivity for the dielectric layer 32. Appropriately, the money-cut formula may include at least one of the following: TMAA // 20 mixture, wall acid / hydrofluoric acid mixture, 15% KOH aqueous solution, and the like. ¥ Conductive sidewall layer 4 6 contains multiple crystal dreams, and when this money-carving step needs to be selective to the oxide stone, the following etching recipes can be used: gas-containing etching recipes such as, BC1S, SiCL 'or HC1; The etching formula of bromine is HBr; and a mixture of the foregoing is HBr + Hcl. When the conductive sidewall layer "comprises polycrystalline silicon, and this etching step requires etching selectivity to silicon nitride, it is best to perform this step using a wet etching method. In this embodiment, there is no etching stop layer, so The etching of the conductive sidewall layer 46 is preferably a timed etch. The 50 connection should be formed between the plate structure silicon and the complex po1ys i structure 54 A, and the structure to be removed will be in contact with the reference contact. Window 34 The contact window may include crystalline silicon and 1i con). Next, except for the location. In addition to this window, fill in 8 pictures in the window to form the first capacitor plate structure 54 in the capacitor plate with a dielectric pillar. The structure 54 has a part of the sidewall 36 and the lateral surface 52 of the dielectric post. The first capacitor is any suitable material, and the preferred one is, for example, a combination of hemispherical grains (a combination of hemispherical grains, 1n-situ doping) Miscellaneous HSG, etc. The thickness on the substrate of the first capacitor plate and the contact window is preferably between 30 and 60 t @ ϋ. The deposited material is ground flatly by grinding: the parts other than the teeth 34 are obtained as Figure 8 ^ Post X Step I also cut-back by a dry etching method I, a 1 is removed. Preferably, ere etched back, to be in "barrier material to avoid contact with the material being etched window

451475 V. Description of the invention (7) Carving 'and prevent particles in the etching process from falling into the contact window. After the etching is completed, the photoresist material is removed. = Referring to FIG. 9, next, an electrical and dielectric layer 56 is deposited along the first capacitor plate structure 54, and the material can be a silicon nitride / silicon oxide double-layer structure, silicon oxide / silicon nitride / silicon oxide Three-layer structure, or any other high-dielectric layer, such as Taj5. After that, a second capacitor plate structure 58 is deposited on the capacitor dielectric layer 56 as an upper electrode. The material of the second capacitor plate structure 58 is usually doped polycrystalline silicon or i n-s i tu doped polycrystalline silicon. The resulting structure forms a three-dimensional capacitor ’which has an enlarged electrode surface

The product's capacitance increases the unit area. In other words, since the present invention improves the performance of the power bank, it allows a capacitor of a smaller size to be applied to a DRAM memory cell. Next, "refer to Fig. 10 to Fig. 14", which shows a second embodiment of the present invention, and the same steps are not repeated here. For convenience, the components with the same meaning as those in Figures 1 to 9 will use the previous labels, and similar components will be added to the suffix " a Π.

First, please refer to FIG. 10 ′, which corresponds to the case where the conductive layer 42 is deposited in FIG. 3. Here, a distinction is made by " 42a ". As shown in the figure, 'the conductive layer 42a is deposited on the dielectric layer 32 and the contact window 34, and the thickness is not formed to fill the entire contact window 34. In this way, it is left in the center of the contact window 34 One channel 44. Next, different from engraving the conductive layer 42 in the first embodiment to form a sidewall layer, in this embodiment, a dielectric layer 48a 'is directly deposited on the conductive layer 42a and fills the entire channel 44. Please refer to Fig. 11 'for removing the dielectric layer 48a outside the contact window and page 10 451475 V. Description of the invention (8) — ~~ The conductive layer 42a' only leaves the part located in the contact window. Therefore, the remaining dielectric layer 48a forms a dielectric pillar 50 & within the contact window 34. This step can be achieved by conventional chemical mechanical polishing or dry etching, but other methods can also be used. 'Please refer to FIG. 12' using a selective etching to remove the conductive layer 42a adjacent to the dielectric pillar 50a to expose the dielectric pillar 50a located in the contact window. As shown in the figure, the dielectric post 50a is located approximately at the center of the contact window, and is supported by the remaining conductive layer 42a 'has a lateral outer surface 52a, and has a certain distance from the contact window side wall 36. In this embodiment, the etching of the conductive layer 42a is preferably a time-series engraving, and it is preferable to leave enough conductive material to support the dielectric pillar 50a. Referring to FIG. 13, a first capacitor plate structure 54a is formed in a contact window 34 having a dielectric post 50a. Therefore, a portion of the capacitor plate structure 54a formed is formed on the sidewall 36 of the contact window and the lateral surface 52a of the dielectric post. Referring to FIG. 14, next, a capacitor dielectric layer 56a is deposited along the first capacitor plate structure 54 & then a second capacitor plate structure 58a is deposited on the capacitor dielectric layer 56a as an upper electrode to complete the present invention Fabrication of the capacitor of the second embodiment. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

Claims (1)

^ 51475 VI. Application Patent Scope 1. A method of forming a capacitor on a semiconductor substrate 'includes the following steps: forming an internal dielectric layer on a semiconductor substrate; forming an opening in the internal dielectric layer to expose the substrate A contact region; forming a conductive plug at the bottom of the opening for electrical connection with the contact region; forming a conductive sidewall layer on the sidewall of the opening, and the conductive sidewall layer defining a channel in the opening; A dielectric material is filled in the channel to form a dielectric pillar; at least a part of the conductive sidewall layer is removed to expose the dielectric slave surface; ^ forming a first capacitor plate structure in the opening and the dielectric pillar On the cross section; # a capacitor dielectric layer is formed on the first capacitor plate structure, and a second capacitor plate structure is formed on the capacitor dielectric layer. 2 The method according to item 丨 of the scope of the patent application, wherein the inner layer includes a borophosphosilicate glass layer (BPSG). Electricity 3. The method as described in the scope of the patent application 'in which the etching is performed in a self-aligned manner corresponding to the contact area β 疋 4. The method as described in the scope of the patent application in item 1, wherein the plug is In-situ doped polycrystalline spar layer. 5. Also insert the method as described in item 丨 of the patent application scope, wherein the wall is an i η-s i t u doped polycrystalline stone layer. Thanks Page 12 451475 6. The scope of the patent application where the dielectric pillar is in the dielectric pillar in which the dielectric pillar is in the first electric 'where the capacitor is in' where the capacitor is in which the capacitor is in which the second is in which 6 The material of the method described in the first patent application scope is silicon oxide. 7 · The method described in item 1 of the patent application is made of nitrided sand. 8 · The method described in item 1 of the scope of patent application is located substantially in the center of the opening. Office 9 · If the method described in item 1 of the scope of patent application ', the plate, and the structure are composed of polycrystalite layer or hemispherical granular compound stone 10 · The method described in item 1 of the scope of patent application The material of the electrical layer is Ta205. The electric layer 1 has a double-layer structure as described in item 1 of the scope of the patent application. The electrical layer system is as described in item 1 of the scope of the patent application. The three-layer structure of the chemical structure / chemical gasification / oxidized gas phase is described in the application section 1 of the application. Method 14 is constructed as a doped polycrystalline silicon layer. Step 骒: A method of forming a capacitor on a semiconductor substrate 'includes a lower internal dielectric layer on a semiconductor substrate; an opening is formed in the dielectric layer in the region M, and a contact on the substrate is exposed to become the first In accordance with the f Μ remaining section 2 military layer on the internal dielectric layer, and fill the opening; plug, invite the first conductive layer 'to form a conductive plug at the bottom of the opening to electrically contact the contact area; W 451475 6. The scope of the patent application forms a second conductive layer on the inner dielectric layer and in the opening; the second conductive layer is anisotropically etched to form a conductive sidewall layer on the side wall of the opening, and the side is erected The wall defines a channel in the opening; a dielectric material is filled in the channel to form a dielectric pillar; at least a part of the conductive sidewall layer is removed to expose the lateral surface of the dielectric pillar; forming a first capacitor plate A structure is formed in the opening and the lateral surface of the dielectric pillar; a capacitor dielectric layer is formed on the first capacitor plate structure; and a second capacitor plate structure is formed on the capacitor dielectric layer. 15. The method of claim 14 in which the inner dielectric layer includes a borophosphosilicate glass layer (BPSG). 16. The method according to item 14 of the scope of the patent application, wherein the opening is etched in a self-aligned manner corresponding to the contact area. 1 7. The method according to item 14 of the patent application, wherein the conductive plug is an in-situ doped polycrystalline silicon layer. 1 8. The method according to item 14 of the scope of patent application, wherein the conductive sidewall is an in-si tu doped polycrystalline silicon layer. 19. The method according to item 14 of the scope of patent application, wherein the second conductive layer is etched by a reactive ion etching method. The material of the master is siliconized silicon. 21. The method described in item 14 of the scope of patent application 'wherein the dielectric 20 is the method described in item 14 of the scope of patent application, wherein the dielectric 4 5 147 5 6. Scope of patent application The material of the column is nitriding dream. 2 2. The method according to item 14 of the scope of patent application, wherein the dielectric post is located substantially in the center of the opening. 2 3. A method of forming a capacitor on a semiconductor substrate, comprising the following steps: forming an internal dielectric layer on a semiconductor substrate; forming an opening in the internal dielectric layer to expose a contact area on the substrate, Forming a first conductive layer on the inner dielectric layer and filling the opening; etching the first conductive layer to form a conductive plug at the bottom of the opening for electrical connection with the contact area; forming a second conductive layer Layer on the inner dielectric layer and in the opening; forming a dielectric layer on the second conductive layer and filling the opening; removing the dielectric layer and the second conductive layer above the opening, So that the dielectric layer remaining in the opening forms a dielectric pillar; removing the second conductive layer adjacent to the dielectric pillar to expose the lateral surface of the dielectric pillar; forming a first capacitor plate structure in the opening and the dielectric pillar On the lateral surface; forming a capacitor dielectric layer on the first capacitor plate structure; and forming a second capacitor plate structure on the capacitor dielectric layer. 2 4. The method as described in item 23 of the scope of patent application, wherein the opening is etched in a self-aligned manner corresponding to the contact area. 25. The method according to item 23 of the scope of patent application, wherein the dielectric Page 15 45 1 47 5 6. Scope of patent application The column is located substantially in the center of the opening. Page 16