TW449918B - Method for forming bipolar junction transistor following the high voltage device processing - Google Patents

Abstract

A method for forming bipolar junction transistor following the high voltage device process is provided, which is an integrated process to form the bipolar junction transistor following the high voltage device process. The method comprises the following steps: providing a substrate having a first portion, a second portion and a third portion; forming a first well in the first portion and a second well in the second portion; forming a plurality of field oxide areas on the substrate; forming two third wells in the third portion; then, forming a fourth well in the first well and two fifth wells in the second well; forming a first gate between the two third wells on the third portion and forming a second gate between the two fifth wells on the second portion; next, forming a first spacer on the first gate and a second spacer on the second gate; doping the first portion with the first ions to form the collector/emitter of the first bipolar junction transistor and doping the third portion to form a first source/drain area and keeping a distance between the first source/drain area and the first gate; finally, doping the first portion with the second ions to form the base of the first bipolar junction transistor and forming the collector/emitter of the second and the third bipolar junction transistor; doping the second portion to form a second source/drain area and keeping a distance between the second source/drain area and the second gate.

Description

4 499 1 8 ---- Case No. 88114788_Year Month Date ___ V. Description of the Invention (1) 5 — 1 Field of Invention: The present invention relates to a method for a semiconductor device, and more particularly to a method for a high-voltage device. (High voltage device) process to form a high gain bipolar junction transistor (BJT) method. 5-2 Background of the Invention: A bipolar junction transistor (BJT) is an electronic component with two pn junctions (pn junctions) in a one-dimensional bipolar junction transistor. There are three contacts, which are called emitter, base, and collector. Among them, the base point is the intermediate point of the three BJT contacts. The pn junction formed by the emitter and the base is called the "emitter-base junction" or EB junction; The junction between the pole and the base is called the collector-base junction, or CB junction. If the emitter and collector are ^ -type semiconductors and the base is p-type semiconductor, then this element is called ηρη transistor (npn transistor); if the emitter and collector are P-type semiconductors, the base is: type 1 semiconductor, then this The device is called a pnp transistor. Bipolar junction transistors are usually used as amplifiers (a m p 1 i f y i n g) or switches

44991B _ case number 88114788 _ year month day __ V. Elements of invention description (2) (sw i t c h i n g). The former is to amplify the AC signal, and the latter is to turn on or off the signal. In the development of the deep submicr ο η program in ULSI, because the doping well doping concentration is very high and uniform, the gain of the BJT will change with As a result, the integration process of high-voltage components is also limited by this high-concentration doped well, and some obstacles have occurred in the deep sub-micron process. For the above reasons, it is necessary to develop a method for forming a high-gain BJT, which can be integrated with the process of high-voltage components to facilitate the current and future deep submicron processes (deepsubmicr ο η process). ). 5-3 Objects and Summary of the Invention: In view of the shortcomings of the traditional method of making a high-gain bi-junction junction transistor (BJT) in the above background of the invention, the object of the present invention is The fabrication of the gain bipolar junction transistor is integrated into the manufacturing process of the high-voltage component without reducing its gain. In one embodiment, a substrate having a first conductivity is provided. The substrate includes a first portion, a second portion, and a third portion. Forming a first well having a second conductivity in the first portion, and a second well having a second conductivity;

Case No. 88114788 4 49 918

V. Explanation of the invention (3) The second well is in the second part, in which the mixing of the first well and the second well is equal. A plurality of field oxidation regions are formed on the substrate. This "I" has the fourth conductivity-the fourth ::-: inside, and the second well with the first conductivity, the fifth well in the fourth and fourth wells. The fifth well has the same dopant concentration. A first = is formed on the third part between the third wells, and a 1: is formed on the second part between the wells as a first-partition wall at the first ^ ^ On the side wall, the second gap wall is on the side wall of the second gate electrode. On each side of the fourth well incorporated in the first part, a collector / emitter of a transistor with a double carrier junction is formed. , And the second part to form a first source / drain region, and a distance between the first source and the polar region is maintained, the first conductive 'electricity's younger-ion is doped into the first part to form the first One base of a bipolar crystal is in the fourth well, and a "^-t ^ / _ # JΛ ΛτΛΛ Λ " ::-collector / emitter of the junction transistor is on the other side of the first well The first $ 2 ^, where the base of the first bipolar junction transistor is the second 3 and the rm junction transistor shares a collector / emitter, and the source forms a second source / impulse region, A distance is maintained between the second / and-pole region and the second gate.

4 499 1 8 _Case No. 88114788_ Year Month Date_ V. Cross-sectional view of manufacturing process (4) (BJT). Symbols of the main parts: 10 Substrate 11 Low-concentration η-type well 12 High-concentration η-type well 13 High-concentration ρ-type 丼 14 Source / drain region of η-type metal-oxide semiconductor

^ 4 4 9 9 1 8 _Case No. 88114788_Year Month Day_ V. Description of the invention (5) 15 p-type metal-oxide semiconductor source / drain region 16 emitter / collector 17 emitter / collector 18 base 20 oxide layer 21 pad oxide layer 22 field oxide region 25 gate oxide layer 26 oxide layer 27 spacer 30 silicon nitride layer 40 polycrystalline silicon layer 41 gate 50 photoresist layer 51 photoresist layer 53 photoresist layer 54 light Resistive layer 5 5 Photoresistive layer 60 η-type ion 61 η-he ion 6 2 ρ-type ion 70 Compensation distance

4 4 9 9 18 __ 月 月 _ Case No. 88114788 V. Description of the invention (6) 5-5 Detailed description of the invention: The present invention can be widely applied to the manufacture of 7L pieces of lane-cow conductors, and there is no material limitation. This is based on the example of the manufacture of semiconductor materials from + _ t ^ u 4 Αu ,, Α substrates in the substrate 'its. 1 icon substrate), however, the spirit of the present invention can also be used for different address materials, Materials such as gallium (Galium Arsenide), gallium (German (R)) and other semiconductor materials. The implementation proposed here is I Φ, less M β. In the example, other unrelated other components are omitted. In the example picture, only the components related to Μ Μ __ \ \ 明 m are shown. In order to have a more obvious description of the present invention. In the case of 眚 竑, Λ, 'In the case of the through-yoke, the semiconductor element includes a ρ-type and an η-type region or as early as 7C. Also, 71 is represented by one. In terms of extension, it can be applied to the opposite electrical The system will be described by Bo, but it will not be repeated here. It is very easy to describe the descriptions of the three parties to or from the three places in the same place. It ’s possible to use the simple description of the description. Shi Guanzhong's Cheng Benjian system is in the space of the second dimension, which is a detailed description of an embodiment in July, which is-through the production of high-voltage components to form a high-gain double carrier junction The method of crystals (BJT), the first to the sixteenth diagrams are used to facilitate the understanding of the present invention. Referring to the first figure, first is provided-a substrate 10, on which an oxide layer (0xlde Uyer) 20 has been formed. This substrate 10 is a p-type substrate, which can accommodate at least two semiconductor elements. High pressure n-type metalloxide (

Page 10, 4499] B No. 88114788 Revised in the first month of the year 5. Description of the invention (7) metahoxide-seiniconductor (MOS) transistor (transistor), P-type metal-oxide semiconductor transistor and double-carrier junction Crystal (bip0ar junction transistor, BJT), etc., the order of these three elements in each diagram is from left to right. The oxide layer 2 can be formed by conventional processes such as thermal oxidation. Its thickness is about 100 to 300 angstroms, and it is used as a sacnficial oxide layer to prevent the ion implantation process. Channel effect. See the figure below, a photoresist layer (ph0toSiSi layer) 50 is formed on the oxide layer 20, and an n-type well (nidi) pattern (Pf 已 ern) has been formed thereon. The pattern is located in the region where the p-type rib 5 transistor is connected to the bipolar transistor or the n-type transistor region, and there is no pattern. The ion implantation method (ion impUntati〇n) doped 11 ions 60 into & 3 to form a low-concentration η-type well 11 with a doping energy of 3el 5 to lei 6 ^ Record- 蚣 after removing the photoresist 5 〇, this n-type well 11 is for the pressure of high-voltage components π ^ pieces must withstand a voltage of about 16 to 18 volts (V◦ 丨 ts), instantaneous seven Lu 2 * volts', so this type of well 11 must be large And deep, after the doped ^ 70% ion implantation procedure, the wafer (wafer) will be placed in the furnace to heat, such as 1 cents, and the ions can diffuse through high temperature. (Di f fusion), and after the conventional procedure removes the oxide layer 20, the structure shown in the third figure is obtained. See the fourth [§1 ,,,, &, _ _ 乂 traditional method to form a pad gasification layer (pad ο X ide layer) on the substrate 10, 1u 'thickness of about 100 to 20 Angstroms Left and right, this pad is oxidized

Page 11 4 49 91 8-Case No. 8 扪 丨 47RR_year month day____ V. Description of the invention (8) Layer 2 1 is used as a buffer for the substrate and the nitride layer on it to prevent thermal processes Injury caused by stress in After that, a nitride second layer 30 is deposited on the hafnium oxide layer 2 丨, which can be performed by low-pressure chemical vapor deposition (LPCVD) or electric gain chemical vapor deposition (p 丨 asma enhanced). chemical vapor deposition (pECVD), and its thickness is about 1,000 to 3,000 angstroms. Refer to the fifth figure, 'form a patterned photoresist 51 on the nitride layer 30' The photoresist layer is a mask, and the nitrided layer 30 is etched by an etching process. The result obtained is shown in the sixth figure. The photoresist layer 51 is removed, and the wafer is placed in a furnace tube. furnace) ^: a plurality of field oxide regions 22 'are formed on the substrate at a high temperature of about 800 to 1000 ° C, as shown in Figure 7 and then removed by conventional procedures. The siliconized layer 30 is shown in the eighth figure. Referring to the ninth figure, another patterned photoresist layer 53 is formed on the substrate 10, and another high-voltage nsMOS transistor has been formed on the substrate. —N-well pattern. Then, n-type ions 61 were implanted by ion implantation (丨 ⑽ imp lantation) is incorporated into the substrate 10 to form two high-concentration n-type wells 12 in a low-concentration n-type MOS transistor region, and then the photoresist layer 53 is removed. See FIG. Another photoresist layer w is formed on the material, and ρ-type ions 62 are doped into the substrate 10 by ion implantation to form high-voltage ρ-type ribs 8 transistors 449918 __Case No. 88114788 Rev. V. Description of the invention (9) Two high-concentration p-type wells 1 3 'are formed in the body region, and then the photoresist layer 54 is removed. The wafer is placed in a furnace tube and heated to complete a high-temperature diffusion process. After that, the oxide layer 21 is removed, and the result is shown in Fig. 11. The steps described below are to form the gate electrode, the source / inverted region in the M0S transistor, and the BJT transistor. The collector, base, and einitter are shown in Fig. 12. Referring to the twelfth figure, a gate oxide layer 25 is formed on the substrate 10, and then A polysilicon layer (poly-Si 1 IC) layer 4 is deposited on the gate oxide layer 25 as a gate conductor. This gate conductor guide can take advantage of other materials such as metal (m e t a 1) or a metal silicide (si 1 icide), etc. is formed of a patterned photoresist layer 55 on the polysilicon layer 40 thereto. See etch all polysilicon surfaces on the surface), as in the fifteenth sequence, such as ions) in the region _17, and doped with the domain 14, and the gate 41 twelfth figure 'The traditional etching process (etch pr0cess) layer 40 Etching; see Figure 14; deposit an oxide layer 26 on top, and then anisotropic dry etch back (etch back) to form a spacer 27,

Figure 13 on page 13 Next, referring to Figure 16, the traditional standard-path implantation method / doping η-type ions into the double-junction junction transistor (BJT is formed by Φ " the first double-junction junction One of the surface transistors has an emitter / collector in the n-type metal-oxide-semiconductor region to form its source / drain region. This source / non-electrode region is located on the n-type metal-oxide-semiconductor ^ 5: On the span-^ direct contact; then, another

4 499 1 B Amendment_ Case No. 88114788 V. Description of the invention (10) 2 Inverse: Electrical P-type ions are doped into the region of the double junction junction transistor to make the first double junction junction transistor and the first The individual emitter / collector 16 of the three-battery junction transistor 1 and the base 8 of the first two-junction junction transistor, of which the base 18 of the first-two-junction junction transistor is also the second An emitter / collector shared by the surface electric solar body and the second bipolar junction transistor, and incorporated into the P-type metal-oxide semiconductor region to form its source / drain region 5 ', and The gate 4 on the p-type metal-oxide semiconductor transistor is maintained between-the distance is not in direct contact. The function of the distance 70 in this segment is the same as the distance function on the eta-type metal oxide semiconductor transistor, which is called the compensation distance (〇f fset) is designed to adapt to high voltage conditions. So far, the fabrication of the bipolar junction transistor is completed along with the above-mentioned two high-voltage transistor processes. The integration of such processes can make the production of the semiconductor industry more efficient in the future. The above are merely preferred embodiments of the present invention and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application.

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Claims (1)

449918 _Case No. 88114788_ 年月 日 _ί ± ί-_ VI. Scope of Patent Application 1. A method for forming a double-carrier junction transistor with a high-voltage component process, including at least: providing one with a first conductivity A substrate comprising a first part, a second part and a third part; forming a first well with a second conductivity in the first part, and a second well with the second conductivity Wells in the second part, wherein the dopant concentrations of the first well and the second well are equal; forming a plurality of field oxidation regions on the substrate; forming two third wells with the second conductivity in the second well In the third part, a fourth well with the first conductivity is formed in the first well, and a second fifth well with the first conductivity is formed in the second well, wherein the fourth well and the fifth well The dopant concentrations of the wells are equal; a first pole is formed on the third portion between two third wells and a second gate is formed on the second portion between two fifth wells Forming a first gap wall on a side wall of the first gate electrode, and a second gap wall on the side One of the two gate electrodes is on one side wall; a first ion having the second conductivity is doped into each side of the fourth well in the first part to form a set of a first double carrier junction transistor Electrode / emitter, and incorporated into the third part to form a first source / drain region, and a distance is maintained between the first source / drain region and the first gate; and A second ion of the first conductivity is doped into the first part to form a base of the first bipolar junction transistor in the fourth well, and a second bipolar junction transistor is formed. One collector / emitter of the crystal is the first Page 16 4 4991 8 _ Case No. 88Π4788_ Year Month Date __ VI. One of the collectors / emitters of the transistor in the first part of the well side and a third bipolar junction transistor on the side of the patent application In the first part on the other side of the first well, the base of the first bipolar junction transistor and the second bipolar junction transistor and the third bipolar junction transistor The crystal shares a collector / emitter and is doped into the second part to form a second source / drain region, and a section is maintained between the second source / drain region and the second gate. distance. 2. The method according to item 1 of the patent application range, wherein the above substrate includes at least a P-type substrate. Page 17 [^ 449918 _Case No. 88114788_Year Month Date__ VI. Patent Application Scope 3. For the method of applying for the first item of the patent scope, wherein the first well mentioned above includes at least η-type wells. 4. The method according to item 1 of the scope of patent application, wherein the second 丼 mentioned above includes at least an η-type well. 5. The method according to item 1 of the scope of patent application, wherein the above-mentioned field oxidation region is formed by a thermal oxidation method (t h e r m a 1 ο X i d a t i ο η). 6. The method according to item 1 of the patent application scope, wherein the third well described above includes at least an η-type well. 7. The method according to item 1 of the patent application range, wherein the fourth well described above includes at least a P-type well. 8. The method according to item 1 of the patent application range, wherein the fifth well mentioned above includes at least a P-well. 9. The method according to item 1 of the scope of patent application, wherein the above-mentioned first ion includes an n-type ion. 10. The method according to item 1 of the scope of patent application, wherein the above-mentioned second ion includes a P-type ion. Page 18 449918 _Case No. 88114788_Year Month __ VI. Application for Patent Scope 11. The method of applying for the first item of patent scope, where the first part mentioned above is a transistor containing at least three double-carrier junction transistors region. 1 2. The method according to item 1 of the scope of patent application, wherein the second part mentioned above includes at least a region of a high-voltage p-type MOS transistor. 1 3. The method according to item 1 of the scope of patent application, wherein the third part described above includes at least a region of a high voltage η-type metal-oxide-semiconductor (high voltage p type MOS transistor) ° 1 4. The method of item 1, wherein the method for pushing in the first ion includes at least an ion implantation method α 1 5. The method in item 1 of the scope of the patent application, wherein the method of incorporation of the first ion includes at least a diffusion method. 16. The method according to item 1 of the scope of patent application, wherein the above-mentioned second ion doping method includes at least an ion implantation method. 1 7. The method according to item 1 of the scope of patent application, wherein the above-mentioned second ion doping method includes at least a diffusion method. Page 19