Ο 5 Ο 4 T W F. D O C / Ο 0 y Α7 Ο 5 Ο 4 T W F. D O C / Ο 0 y Α7 經濟部中央標準局員工消費合作社印^ Β7 五、發明説明（Ί ) 本發明是有關於一種絕緣閘雙極性電晶體（Insulated GateBipolarTrarmstoriIGBT)的製造方法，且特別是有關於 一種具有矽化鈦（TiSi2)射極的IGBT之製造方法。 絕緣閘雙極性電晶體（IGBT)是目前工業界經常使用到 的功率電晶體’其結合Γ金氧半場效電晶體(M〇SFET)的絕 緣鬧結構及雙極性電晶體（BJT)的導通特性，因此亘有高輸 出電流及高-入阻抗的雙重優點，極適合電力電子上的應 用。然而’其結構中寄生了 PNPN四層的閘流體(thynst〇r) 結構，此寄生的閘流體在電流過大或元件動態切換時，有 可能被觸發導通’造成閘極失控，電流突增的情形出現， 也就是所謂的問鎖現象（latch up)。問鎖現象必須加以避 免’否則不僅本身會被燒毀，線路上的N+型擴散區其他設 備也可能遭到嚴重破壞。 請參照第1圖，圖1所示的係一種習知的N型IGBT的 部份剖面示意圖。在圖1中，IGBT包括有P井120形成的 射極、金氧半電晶體的閘極140形成的閘極、P型底材1〇〇 形成的集極，其中，該金氧半電晶體包括N+擴散區130構 成的源極' N-型磊晶矽層110構成的汲極、P井120構成 的通道區與閘極140。如圖1所示的IGBT結構中，P型底 材100、N_型磊晶矽層110、P井120構成一主要工作的 PNP電晶體，而N+型擴散區丨30、P井120及N-型磊晶矽 層110構成-.·寄生NPN電晶體，此寄生的NPN與正常工作 的PNP電晶體即形成寄生的閘流體。在該IGBT的導通锺; 流中，電子電流是由N +擴散區130經山閘極140 F方之P 呗井1 20流至N_型磊晶矽層1 1 〇，洱由P型底材| 〇〇形成的 --------^ I 装------ir-----*線 (請先聞讀背面之法意事續存填寫本頁) 本紙伖度適用中國國家樓枣（CNS ) Λ4規格（ZIOXM7公缝）Ο 5 Ο 4 TW F. DOC / Ο 0 y Α7 Ο 5 Ο 4 TW F. DOC / Ο 0 y Α7 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs ^ Β7 V. Description of Invention (Ί) The present invention relates to a The manufacturing method of insulated gate bipolar transistor (Insulated GateBipolarTrarmstoriIGBT), and in particular relates to a manufacturing method of IGBT with titanium silicide (TiSi2) emitter. Insulated gate bipolar transistor (IGBT) is a power transistor commonly used in industry at present. It combines the insulation structure of Γ metal oxide half field effect transistor (M〇SFET) and the conduction characteristics of bipolar transistor (BJT) Therefore, it has the dual advantages of high output current and high-in impedance, which is very suitable for power electronics applications. However, 'the structure has a PNPN four-layer thyristor (thynstor) structure. This parasitic thyristor may be triggered to conduct when the current is too large or the device is dynamically switched', causing the gate to run out of control and the current surge Appears, which is the so-called latch up phenomenon. The interlocking phenomenon must be avoided. Otherwise, not only will it be burned, but other equipment in the N + diffusion area on the line may also be severely damaged. Please refer to FIG. 1, which is a schematic partial cross-sectional view of a conventional N-type IGBT. In FIG. 1, an IGBT includes an emitter formed by a P well 120, a gate formed by a gate 140 of a metal oxide semitransistor, and a collector formed by a P-type substrate 100, wherein the metal oxide semitransistor It includes a source composed of an N + diffusion region 130, a drain composed of an N-type epitaxial silicon layer 110, a channel region composed of a P well 120, and a gate 140. In the IGBT structure shown in FIG. 1, the P-type substrate 100, the N_-type epitaxial silicon layer 110, and the P-well 120 constitute a main working PNP transistor, and the N + -type diffusion region 30, P-well 120, and N The -type epitaxial silicon layer 110 constitutes a parasitic NPN transistor. This parasitic NPN and a normally working PNP transistor form a parasitic thyristor. In the conduction of the IGBT; in the flow, the electron current flows from the N + diffusion region 130 through the mountain gate 140 to the N-type epitaxial silicon layer 1 10 through the P chanter well 120 of the F side. Material | 〇〇Formed -------- ^ I installed ------ ir ----- * line (please read the legal matters on the back side and continue to fill out this page) The degree of this paper Applicable to China National Building Date (CNS) Λ4 specification (ZIOXM7 male seam)
3120§)^f^doc/003 A7 經濟部中央標隼局員工消費合作社印製 B7 五、發明説明（2 ) 集極端流出元件；而電洞電流是由p型底材100注入型 磊晶矽層110，再沿著Ν+型擴散區130下方的Ρ井120流 出元件。由於寄生的ΝΡΝ電晶體之基極(Ρ井120)與射極電 極間仍存在有一段並聯電阻，當電洞電流流過該並聯電阻 而產生足夠大的壓降時，寄生的ΝΡΝ電晶體就會導通，而 造成寄生的閘流體導通的閂鎖現象。 有鑑於此，本發明之主要目的就是在提供一種絕緣雙極 性電晶體之射極的製造方法，以改進習知IGBT之缺點，防 止ΝΡΝ電晶體的射基接面被順偏，而避免閂鎖現象。 根據本鸯明之目的，提出一種絕緣雙極性電晶體之射極 的製造方法，包括： a. 提供一底材，作爲絕緣閘雙極電晶體的集極，其上形 成有一電性與底材相反的磊晶矽層，其中，在磊晶矽層中 形成有複數個電性與磊晶矽層相反的井，且在磊晶矽層上 已界定出複數個主動區； b. 在該些主動區表面形成一閘氧化層； c. 形成一複晶矽層於閘氧化層上； d. 形成一墊氧化層於複晶矽層上； e. 形成=氮化矽層於墊氧化層上； f. 定義氮化矽層、墊氧化層、複晶矽層與閘氧化層，形 成絕緣閘雙極電晶體的閘極； g. 在該閘極之複晶矽層兩側形成-側壁氧化層； h. 進行離子佈植，在閘極兩側下方之該些井中形成絕緣 閘雙極電晶體的離子通道區； 1.在閘極兩側裸露之磊晶矽層表面形成一金屬矽化物 4 表紙張尺咬過川中闽阈家樣苹（CNS ) Λ4軋格（210、公緣1 (請先閱讀背面之注意事項再填寫本頁) -裝· 、-° 線 0504TWF. DOC/00> A7 0504TWF. DOC/00> A7 經濟部中央橾隼局員i消費合作社印裝 Β7 五、發明説明（3 ) 層，以構成絕緣閘雙極電晶體的射極。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下。 圖式之簡單說明： 第1 知的一種絕緣閘雙極電晶體的部份剖面示 意圖。' 第—系列剖面圖，用以解釋本發明之一較佳 實施例的製5^1^。 較佳實施例 請先參照第2a圖，提供一 P型矽底材10，並形成一低 度摻雜的N·型磊晶矽層20於P型底材10上，其中N·型磊 晶矽層20之摻雜濃度約介於1 X 1014〜3 X 1014atoms/cm 3 之間。然後，以熱氧化成長方法或是化學氣相沈積法(CVD) 形成一第一氧化層22於磊晶矽層20上，其較佳厚度約是介 於3500〜4500A。接著，以習知的光學微影及蝕刻技術蝕刻 第一氧化層22，在磊晶矽層20表面界定出複數個P井預定 區。使用氟化硼作離子佈植以形成P井30，其中植入的硼 離子劑量約5 X 1015atoms/cm 2，佈植能量約80KeV，並在 溫度約1050 °C下擴散驅入。 其次，請參照第2b圖，以濕式氧化法於第一氧化層22 上再沈積一第二氧化層24，其厚度約介於6000〜8000A。然 後’以習知的光學微影及蝕刻技術界定出主動區，並在主 動區表面上沈積-一較佳厚度約是介於1000〜1100 A之閘氧化 層26。其次，以低壓化學氣相沈積法（LPCVD)於溫度約6.20 本紙張尺度適用中國國家榡率（CNS ) Λ4^格（2丨0X 297公缝） -------J-ν— 裝------訂------：線 (請先閲讀背面之注意事項再填寫本頁) .Doc/ocn A7 B7 經濟部中央標準局員工消費合作社印裝 五、發明説明（4 ) 。(：下沈積一複晶矽層28於第二氧化層24及閘氧化層26 上，其較佳厚度約是介於5000〜6000A。再其次’用劑量約 5 X 1015atoms/cm 2且能量約80KeV的砷摻雜複晶矽層28。 接著，形成一墊氧化層32於複晶矽層28上’其較佳厚度約 是介於200〜400A。再以CVD法沈積一氮化矽層34於墊氧 化層32上，其較佳厚度約是介於5〇0〜1〇〇〇人。 其次，請參照第2c圖，以習知的光學微影及鈾刻技術’ 定義複晶矽層28，以形成絕緣閘雙極性電晶體元件的閘極 36 ° 其次，請參照第2d圖，以熱氧化法將複晶矽再氧化’ 並在複晶矽電極及P并之表面分別形成一側壁間隔層38及 一氧化層39，其厚度約是介於300〜400A’此目的是將閘極 36密封起來，防止閘極與後續完成之射極產生短路。接著， 以氟化硼作離子佈植，在P井30中形成該絕緣閘雙極電晶 體的P-型通道40，其中氟化硼的劑量約是5 X 1013atoms/ cm 2，佈植能量約爲40KeV，且擴散驅入的溫度約是介於 1000~1100 °C。接著，再利用乾蝕刻法將厂型通道40上方 的氧化層39去除。 接著，請看第2e圖，以習知的自行對準矽化物（saliC1de) 製程，先濺鍍一厚度約50~60nm的金屬鈦層，然後在高溫 下於裸露的N-型磊晶矽層20表面’形成一矽化鈦層42， 其厚度約80〜lOOnm，未反應的鈦則以濕蝕刻法除去。此矽 化鈦層42即爲應用本發明之丨GBT的射極。 最後，請參照第2f圖’去除氮化矽層34。然後，以常 壓化學氣相沈積法（APCVD)沈積…第四氣化層44於N:型磊 (請先閲讀背面之注意事項再填寫本頁) 丨裝- 訂 線 本紙張坟度適用中國國家標隼（CNS ) Λ4規格（210X297公楚 0 5 0 4TWF.DOC # Ο Ο 3 A 7 Β7 五、發明説明（5 ) 晶矽層20上，並以習知的光學微影及蝕刻技術形成複數個 接觸區窗口 45。其中，第四氧化層44的厚度較佳約是介於 5500-6000A。最後，於該晶片之正反兩面各沈積一金屬鋁 層48、50，其較佳厚度約1.0〜1.2μπι。接著利用傳統的光 罩製版與蝕_技術，定義金屬鋁層48，使留在複數個接觸 區窗口 45中的金屬鋁層48形成如圖所示的金屬內連線，如 此，便完成本較佳實施例。 依據本發明所完成的絕緣閘雙極電晶體之射極，以矽化 鈦層取代N+擴散區使得P+NT+N+構成的閘流體電路消失， 留下工作電極P+NT+，故不會產生閂鎖效應，改變電晶體 之操作電流。 雖然本發明已以若干較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內‘，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 --------—裝------訂-----(.線 (請先閱讀背面之Vi意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 衣紙浪尺度過用中國阈家橾隼（CNS )人4见格（2丨0 < 公绛）3120§) ^ f ^ doc / 003 A7 B7 printed by the Employee Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economy V. Description of the invention (2) Collector outflow device; and the hole current is injected from p-type substrate 100 epitaxial silicon The layer 110 then flows out of the device along the P well 120 below the N + type diffusion region 130. Since there is still a parallel resistance between the base of the parasitic NPN transistor (P well 120) and the emitter electrode, when the hole current flows through the parallel resistance and a sufficient voltage drop is generated, the parasitic NPN transistor It will conduct, and cause the parasitic thyristor to conduct the latch-up phenomenon. In view of this, the main purpose of the present invention is to provide a method for manufacturing an emitter of an insulated bipolar transistor to improve the shortcomings of the conventional IGBT and prevent the emitter-based junction of the NPN transistor from being deflected forward to avoid latch-up phenomenon. According to the purpose of this project, a method for manufacturing the emitter of an insulated bipolar transistor is proposed, which includes: a. Providing a substrate as the collector of the insulated gate bipolar transistor on which an electrical property opposite to the substrate is formed Of the epitaxial silicon layer, in which a plurality of wells opposite to the epitaxial silicon layer are formed in the epitaxial silicon layer, and a plurality of active regions have been defined on the epitaxial silicon layer; b. In these active Forming a gate oxide layer on the surface of the area; c. Forming a polycrystalline silicon layer on the gate oxide layer; d. Forming a pad oxide layer on the polycrystalline silicon layer; e. Forming = silicon nitride layer on the pad oxide layer; f. Define the silicon nitride layer, pad oxide layer, polycrystalline silicon layer and gate oxide layer to form the gate of the insulated gate bipolar transistor; g. form a side wall oxide layer on both sides of the polycrystalline silicon layer of the gate H. Conduct ion implantation to form an ion channel region of insulated gate bipolar transistors in the wells below the two sides of the gate; 1. Form a metal silicide on the surface of the epitaxial silicon layer exposed on both sides of the gate 4 The paper ruler bites the Chuanzhong Min threshold home sample (CNS) Λ4 rolling grid (210, common edge 1 (please read the back first (Please fill out this page again)-Installation ·,-° Line 0504TWF. DOC / 00 > A7 0504TWF. DOC / 00 > A7 Printed by the Consumer ’s Cooperative of the Central Falcon Bureau of the Ministry of Economic Affairs B7. Invention description (3) layer, To constitute the emitter of the insulated gate bipolar transistor. In order to make the above and other objects, features, and advantages of the present invention more obvious and understandable, a preferred embodiment is described in detail below, in conjunction with the accompanying drawings, for details The description is as follows. Brief description of the drawings: Partial cross-sectional schematic diagram of an insulating gate bipolar transistor known in the first place. The first series of cross-sectional diagrams are used to explain the fabrication of a preferred embodiment of the present invention. For preferred embodiments, please refer to FIG. 2a first, to provide a P-type silicon substrate 10 and form a low-doped N · -type epitaxial silicon layer 20 on the P-type substrate 10, of which N · -type The doping concentration of the crystalline silicon layer 20 is about 1 X 1014 ~ 3 X 1014 atoms / cm 3. Then, a first oxide layer 22 is formed by thermal oxidation growth method or chemical vapor deposition (CVD) method The preferred thickness of the crystalline silicon layer 20 is about 3500 ~ 4500A. Then, using conventional optical lithography and etching techniques The first oxide layer 22 is etched to define a plurality of P-well predetermined areas on the surface of the epitaxial silicon layer 20. Boron fluoride is used for ion implantation to form the P-well 30, wherein the dose of implanted boron ions is about 5 X 1015 atoms / cm 2. The implantation energy is about 80KeV, and it is diffused and driven at a temperature of about 1050 ° C. Secondly, please refer to Figure 2b, a second oxide layer 24 is deposited on the first oxide layer 22 by a wet oxidation method, which The thickness is about 6000 ~ 8000A. Then, the active area is defined by the conventional optical lithography and etching technology, and deposited on the surface of the active area-a gate oxide layer 26 with a preferred thickness of about 1000 ~ 1100A . Secondly, the low-pressure chemical vapor deposition method (LPCVD) is applied at a temperature of about 6.20. The paper scale is suitable for the Chinese national rate (CNS) Λ4 ^ grid (2 丨 0X 297 male seam) ------- J-ν- ------ Subscribe ------: line (please read the precautions on the back before filling in this page). Doc / ocn A7 B7 Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of invention (4 ). (: A polycrystalline silicon layer 28 is deposited on the second oxide layer 24 and the gate oxide layer 26, the preferred thickness is about 5000 ~ 6000A. Secondly, the dosage is about 5 X 1015 atoms / cm 2 and the energy is about 80KeV of arsenic-doped polycrystalline silicon layer 28. Next, a pad oxide layer 32 is formed on the polycrystalline silicon layer 28. The preferred thickness is about 200 ~ 400A. Then a silicon nitride layer 34 is deposited by CVD method On the pad oxide layer 32, the preferred thickness is about 5000 ~ 1000 people. Secondly, please refer to FIG. 2c to define the polycrystalline silicon layer with the conventional optical lithography and uranium engraving technology. 28, to form the gate of the insulated gate bipolar transistor device 36 ° Secondly, please refer to Figure 2d, reoxidize the polycrystalline silicon by thermal oxidation method and form a side wall on the surface of the polycrystalline silicon electrode and P The thickness of the spacer layer 38 and the oxide layer 39 is about 300 ~ 400A. The purpose is to seal the gate 36 to prevent the gate from short-circuiting with the subsequent emitter. Then, use boron fluoride as the ion cloth Planting, forming a P-type channel 40 of the insulated gate bipolar transistor in the P well 30, where the dose of boron fluoride is about 5 X 1013 atoms / c m 2, the implantation energy is about 40KeV, and the temperature of the diffusion drive is about 1000 ~ 1100 ° C. Then, the oxide layer 39 above the factory channel 40 is removed by dry etching. Then, please see Figure 2e, using the conventional self-aligned silicide (saliC1de) process, a metal titanium layer with a thickness of about 50 ~ 60nm is sputtered first, and then formed on the surface of the exposed N-type epitaxial silicon layer 20 at high temperature The thickness of the titanium silicide layer 42 is about 80 ~ 100nm, and the unreacted titanium is removed by wet etching. The titanium silicide layer 42 is the emitter of the GBT of the present invention. Finally, please refer to Figure 2f to remove nitrogen The silicon layer 34. Then, deposited by atmospheric pressure chemical vapor deposition (APCVD) ... The fourth gasification layer 44 is in N: type Lei (please read the precautions on the back before filling this page) The paper thickness is applicable to China National Standard Falcon (CNS) Λ4 specification (210X297 Gongchu 0 5 0 4TWF.DOC # Ο Ο 3 A 7 Β7. V. Description of the invention (5) On the crystalline silicon layer 20, and using the conventional optical micro Shadow and etching techniques to form a plurality of contact area windows 45. Among them, the thickness of the fourth oxide layer 44 is preferably about 5500-600 0A. Finally, deposit a metal aluminum layer 48, 50 on the front and back sides of the wafer, the preferred thickness is about 1.0 ~ 1.2μπι. Then use the traditional mask making and etching technology to define the metal aluminum layer 48, so that The metal aluminum layer 48 left in the plurality of contact area windows 45 forms a metal interconnect as shown in the figure, and thus, the present preferred embodiment is completed. The emitter of the insulated gate bipolar transistor completed according to the present invention To replace the N + diffusion region with a titanium silicide layer makes the thyristor circuit composed of P + NT + N + disappear, leaving the working electrode P + NT +, so there will be no latch-up effect and change the operating current of the transistor. Although the present invention has been disclosed above in a number of preferred embodiments, it is not intended to limit the present invention. Anyone who is familiar with this skill will not deviate from the spirit and scope of the present invention, but can make some changes and retouches, so The scope of protection of the present invention shall be subject to the scope defined in the attached patent application. --------—— 装 ------ 訂 ----- (. 线 (Please read the Vi matters on the back before filling out this page) Printed garments by the Employees Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs The paper wave scale has been used by the Chinese threshold family Falcon (CNS) people 4 see grid (2 丨 0 < Gongjiang)