445556 經濟部中央搮準局貝工消费合作杜印策 C7 D7 五、創作説明（x ) 創作領垅 本創作係關於一種降低電氣雜訊之球陣列封裝裝置， 特別是關於一種利用半導體封裝技術將複數個電容内嵌於 電源平面及接地平面之球陣列封裝裝置β 創作背景 隨著半導體製程技術之進步，在一積體電路内往往内 建有數十萬甚至數百萬顆電晶體。若該數十萬顆電晶體同 時處於工作的狀態，例如同時開啟（turn οη)或同時關閉 (turn off) ’則將對電源供應造成瞬間的脈衝效應和電氣 雜訊，而使得該積體電路的運算結果處於一種不確定的狀 態。 為解決電源供應之穩壓及電氣雜訊的問題，習知的方 法係在連接該積體電路之電路板上加入複數個電容器以消 除該電氣雜訊。如圖I係習知之一塑膠球陣列封裝（ΡΒσΑ) 元件之俯視囷。該球陣列封裝元件固著於_電路板13 之上’而在該球陣列封裝元件1 1四周設置複數個外接式電 容器12。各該複數個外接電容器12電氣連接至該球陣列 封裝元件1 1之電源平面及接地平面，以消除該電源平面及 遠接地平面之間的電氣雜訊。 習知方法將造成電路板13上充斥著各種不同尺寸及種 類的電谷器’不僅造成高成本及大面積之缺點且不符合現 今高科技產品輕薄短小的特性。 創作之簡要說明 本創作之目的係為消除目前使用於球陣列封裝元件之 —4 — ( CNS M4ii*i210X297^jt ) ---- (請先閲讀背面之注意事項再填寫本頁)445556 Central Government Bureau of Standards, Ministry of Economic Affairs, Shellfish Consumer Cooperation, Du Yince, C7, D7 V. Creative Instructions (x) Creative Leadership This creative work is about a ball array packaging device that reduces electrical noise, especially a semiconductor packaging technology. Ball array packaging devices with a plurality of capacitors embedded in the power plane and the ground plane β Creative background With the advancement of semiconductor process technology, hundreds of thousands or even millions of transistors are often built in an integrated circuit. If the hundreds of thousands of transistors are in a working state at the same time, for example, turn on (turn οη) or turn off (turn off) 'at the same time, it will cause an instantaneous pulse effect and electrical noise on the power supply, making the integrated circuit The result of the operation is in an uncertain state. In order to solve the problems of power supply voltage stabilization and electrical noise, a conventional method is to add a plurality of capacitors to a circuit board connected to the integrated circuit to eliminate the electrical noise. Figure I is a top view of a conventional plastic ball array package (PBσA) device. The ball array package element is fixed on the circuit board 13 ', and a plurality of external capacitors 12 are provided around the ball array package element 1 1. Each of the plurality of external capacitors 12 is electrically connected to a power plane and a ground plane of the ball array package element 11 to eliminate electrical noise between the power plane and the far ground plane. The conventional method will cause the circuit board 13 to be flooded with electric valley devices of various sizes and types, which not only causes the disadvantages of high cost and large area, but also does not meet the characteristics of thinness and shortness of today's high-tech products. Brief description of the creation The purpose of this creation is to eliminate the currently used components of the ball array package —4 — (CNS M4ii * i210X297 ^ jt) ---- (Please read the precautions on the back before filling this page)
*1T -線 經濟部中夬樣準局月工消費合作社中裂 Λ 45 55 6 C7 _______D7____ 五、創作説明（2 ) 電氣雜訊過濾方式之成本較高及使用面積較大之缺點。為 了達到上述目的，本創作提供一種降低電氣雜訊之球陣列 封裝裝置，該裝置利用半導體封裝技術將複數個内接式電 容固著於本創作裝置之基座之上，並將該複數個内接式電 容直接或經由一導通孔電氣連接至本創作裝置之電源平面 及接地平面’以有效達成穩壓及過濾電氣雜訊之功能。 本創作之降低電氣雜訊之球陣列封裝裝置，包含一基 座（substrate)、複數個銲接球（s〇lder ball)及複數個内 接式電容。該基座包含一接觸層、一電源平面及—接地平 面。該複數個銲接球，固著於該接觸層之上。該複數個内 接式電容’設置於該接觸層之上，其利用一導電膠電氣連 接至邊電源平面及該接地平面’以降低該電源平面及該接 地平面之間的電氣雜訊。 圖式之簡罕說明 本創作將依照後附圖式來說明，其中： 囷1係習知之球陣列封裝元件之俯視圖； 圖2係本創作之降低電氣雜訊之球陣列封裝裝置之第一較 佳實施例的俯視剖面囷； 圖3係本創作之降低電氣雜訊之球陣列封裝裝置之第二較 佳實施例之橫切面圖； 圖4係本創作之降低電氣雜訊之球陣列封裝裝置之第三較 佳實施例之橫切面囷；及 圖5係本創作之降低電氣雜訊之球陣列封裝裝置之第四較 佳實施例之橫切面囷。 _________- 5 - 本紙張ΛΑΑ財e B家料{ CNS > A峨《· ( 210X 297公釐')---- ί _先閲讀背面之注意事項再填寫本頁) 訂 線 4 4 5 5 5 6 C7 —_ D7 五、創作説明（3 ) 孟件符號說明 11 球陣列封裝元件 12 外接式電容 13 電路板 2 1 球陣列封裝裝置 22 接地球 23 内接式電容 24 接地平面 25 電源平面 2 6 訊號球 27 電源球 3 0 基座 3 1 訊號平面 3 2 絕緣平面 3 3 黏著膠 3 4 防銲漆 3 5 導通孔 3 6 接觸層 3 7 導電膠 (請先閲讀背面之注意事項再填寫本頁) 41接地平面連接至接觸層的相對位置 42電源平面連接至接觸層的相對位置 較佳實施例說明 圖2係本創作之降低電氣雜訊之球陣列封裝裝置之第 一較佳實施例的俯視剖面圖。該球陣列封裝裝置2 1包含— 基座30。在該基座30之中央位置為一接地平面24，且在 該接地平面24之上方固著複數個接地球22。該接地平面 之外部為一電源平面25，且在該電源平面25之上方固著 複數個電源球27。複數個内接式電容23固著於該基座30 之上’且電氣連接於該接地平面24及該電源平面25。該 内接式電容23之功能相當於圖1之外接式電容12，用以達 到穩壓及滅除該電源平面2 5及該接地平面2 4之間的電氣 雜訊。該電源平面2 5·外部設置複數個訊號球26。本文中 本紙张尺度遑用中·家橾♦ ( CNS > A4*l格（210X297公釐） 訂 線 經濟部中央標準局員工消合作社印¾ 445556 鯉濟部中央標準局負工消费合作社印11 C7 D7 五、創作説明（4 ) 之接地球2 2、電源球2 7及訊號球2 6統稱為銲接球。該複 數個接地球2 2 '該複數個電源球2 7及該複數個訊號球2 6 均可傳送連接本創作裝置之電路板13的電氣訊號，並可利 用傳導原理將本創作裝置2 1所產生的熱能經由該電路板 13釋放出去。遠接地平面24之電壓準位通常以符號vss表 示，在數位積體電路中常見的電壓準位為〇伏特。該電源 平面25之電壓準位通常以符號Vdd表示，在現今之數位積 體電路中常見的電壓準位為3.3伏特。因該内接式電容23 係以半導體封裝技術内嵌（e m b e d d e d)於本創作之球陣列 封裝裝置21之内’故就整體應用而言，可有效地降低該球 陣列封裝裝置21之製造成本及使用面積。該内接式電容 23並不限於任何材質，只要符合積體電路封裝技術者均可 適用。一種可行之内接式電容封裝技術係在本創作之球陣 列封裝裝置2 1進行植球後’以一執行表面黏著技術之機台 將該内接式電容23固著於該電源平面25及該接地平面24 之間。 圖3係本創作之降低電氣雜訊之球陣列封裝裝置之第 二較佳實施例之横切面圖’本實施例之球陣列封裝裝置2 i 係為雙層結構。第一層為一包含該電源平面2 5及該接地平 面24之接觸層36，而在該電源平面25及該接地平面24之 間以一防銲漆（solder mask)34予以隔離。第二層為—用 於傳輸電氣訊號之訊號平面31，該訊號平面31之材質並 不受任何限制，例如為常見的銅金屬。在第一層和第二層 間以一絕緣平面3 2予以隔離，該絕緣平面3 2並不受任何 -7 - 本紙張ΧΛϋ用 +«邮科（CNS > ( 21GX297公釐) ' 一~~'~~ <請先Μ讀背面之注意事項再填寫本頁)* 1T -line The Ministry of Economic Affairs of the Central China Procurement Bureau, the monthly labor consumer cooperative Λ 45 55 6 C7 _______D7____ V. Creation instructions (2) The disadvantages of the high cost of the electrical noise filtering method and the large use area. In order to achieve the above purpose, the present invention provides a ball array package device for reducing electrical noise. The device uses semiconductor packaging technology to fix a plurality of internal capacitors on the base of the creative device, and the plurality of The connection capacitor is directly or electrically connected to the power plane and the ground plane of the creative device through a via hole to effectively achieve the functions of voltage stabilization and filtering of electrical noise. The ball array packaging device for reducing electrical noise in this creation includes a substrate, a plurality of solder balls, and a plurality of internal capacitors. The base includes a contact layer, a power plane, and a ground plane. The plurality of solder balls are fixed on the contact layer. The plurality of internal capacitors are disposed on the contact layer, and are electrically connected to the side power plane and the ground plane by using a conductive adhesive to reduce electrical noise between the power plane and the ground plane. A brief description of the drawings This creation will be explained in accordance with the following drawings, where: 囷 1 is a top view of a conventional ball array package component; FIG. 2 is the first comparison of the ball array package device of this invention to reduce electrical noise Top view of the preferred embodiment; Figure 3 is a cross-sectional view of the second preferred embodiment of the ball array packaging device for reducing electrical noise of the present invention; Figure 4 is of the ball array packaging device for reducing electrical noise of the present invention A cross-section 第三 of a third preferred embodiment; and FIG. 5 is a cross-section 囷 of a fourth preferred embodiment of the ball array packaging device for reducing electrical noise of the present invention. _________- 5-This paper ΛΑΑ 财 e B home materials {CNS > A EM "· (210X 297 mm ') ---- ί _ Read the precautions on the back before filling this page) Thread 4 4 5 5 5 6 C7 —_ D7 V. Creation Instructions (3) Meng Symbols 11 Ball Array Package Components 12 External Capacitors 13 Circuit Board 2 1 Ball Array Package Device 22 Ground Ball 23 Internal Capacitor 24 Ground Plane 25 Power Plane 2 6 Signal ball 27 Power ball 3 0 Base 3 1 Signal plane 3 2 Insulating plane 3 3 Adhesive 3 4 Solder paint 3 5 Vias 3 6 Contact layer 3 7 Conductive glue (please read the precautions on the back before filling in this (Page 41) The relative position of the ground plane connected to the contact layer 42 The relative position of the power plane connected to the contact layer Description of the preferred embodiment FIG. 2 is a first preferred embodiment of the ball array package device of the present invention for reducing electrical noise Top sectional view. The ball array package 2 includes-a base 30. A ground plane 24 is located at the center of the base 30, and a plurality of ground balls 22 are fixed above the ground plane 24. Outside the ground plane is a power plane 25, and a plurality of power balls 27 are fixed above the power plane 25. A plurality of internal capacitors 23 are fixed on the base 30 'and are electrically connected to the ground plane 24 and the power plane 25. The function of the internal capacitor 23 is equivalent to that of the external capacitor 12 of FIG. 1 for achieving voltage stabilization and eliminating electrical noise between the power plane 25 and the ground plane 24. A plurality of signal balls 26 are externally provided on the power plane 2 5 ·. In this paper, the paper size is in use and home. ♦ (CNS > A4 * l (210X297 mm) Thread Seal of the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 445556 C7 D7 5. The creation ball (2) ground ball 2 2. Power ball 2 7 and signal ball 26 are collectively referred to as solder balls. The plurality of ground balls 2 2 'the plurality of power balls 27 and the plurality of signal balls 2 6 can transmit electrical signals connected to the circuit board 13 of the creative device, and can use the principle of conduction to release the thermal energy generated by the creative device 21 through the circuit board 13. The voltage level of the far ground plane 24 is usually The symbol vss indicates that the common voltage level in digital integrated circuits is 0 volts. The voltage level of the power plane 25 is usually represented by the symbol Vdd, and the common voltage level in today's digital integrated circuits is 3.3 volts. Because the internal capacitor 23 is embedded in the ball array packaging device 21 created by the semiconductor packaging technology, so as to the overall application, the manufacturing cost of the ball array packaging device 21 can be effectively reduced. And use area. The internal capacitor 23 is not limited to any material, as long as it conforms to the integrated circuit packaging technology. A feasible internal capacitor packaging technology is planted in the ball array packaging device 21 of this creation. Behind the ball, the internal capacitor 23 is fixed between the power plane 25 and the ground plane 24 by a machine that implements surface adhesion technology. Figure 3 shows the ball array packaging device for reducing electrical noise in this creation. Cross-sectional view of the second preferred embodiment 'The ball array packaging device 2 i of this embodiment is a two-layer structure. The first layer is a contact layer 36 including the power plane 25 and the ground plane 24, and The power plane 25 and the ground plane 24 are separated by a solder mask 34. The second layer is a signal plane 31 for transmitting electrical signals, and the material of the signal plane 31 is not subject to any restrictions. For example, it is a common copper metal. The first and second layers are separated by an insulating plane 32, which is not subject to any -7-This paper XΛϋ uses + «Post section (CNS > ( 21GX297 mm) 'a ~~' ~~ < First Μ Notes Complete this page and then read it back)
C7 D7 4, 4δ 5 5 6 五、創作説明（5 ) 限制，常見之高分子樹脂（BT Resins)均可適用。該訊號 平面31以一内嵌有導電材質之導通孔（via)35和該電源平 面25或該接地平面24相通，以達到電氣訊號移轉的功 能。該内接式電容23可經由一黏著膠33固著於該接觸層 36之上。該黏著膠33並不限於任何材質，常見之紅膠均 可適用。該内接式電容23並經由一導電膠37電氣連接於 該電源平面2 5及該接地平面2 4之間。該導電膠3 7並不限 於任何材質，常見之錫鉛合金材質均可適用。該内接式電 容2 3的兩侧分別為該接地球2 2、該電源球2 7及該訊號球 2 6。值得注意的是，該内接式電容2 3的高度應小於該接 地球22、該電源球27及該訊號球26的高度，以避免導致 該球陣列封裝裝置21和該電路板13因接觸面積不足而造 成接觸不良的瑕截。 圖4係本創作之降低電氣雜訊之球陣列封裝裝置之第 二較佳實施例之橫切面圖’本實施例之球陣列封裝裝置係 為四層結構’但亦可適用於其他層數的結構。因為圖3之 雙層結構有一值得改進之處，即該接地平面24及電源平面 25將被限制於一特定之區域，因此該内接式電容亦同樣被 限制於該特定區域。因此，雖然雙層結構有成本較低的優 點，但在使用上缺乏彈性。在現今球陣列封裝已有趨向多 層板的設計趨勢下，可以選擇將該内接式電容23固著於該 球陣列封裝裝置21中安置較少元件的區域，以提高該球陣 列封裝裝置21之使用效率。此外，該安置的區域可使用於 孩基座30之正面或反面，本發明並不作任何之限制。如圖 7紙張从祿率(㈤)勵(2l0x29‘,-------- (請先閲讀背面之注意事項再填寫本頁) 訂 線 經濟部中央樓準局工消費合作杜印策 445556 C7 D7 經濟部肀央揉率扃只工消费合作社印装 五、創作説明（6) 4所示，接觸廣3 6、電源平面2 5及接地平面2 4係位於該球 陣列封装裝置2 1之不同層。該電源平面2 5及該接地平面 24可分別經由一内嵌有導電材質之導通孔35電氣連接至 該接觸層30。該内接式電容23並經由一黏著膠33固著於 該接觸層36之上，並利用一導電膠37電氣連接至該接地 平面2 4及該電源平面2 5經由該導通孔3 5出現在該接觸層 3 6之相對位置4 1和4 2 ’以降低該電源平面2 5及該接地平 面24之間的電氣雜訊" 圖5係本創作之降低電氣雜訊之球陣列封裝裝置之第 四較佳實施例之橫切面圖，本實施例之球陣列封裝裳置係 為四層結構’但亦可適用於雙層或其他層數的結構。圖5 之導電膠37的位置係位於該内接式電容23之下方，而圖4 之導電膠37的位置係位於該内接式電容23之兩側。圖4和 圖5之導電膠37的功能均是將該内接式電容23透過該導電 膠37而電氣連接至該電源平面25及接地平面24，但差別 在於兩者在製程上的步驟和順序有一些差異。圖4之結構 在製程上為先黏合該内接式電容23於該接觸層36之上， 再以該導電膠37電氣速接該内接式電容23、該電源平面 25及接地平面24。圖5之結構在製程上為先黏合該導電膠 37於該電源平面25及接地平面24之上，再以該内接式電 容23固著於該導電勝37之上’而使該内接式電容23、該 電源平面25及該接地平面24達成電氣連接。 本創作之技術内容及技術特點巳揭示如上，然而熟悉 本項技術之人士仍可能基於本創作之教示及揭示而作種種 ______- 9 - 本纸張^/1逍用中8|調家揉丰（〇那）八4«(^(210¥297公瘦) ' {请先閱讀背面之注意事項再填寫本頁)C7 D7 4, 4δ 5 5 6 5. Restrictions on creation (5). Common polymer resins (BT Resins) can be used. The signal plane 31 communicates with the power plane 25 or the ground plane 24 via a via 35 embedded with a conductive material to achieve the function of transferring electrical signals. The internal capacitor 23 can be fixed on the contact layer 36 through an adhesive 33. The adhesive 33 is not limited to any material, and common red adhesives can be used. The internal capacitor 23 is electrically connected between the power plane 25 and the ground plane 24 through a conductive adhesive 37. The conductive adhesive 37 is not limited to any material, and common tin-lead alloy materials can be used. The two sides of the internal capacitor 23 are the ground ball 2 2, the power ball 27, and the signal ball 26. It is worth noting that the height of the internal capacitor 23 should be less than the height of the ground ball 22, the power ball 27, and the signal ball 26, so as to avoid the contact area of the ball array packaging device 21 and the circuit board 13 due to the contact area. Insufficient contact and flaws. Fig. 4 is a cross-sectional view of the second preferred embodiment of the ball array packaging device for reducing electrical noise of the present invention. "The ball array packaging device of this embodiment has a four-layer structure." But it can also be applied to other layers. structure. Because the double-layer structure of FIG. 3 has a worthy improvement, the ground plane 24 and the power plane 25 will be limited to a specific area, so the internal capacitor is also limited to the specific area. Therefore, although the double-layer structure has the advantage of lower cost, it lacks flexibility in use. Under the current design trend of multi-layer boards for ball array packaging, the internal capacitor 23 can be fixed to the ball array packaging device 21 with fewer components in place, so as to improve the ball array packaging device 21 Use efficiency. In addition, the placement area can be used for the front or back of the child base 30, and the present invention is not limited in any way. As shown in Figure 7, the paper from the rate (㈤) encourages (2l0x29 ', -------- (Please read the precautions on the back before filling out this page). 445556 C7 D7 Ministry of Economic Affairs, Central Government, Printing, Printing by Consumer Cooperatives V. Creative Instructions (6) 4, Contact Wide 3 6, Power Plane 2 5 and Ground Plane 2 4 are located in the ball array packaging device 2 1 The power plane 25 and the ground plane 24 can be electrically connected to the contact layer 30 through a conductive hole 35 embedded with a conductive material, respectively. The internal capacitor 23 is fixed to the contact layer 30 by an adhesive 33 Above the contact layer 36 and electrically connected to the ground plane 24 and the power plane 25 with a conductive adhesive 37 appear at the relative positions 4 1 and 4 2 ′ of the contact layer 36 through the via 35. Reducing electrical noise between the power plane 25 and the ground plane 24. FIG. 5 is a cross-sectional view of the fourth preferred embodiment of the ball array packaging device for reducing electrical noise of the present invention. The ball array package is a four-layer structure, but it can also be applied to double-layer or other-layer structures. The position of the conductive adhesive 37 in FIG. 5 is below the internal capacitor 23, and the position of the conductive adhesive 37 in FIG. 4 is on both sides of the internal capacitor 23. The positions of the conductive adhesive 37 in FIG. 4 and FIG. The function is to electrically connect the internal capacitor 23 to the power plane 25 and the ground plane 24 through the conductive adhesive 37, but the difference is that there are some differences in the steps and sequence of the two processes. The structure of Figure 4 is in the process First, the internal capacitor 23 is bonded on the contact layer 36, and then the conductive capacitor 37 is used to electrically connect the internal capacitor 23, the power plane 25, and the ground plane 24. The structure of FIG. 5 is on the manufacturing process. In order to adhere the conductive adhesive 37 on the power plane 25 and the ground plane 24, and then fix the internal capacitor 23 on the conductive surface 37, the internal capacitor 23 and the power plane 25 are fixed. And the ground plane 24 to achieve an electrical connection. The technical content and technical characteristics of this creation are disclosed above, but those familiar with this technology may still make various ______- 9-this paper based on the teaching and disclosure of this creation ^ / 1 Xiaoyongzhong 8 | Tune home rubbing (〇 that) eight 4 «(^ (210 ¥ 297 public Thin) '(Please read the notes on the back before filling this page)
T 線 44555 6 C7 D7 五、創作説明（7 ) 不背離本創作精神之替換及修飾；因此，本創作之保護範 圍應不限於實施例所揭示者，而應包括各種不背離本創作 之替換及修飾，並為以下之申請專利範圍所涵蓋。· ----------,Μ- (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中夬標準局負工消費合作社印裂 -10 - 本紙张尺度逍用中國《家標準（〇'«)人4«<格（210父297公釐）T line 44555 6 C7 D7 V. Creation instructions (7) Does not depart from the spirit of the creation and modification; therefore, the scope of protection of this creation should not be limited to those disclosed in the embodiment, but should include all kinds of replacement and Modified and covered by the following patent application scope. · ----------, Μ- (Please read the notes on the back before filling out this page) Order the China National Standards Bureau of the Ministry of Economic Affairs and the Consumer Cooperatives Print -10-This paper standard is used in China " Family standard (〇 '«) person 4« < case (210 father 297 mm)