TW445500B - Method and device for testing wafer in a bare die state - Google Patents

Method and device for testing wafer in a bare die state Download PDF

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Publication number
TW445500B
TW445500B TW89107351A TW89107351A TW445500B TW 445500 B TW445500 B TW 445500B TW 89107351 A TW89107351 A TW 89107351A TW 89107351 A TW89107351 A TW 89107351A TW 445500 B TW445500 B TW 445500B
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Taiwan
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wafer
test
positioning
bare
substrate
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TW89107351A
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Chinese (zh)
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Cheng-Shiang You
Ren-Nan Luo
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Advanced Semiconductor Eng
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Abstract

The present invention relates to a method and device for testing bare die. The wafer module to be tested is positioned on a positioning platform. A plurality of probes on a testing platform are used to correspondingly press and touch the ball pads pre-arranged on the bottom of the wafer module. A testing current is inputted from the testing platform via the probes and ball pads for thereby forming a circuit loop in the die. The testing platform also detects and compares the voltage signals of the bare die circuit outputted from the ball pads. Accordingly, based on the bare die state of the wafer before being molded, it is able to detect and determine the correct position of the bad contact point of the circuit, and further save the manufacturing cost.

Description

445500445500

五、發明說明(1) 本發明係有關於一種晶圓於裸晶狀態之測試方法及其 裝置之設計,特別是指一種可於晶圓在封模前的裸晶狀態 ’測知判斷棵晶内部迴路之不良接點的正確位置,進而能 達到節省製造成本等功效之晶圓於裸晶狀態之測試方法及 其裴置者。 按,隨著1C製造技術的不斷進步,從數個微米製程技 術到現在的次微米’甚至一至二年後的深次微米技術,IC 功能的不斷增加’相對帶動下游封裝業之封裝技術的精益 求精,由於目前電子產品的設計趨勢大致係朝高速化、多 功能化、小塑化及輕量化發展,而丨c設計亦大致朝高集積 化、快速化、多功能化、低耗能化及高頻化之趨勢發展, 因此封裝的發展趨勢遂亦逐漸走向多腳數化、導線細微化 、小型化、及高散熱化。 目前IC晶圓封裝型態大致可區分為兩大類,一為引線 插入型’另一則為表面粘著型’其中以表面粘著型為例, /、主要封裝型悲有球柵陣列(B a U g丨i d A r r a y,簡稱B G A) 方式所明球柵陣列(B G A)封裝技術係目前最新的高接腳 數積體電路封裝技術’適用於今日以次微米解析度所製造 之超大規模集積(Ultra-Large Scale Integration)。晶 0見行之封裝步驟為上基板— —封模—上錫球— 分割,樣士 + α r —、、° 5之’其封裝方式主要係將分割開之單一晶圓固 疋於陣列封裝型印刷電路之基板上,進行打線作業後 ^膠以包封突出於基板表面上之晶圓’前述球格陣列 封'"型印刷電路之基板上預焊有呈球格陣列狀排列之焊點V. Description of the invention (1) The present invention relates to a test method and device design for a wafer in a bare die state, and particularly refers to a method for detecting and determining a bare crystal state before the wafer is sealed. The correct position of the bad contact of the internal circuit can further achieve the test method for saving wafer cost and other functions in the bare die state and its installer. According to the continuous progress of 1C manufacturing technology, from several micron process technology to the current sub-micron technology, and even the deep sub-micron technology one to two years later, the continuous increase of IC functions' has driven the excellence of packaging technology in the downstream packaging industry. Due to the current design trends of electronic products, they are generally moving towards high speed, multifunctionalization, small plasticization and light weight, and 丨 c design is also generally toward high integration, rapidization, multifunctionality, low energy consumption and high energy consumption. The trend of frequency development has developed, so the development trend of packaging has gradually moved towards multi-pin counting, miniaturization of wires, miniaturization, and high heat dissipation. At present, IC wafer packaging types can be roughly divided into two categories, one is a lead-insertion type and the other is a surface-adhesive type. Among them, the surface-adhesive type is used as an example. /, The main package type is a ball grid array (B a Ug 丨 id Aray (BGA) ball-grid array (BGA) packaging technology is currently the latest high-pin integrated circuit packaging technology 'applicable to ultra-large-scale accumulation manufactured today with sub-micron resolution ( Ultra-Large Scale Integration). The packaging steps of the crystal 0 line are the upper substrate—molding—the upper solder ball—segmentation, sample + α r —, ° 5 ', and its packaging method is mainly to fix the separated single wafer to the array package. After the wire bonding operation is performed on the substrate of the printed circuit board, glue is used to encapsulate the wafer protruding above the surface of the substrate. The aforementioned “ball grid array sealing” " point

第4頁 五、發明說明(2+) ,且為使各 作為锡球塾 則後續所植 行沖切作業 短路現象, 前述晶 知晶圓封裝 當檢測出不 ,如此不僅 民本等更形 其作業方式 ?瓜咼是否不 <由於係為 檢測速度較 為疏失而產 本案之 進行檢測作 而造成製造 關工作之經 順利植上 鍍層,若 球會脫落 個封裝作 對各晶圓 步驟,晶 檢測作業 ,無法針 料上的浪 ;或有於 線步驟後 成線塌所 測,而非 率差,且 情形。 有鑑於習 旦發現接 南等之缺 以潛心研 作業係於封模後才逐— 則整個成品需報廢,因 是乃憑本身多年從事相 ,終得有本發明之問世 焊點可 之金屬 上的錫 ’於整 必需再 圓封裝 之電性 良品時 造成原 同虛工 係於打 足而造 人工檢 慢、效 生誤判 發明人 業… 成本提 驗,加 錫球, 該焊點 而形成 業完成 施以電 圓於封 係於晶 對不良 費,且 封模前 利用人 弓丨起之 藉助儀 無可避 封裝 點不良 失,於 究構思 各焊點 未順利 不良品 後,為 性檢測 模前稱 圓封模 品進行 之前的 的裸晶 的肉眼 短路現 器之電 免會有 上須先 鍍上金 ,最後 確定晶 作業。 為裸晶 後才進 任何的 作業工 狀態作 逐一檢 象,此 性檢測 因眼睛 鍛上一層 屬鍍層, 再依序進 圓是否有 ,由於習 行,以致 補救作業 時及人工 檢測者, 測打線之 種作業方 ,故不僅 疲勞或人 離之:心Γ"月之王…乃在於提供一種晶圓於裸” ;之別成方法,其係確實能測知判斷晶圓於裸s j阳次 Z、内部迴路之不良接點的正確位置等功效者。 % 而本發明之另一目的則係在於提供—種晶圓 '呀as狀5. Explanation of the invention (2+), and in order to make the die-cutting operation of the subsequent die-cutting operation short-circuited as a solder ball, the above-mentioned crystal-knowledge wafer package should not be detected, so that it is not only the people but the others. Operation method? Is it not < Since the detection of this case is due to the negligence of the detection speed, the manufacturing process has been successfully plated, and if the ball will fall off, the package will be used for each wafer step. , Can not pin the wave on the material; or have been measured after the line step into a line collapse, not the rate difference, and the situation. In view of the fact that Xi Dan found that the lack of access to the South and so on was concentrated after the mold is closed. The entire finished product must be scrapped because it has been engaged in phases for many years. When the electrical quality of the tin is required to be rounded and packaged, the original virtual work is caused by the slow motion and the artificial detection is slowed down. The inventor's business is misjudged ... Cost inspection, adding solder balls, and forming the solder joint Completed the application of electrical rounds to the sealing system and the wafer to the bad fee, and the use of a human bow before sealing the mold can not avoid the failure of the packaging point. After conceiving that each solder joint is not successfully defective, it is a sexual detection mold. The former said that the naked-eye short-circuit current generator of the bare die before the sealing of the mold had to be plated with gold before finalizing the crystal operation. Make a one-by-one inspection of the status of any worker before entering the bare crystal. This test is performed by forging a layer of metal plating on the eyes and then sequentially entering the circle. Due to the practice, during the remedial operation and manual inspection, the test line is measured. This kind of operator is not only tired or away from people: the heart of the moon "is to provide a kind of bare wafer"; the other method is that it can really determine whether the wafer is bare. , The correct position of the bad contact of the internal circuit, etc.% Another object of the present invention is to provide a kind of wafers

445500 五、發明說明(3) 態之測試裝置,其係確實能具有節省製造成本等功效者。‘ 依據上述之目的,本發明之特徵係在於藉由將待測琴 之晶圓模組定位於一定位基台上’利用一測試台上之多數 探針對位頂觸預設於該晶圓模組底面之球墊,由測試台將 —測試電流經由探針及球墊輸入,而使晶圓模組之晶圓内 部構成一迴路,同時該測試台並偵測比較自球塾輸出之晶 圓内部迴路的電壓訊號’藉此於晶圓封模前之裸晶狀態, 即可測知判斷其内部迴路之不良接點的正確位置,進而能 達到節省製造成本等功效者。 b 依序包 ;其中 位基台 基板已 —端接 驟中, 應之球 波經由 迴路; 路的電 於裸晶 作之裝 3又 台上用 是,本發 含有定位 ,該定位 上,該晶 預設有多 合處係分 係利用一 墊;接著 探針及球 而後於偵 壓訊號, 狀態時, 置則係包 於定位基 以壓制晶 法,其主要係 測比較等步驟 组定位於一定 ,其側 於該等 ;而於 觸於前 明晶圓 、對位 步驟, 圓模組 數導線 別設有 測試台 於訊號 墊輸入 測比較 並與預 其内部 含有一 台下方 圓組達 於裸晶 、訊號 係將待 之晶圓 ,另於 預供錫 上之多 輸出步 ,而使 步驟, 設值進 迴路之 機架、 之機架 定位之 輸出, 測試之 於裸晶 基板底 球定位 數探針 驟,係 裸晶狀 係接收 行比較 短路或 $又置 上之測 定位裝 以及偵 晶圓模 狀態時 面對應 之球墊 對位了頁 由測試 態之晶 自球墊 ’藉β 開路狀 於機架 試台、 置,以 台將一 圓内部 輸出之 測知判 況;至 上之定 一設於 及一設 邊與一 導線的 對位步 述相 測試f 構成-晶圓运 斷晶n 於本倉 位基合 定位i 於測驾445500 V. Description of the invention (3) The test device can really save the manufacturing cost and other effects. '' According to the above purpose, the present invention is characterized by positioning the wafer module of the piano to be tested on a positioning abutment. The ball pad on the bottom of the group is input by the test bench through the probe and the ball pad to form a loop inside the wafer module wafer. At the same time, the test bench detects and compares the wafer output from the ball pad. The voltage signal of the internal circuit can be used to determine the correct position of the bad contact in the internal circuit before the die is die-sealed before the wafer is sealed, thereby achieving effects such as saving manufacturing costs. b Sequential package; the base plate of the base station has been terminated-the ball wave should pass through the circuit; the circuit of the circuit is mounted on the bare chip. 3 is used on the platform, the hair contains positioning, the positioning, the The crystal is preset to use multiple pads, and then a pad is used; then the probe and the ball are then used to detect the pressure signal. When the state is set, the crystal is wrapped in a positioning base to suppress the crystal method. Certainly, it is on the side; and in the step of contacting the front-facing wafer and the alignment step, the round module wire is provided with a test bench for signal input and comparison with the signal pad, and it contains a lower round group in the inside. The die and signal are the wafers to be waited for, and there are multiple output steps on the pre-supply tin, and the step is to set the value into the circuit rack, the rack positioning output, and test the bottom ball positioning of the bare substrate. The number of probes is the same as that in the bare crystal system. The receiving line is relatively short-circuited or the measurement position is placed again and the corresponding ball pad is aligned when the wafer mold status is detected. The test state is obtained from the ball pad. Open circuit in the rack test bench, The test results of a circle's internal output are determined by the platform; the above-mentioned set-up and set-up phase and phase comparison test with a wire f constitutes-wafer transport chip n is located in this position and i is positioned at Test drive

五、發明說明(4) 台下方且可連動測試台昇降移動之昇降裝置等構件;且該 測試台頂面係配合裸晶狀態之晶圓的線路設計而佈置有多 數個探針,且該測試台並連設有一可提供測試電流與接收 偵測電壓之測試機,藉此於晶圓於封模前之裸晶狀態即可 測知判斷其内部迴路之不良接點的正確位置,進而能達到 節省製造成本等功效者。 為期能對本發明之目的、功效以及特徵有更詳盡明確 的瞭解,茲舉本發明之較佳實施例並配合圖式說明如后: 首先,請參閱第一圖,係本發明一較佳實施例之流程 -塊圖,如圖所示,由前述習知所述可知,一般封裝作業 之流程大致係可依序區分為晶圓上基板、打線、封模、上 錫球及沖切等作業步驟,而本發明晶圓於裸晶狀態之測試 方法1即係於前述習知打線作業後,封模作業前實施;該 裸晶測試方法1 主要係依序包含有定位1 1、對位1 2、訊號 輸出1 3,以及偵測比較1 4等步驟;以下就各步驟之製程詳 細說明如后。 請同時參閱第二、三圖,係分別為本發明一較佳實施 例之定位、對位步驟實施狀態示意圖,以及本發明一較佳 實施例之裸晶測試裝置示意圖,如圖所示,於定位步驟1 1 i可利用機械手臂或輸送帶傳輸方式將晶圓模組2輸送至 定位基台3 1上,其中,該晶圓模組2係具有一基板2 1 ,該 基板Η上定位有一呈裸晶狀態之晶圓(d 1 e ) 2 2,且晶圓2 2 側邊與基板2 1連接有多數導線23,另於基板2 1底面對應於 該等導線2 3的一端接合處係分別設有預供錫球定位之球墊V. Description of the invention (4) The lifting device and other components under the platform that can be moved up and down in conjunction with the test platform; and the top surface of the test platform is arranged with a plurality of probes in accordance with the circuit design of the wafer in the bare crystal state, and the test A testing machine capable of providing a test current and receiving a detection voltage is connected in parallel, so that the correct position of the bad contact of the internal circuit can be detected and judged before the die state of the wafer before the mold is sealed. Those who save the cost of manufacturing. In order to have a more detailed and clear understanding of the purpose, effect, and characteristics of the present invention, the preferred embodiment of the present invention will be described in conjunction with the drawings as follows: First, please refer to the first figure, which is a preferred embodiment of the present invention. Process flow-block diagram, as shown in the figure. As can be seen from the previous knowledge, the general packaging operation process can be roughly divided into operating steps such as substrates on wafers, wire bonding, mold sealing, solder balls and punching. The test method 1 of the wafer in the die state of the present invention is implemented after the aforementioned conventional wire bonding operation and before the mold sealing operation; the die test method 1 mainly includes positioning 1 1 and alignment 1 2 in order. , Signal output 1 3, detection and comparison 1 4 and other steps; the detailed description of the process of each step is as follows. Please refer to the second and third figures at the same time, which are schematic diagrams of the implementation status of the positioning and alignment steps of a preferred embodiment of the present invention, and a schematic diagram of a bare crystal test device of a preferred embodiment of the present invention, as shown in the figure. The positioning step 1 1 i can use a robotic arm or a conveyor belt to transfer the wafer module 2 to the positioning base 31, wherein the wafer module 2 has a substrate 2 1 and a substrate 2 is positioned on the substrate Η. The wafer (d 1 e) 2 2 in a bare state, and the side of the wafer 2 2 is connected to the substrate 21 with a plurality of wires 23, and the bottom of the substrate 2 1 corresponds to the junction of one end of the wires 2 3 Ball pads for pre-supplied solder ball positioning

445 5 Ο Ο 五、發明說明(5) " ' - H ’而於對位步驟1 2,係利用一測試台3 2上之多數探針, 對位頂觸於前述相對應之球墊24。 泣_接著於訊號輸出步驟23中,係由測試台32將一測試電 =二由探針321及球墊24輸入’而使晶圓22内部構成—迴 最後進行偵測比較步驟24 ’係接收自球墊24輸出之晶 迴路的電壓訊號,並與預設值進行比較,俾以於封模 二^知判斷晶圓2 2内部迴路之短路或開路狀況(即晶圓内 ^ k路之不良接點的正確位置),藉此於封模前能即時補 =線路不良之半成品,以改善習知於封模後才進行測試作 。,一旦發現接點不良則整個成品需報廢,以致造成製造 成本提高等缺失。 '仍請參閱第二、三圖所示,本發明用以達成前述測試 方法之裸晶測試裝置3 ,其主要係包含有一機架33、一設 置於機条33上之定位基台31、一設於定位基台31下方之機 木上之測试台3 2 ' 一設於定位基台31上用以壓制晶圓2 2 達疋位之定位裝置34,以及一設於測試台32下方且可連動 測試台32昇降移動之昇降裝置35等構件;纟中,該測試台 32頂面係配合晶圓22之線路設計而佈置有多數個探針32 1 ’且該測試台32並連設有—可提供測試電流與接收偵測電 壓之測試機322 ;該定位裝置34係具有多數個立置於定位 基台31上之導桿341 ,以及一可循該等導桿341昇降位移 之壓制座3 4 2等構件’該壓制座3 4 2上對應於晶圓2 2之置 放處係設有一凹槽343 ’以令壓制座342降下壓制晶圓組 2之基板21時’晶圓22恰可相對伸置於該凹槽343中;另445 5 Ο Ο 5. Description of the invention (5) "--H 'And in the alignment step 12, most of the probes on a test bench 32 are used, and the alignment top touches the corresponding ball pad 24. . Wee_ Next in the signal output step 23, the test bench 32 inputs a test electric = two by the probe 321 and the ball pad 24 'to make the wafer 22 internal structure-go back to the detection and comparison step 24' Receive The voltage signal of the crystal circuit output from the ball pad 24 is compared with the preset value, so as to determine the short circuit or open circuit condition of the internal circuit of the wafer 2 (that is, the failure of the ^ k circuit in the wafer). The correct position of the contact point), so that the semi-finished product can be compensated immediately before the mold is sealed to improve the habit of testing before the mold is sealed. Once the contact is found to be bad, the entire finished product needs to be scrapped, resulting in a lack of increased manufacturing costs. 'Still referring to the second and third figures, the bare-crystal test device 3 for achieving the foregoing test method according to the present invention mainly includes a frame 33, a positioning base 31 provided on the bar 33, a A test stand 3 2 ′ provided on the machine wood below the positioning base 31, a positioning device 34 provided on the positioning base 31 to suppress the wafer 2 2 to the position, and a positioning device 34 provided below the test stand 32 and A lifting device 35 and other components capable of interlocking with the test bench 32 can be linked; in the middle, the top surface of the test bench 32 is arranged with a plurality of probes 32 1 ′ in accordance with the circuit design of the wafer 22 and the test bench 32 is provided in parallel. —Testing machine 322 capable of providing test current and receiving detection voltage; the positioning device 34 has a plurality of guide rods 341 standing on the positioning base 31, and a pressing seat capable of following the guide rods 341 for lifting and displacement 3 4 2 and other components' The pressing seat 3 4 2 is provided with a groove 343 in the place corresponding to the wafer 2 2 'to enable the pressing seat 342 to lower the substrate 21 of the wafer group 2' wafer 22 is just Can be relatively extended into the groove 343; another

五、發明說明¢6) 外,該昇降裝置3 5係可為液壓缸,該液壓缸並具有一可伸 縮移動之伸縮桿3 5 1 ,該伸縮桿3 5 1另一端係固設於測試 台3 2底部。 藉此於檢測晶圓2 2内部迴路之開、短路狀況時,僅需 將待測試之晶圓模組2 定位於該定位基台3 1上,利用一測 試台3 2上之多數探針3 2 1對位頂觸預設於該晶圓模組2之 基板2 1底面之球墊2 4,利用測試機3 2 2 將一測試電流經由 測試台3 2上之探針3 2 1 及球墊2 4輸入,俾使晶圓2 2内部構 成一迴路,同時該測試機3 2 2 並透過測試台3 2偵測比較自 :墊2 4輸出之晶圓2 2迴路的電壓訊號,藉此於晶圓2 2封模 前即可測知判斷晶圓2 2内部迴路之不良接點的正確位置, 以即時補救線路不良之半成品,若於檢測過程中測得兩個: 以上之晶圓模組相同具有不良接點的情形,即可合理懷疑. 該裸晶測試裝置之預設參數有誤,而予以即時調整,避免; 損失擴大。 ’ 是以,本發明晶圓於裸晶狀態之測試方法及其裝置, 係藉由將待測試之晶圓模組定位於一定位基台上,利用一 測試台上之多數探針對位頂觸預設於該晶圓模組底面之球 墊,由測試台將一測試電流經由探針及球墊輸入,而使呈 .,晶狀態之晶圓内部構成一迴路,同時該測試台並偵測比 較自球墊輸出之裸晶迴路的電壓訊號,藉此提供一種於封 模前即可實施且檢測方式簡單之裸晶測試方法及其裝置, 使得晶圓於灌膠封模前之裸晶狀態即可先行測知判斷其内 部迴路之不良接點的正確位置,亦即可檢測出打線之失敗V. Description of the invention ¢ 6) In addition, the lifting device 3 5 series can be a hydraulic cylinder, and the hydraulic cylinder has a telescopic rod 3 5 1 which can be telescopically moved, and the other end of the telescopic rod 3 5 1 is fixed on the test bench. 3 2 bottom. Therefore, when detecting the open and short circuit conditions of the internal circuit of the wafer 22, it is only necessary to position the wafer module 2 to be tested on the positioning base 31, and use most of the probes 3 on a test platform 32. 2 1 Alignment top contacts the substrate 2 preset on the wafer module 2 1 The ball pad 2 on the bottom surface 2 and a test machine 3 2 2 is used to pass a test current through the probe 3 2 1 and the ball on the test table 3 2 Pad 2 4 input, so that the wafer 2 2 internally constitutes a loop. At the same time, the tester 3 2 2 detects and compares the voltage signal of the wafer 2 2 circuit output from the pad 2 4 through the test bench 32. Before the wafer 2 2 is sealed, the correct position of the bad contact in the internal circuit of the wafer 2 2 can be determined to immediately remedy the semi-finished product with the defective circuit. If two are detected during the inspection process: If the same group has bad contacts, it can be reasonably suspected. The preset parameters of the bare chip test device are wrong, and they can be adjusted immediately to avoid loss; the loss is enlarged. '' Therefore, the method and device for testing a wafer in a bare state according to the present invention is to position the wafer module to be tested on a positioning base and use most of the probes on a test stand to align and touch. The ball pad which is preset on the bottom surface of the wafer module, a test current is input by the test bench through the probe and the ball pad, so that the wafer inside the crystal state constitutes a loop, and the test bench detects The voltage signal of the die circuit output from the ball pad is compared, so as to provide a die test method and device that can be implemented before the mold sealing and the detection method is simple, so that the wafer is in the state of the die before the mold is filled and sealed. You can test and determine the correct position of the bad contact in the internal circuit first, and you can also detect the failure of wiring.

_4455 0 Q_ 五、發明說明(7) 率(如是否有打線之弧高不足而造成線塌所引起之短路現 象等),以即時補救線路不良之半成品,若於檢測過程中 測得兩個以上之相同不良接點,還可合理懷疑該裸晶測試 裝置之預設參數有誤,而予以即時調整,避免損失擴大, 同時由於本發明不需在打線步驟之後實施人工檢測,可避 免習知以人肉眼檢測時因人為因素而產生誤判現象,更可 節省人力資源的耗費,故能確實達到節省製造成本等功效 者。 綜上所述*本發明裸晶測試方法及其裝置,係藉由於 晶圓於封模前之裸晶狀態即檢測判斷其内部迴路之不良接 點的正確位置,以即時補救線路不良之半成品,進而能達 到節省製造成本等之功效;是以,本發明誠為一進步之設 計*又未見有相同或近似之方法揭露於市,疫依法提出專 利申請。 唯,以上所述,僅係本發明之較佳實施例而已,故舉 凡應用本發明說明書及申請專利範圍所為之等效結構變 化,理應包含在本發明之專利範圍内。_4455 0 Q_ V. Description of the invention (7) The rate (such as whether there is a short-circuit phenomenon caused by wire collapse caused by insufficient arc height of the wire), in order to immediately remedy the semi-finished product with poor circuit, if more than two are measured during the testing process With the same bad contacts, it is also possible to reasonably suspect that the preset parameters of the bare chip test device are wrong and adjust them immediately to avoid loss expansion. At the same time, the present invention does not need to perform manual inspection after the wire bonding step, which can avoid the conventional The human body's human body causes false judgments when it is detected by human eyes, which can save human resources, so it can really achieve the effects of saving manufacturing costs and other effects. To sum up * the bare die test method and device of the present invention are based on the bare die state of the wafer before the mold is sealed, that is, the correct position of the bad contact in the internal circuit is detected to immediately repair the semi-finished product with bad wiring. Further, it can achieve the effects of saving manufacturing costs, etc. Therefore, the present invention is a progressive design *, and no similar or similar method has been disclosed in the city, and the patent application has been filed according to law. However, the above are only the preferred embodiments of the present invention. Therefore, any equivalent structural changes made by applying the description of the present invention and the scope of patent application should be included in the patent scope of the present invention.

苐10頁苐 Page 10

Claims (1)

145 5 0 0 六、申請專利範圍 1 —種晶圓於裸晶狀態之測試方法’其主要係依序包谷 有: 定位步驟,係將待測試之晶圓模組定位於一定位 基台上,其中,該晶圓模組係具有一基板’該基板上 定位有一晶圓,且晶圓側邊與基板連接有多數導線, 另於基板底面對應於該等導線的一端接合處係分別設 有預供錫球定位之球墊; x 對位步驟’係利用一測試合上之多數探 觸於前述相對應之球墊; +對位頂 訊號輸出步驟,係由測試台將一測試電流經由探 針及球墊輸入,而使晶圓内部構成一迴路;以及 偵測比較步驟,係接收自球墊輸出之晶圓迴路的 電壓訊號,並與預設值進行比較’藉以測知列斷晶圓 内部迴路之短路或開路狀況者。 2 ·依據申請專利範圍第1項所述晶圓於裸晶狀態之測試 方法,其中,於定位步驟中’係可利用機械手臂將晶 圓模組夹取傳送至定位基·台上者° 3 .依據申請專利範圍第丄項所述晶圓於裸晶狀態之測試 方法,其中,於定位步驟中丄係可利用輸送帶傳輸方 式將晶圓模組輸送至定位基ΰ上者 4 . ~種晶圓於裸晶狀態之測試裝置’其主要係包含有- 機架,—設置於機架上之定位基=,一設於定位基台 下方之機架上之測試台設於定位基台上用以壓制 晶圓模組達定位之定位裝礬,以及一設於測試台下方 六、申請專利範圍 且可連動測試台昇降移動之昇降裝置等構件;其中, 该測试台頂面係配合裸晶狀態之晶圓線路没計而佈置 有多數個探針,且該測試台並連設有一可提供測試電 流與接收偵測電壓之測試機者。 a _依據申請專利範圍第4項所述之晶圓於裸晶狀態之測 試裝置,其中,該定位裝置係具有多數個立置於定位 基台上之導桿,以及一可循該等導桿昇降位移之壓制 座等構件,該壓制座上對應於晶圓之置放處係設有一 凹槽,以令壓制座降下壓制晶圓模組之基板時,晶圓 恰可相對伸置於該凹槽中者。 & ·依據申請專利範圍第4項所述之晶圓於裸晶狀態之測 試裝置,其中,該昇降裝置係可為液壓缸,該液壓缸 並具有一可伸縮移動之伸縮桿,該伸縮桿另一端係固 設於測試台底部者。145 5 0 0 VI. Application for Patent Scope 1-A test method for wafers in bare die state. The main methods are as follows: The positioning step is to position the wafer module to be tested on a positioning base. Wherein, the wafer module has a substrate. A wafer is positioned on the substrate, and a plurality of wires are connected to the side of the wafer and the substrate. In addition, a joint on one end of the bottom of the substrate corresponding to the wires is provided with a pre-assembly. Ball pad for solder ball positioning; x Alignment step 'uses most of the closed test to touch the corresponding ball pad; + Alignment top signal output step, a test current passes a test current through the probe And ball pad input to form a loop inside the wafer; and a detection and comparison step is to receive the voltage signal of the wafer loop output from the ball pad and compare it with a preset value to detect the inside of the wafer. Short circuit or open circuit conditions. 2 · According to the test method of the wafer in the bare die state described in item 1 of the scope of the patent application, in the positioning step, the robot module can be used to grip and transfer the wafer module to the positioning base · on the stage ° 3 According to the test method of the wafer in the bare state described in item (2) of the scope of the patent application, in the positioning step, the wafer module can be transported to the positioning base by using a conveyor belt transmission method. The test device of the wafer in the bare die state mainly includes-a rack,-a positioning base set on the rack =, and a test stand on a rack below the positioning base is set on the positioning base. A positioning device for pressing wafer modules to achieve positioning, and a lifting device such as a patent application and a lifting device that can be linked to the testing table, which are located below the testing table; among them, the top surface of the testing table is matched with bare The wafer line in the crystalline state is provided with a plurality of probes, and the test bench is also connected with a tester that can provide a test current and receive a detection voltage. a _ The test device for a wafer in a bare state according to item 4 of the scope of the patent application, wherein the positioning device has a plurality of guide rods standing on a positioning abutment, and a guide rod capable of following the guide rods A component such as a pressing seat for lifting and displacing is provided with a groove on the pressing seat corresponding to the placement of the wafer, so that when the pressing seat lowers the substrate of the pressing wafer module, the wafer can be relatively extended into the depression. Those in the slot. & The testing device for the wafer in bare state according to item 4 of the scope of the patent application, wherein the lifting device can be a hydraulic cylinder, and the hydraulic cylinder has a telescopic rod that can be telescopically moved, and the telescopic rod The other end is fixed at the bottom of the test bench. 第13頁Page 13
TW89107351A 2000-04-19 2000-04-19 Method and device for testing wafer in a bare die state TW445500B (en)

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