TW444367B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TW444367B
TW444367B TW089109313A TW89109313A TW444367B TW 444367 B TW444367 B TW 444367B TW 089109313 A TW089109313 A TW 089109313A TW 89109313 A TW89109313 A TW 89109313A TW 444367 B TW444367 B TW 444367B
Authority
TW
Taiwan
Prior art keywords
hole
semiconductor device
scope
patent application
item
Prior art date
Application number
TW089109313A
Other languages
Chinese (zh)
Inventor
Ruei-Yu Juang
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to TW089109313A priority Critical patent/TW444367B/en
Application granted granted Critical
Publication of TW444367B publication Critical patent/TW444367B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Landscapes

  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

A semiconductor device which comprises a die pad; a chip connecting with the die pad; a plurality of pins on the periphery of the die pad; conductive metal wires connected between the chip and those pins; and, an encapsulation for enclosing the pins, the conductive metal wires and at least the outer portion of the bottom surface of the die pad by exposing the outer surface and the bottom surface of these pins; in which, these pins are configured with at least a pin hole penetrated or non-penetrated through the pin depth direction and the pin hole comprises different projection section areas along the axial direction that are formed with at least one projection section area smaller than another projection section area underneath or with axial extension by slanting to the perpendicular such that these pins can be effectively bonded with the encapsulation by the tight adherence between the inner wall of the pin hole and the encapsulation filling within these pin holes. Accordingly, no delamination or loss of pin is occurred between the pins and the encapsulation.

Description

4443 6 7 A7 ______B7_____ 五、發明說明（1 ) 本發明係有關一種半導體裝置，尤指一種得令導腳與 封裝膠體緊密接合’使無脫層或導腳脫落等問題產生之半 導體裝置。 請 先 闓 讀 背 面 之 注 意 事 項 再 I敦 頁 隨著目前朝向輕、薄、短、小、快之趨勢急速發展之 半導體裝置技術之進步’以小尺寸與高效能取勝之 QFN(Quad Flat Non-lead)封裝件亦告問世。此種QFN 封裝件係如第1圖所示，主要包括晶片座1，接合於該晶 片座1上之晶片2,設置於該晶片座1周圍之導腳3,連設 於該晶片2與導腳3間之導電金屬線4，以及以使該等導 腳3之外側表面3a及底側表面3b外露之方式將該等導腳 3、晶片2、導電金屬線4、以及該晶片座1加以包覆之封 裝膠體5。由於此種QFN封裝件係摒棄傳統QFP(Quad Flat Package)封裝件利用引出腳（External)與印刷電路板 (Printed Circuit Board)導電連接之方式，而改以其導腳3 之底側外露表面3b直接與印刷電路板導電連接，故可省卻 引出腳之配置，使其尺寸大小可較傳統之QFp封裝件縮小 達60%。此外’此種qfn封裝件沒有引出腳之導腳設計， 經濟部智慧財產局員工消費合作社印製 亦因可提供更短之訊號值輪路梅，使可獲得更佳之電子運 作效率。 另一種QFN封裝件係如第2圖所示，其係選擇將晶片 座ί’之下表面向外露出’俾獲得更直接而有效之散熱途 徑’以提昇其散熱效果。 上述由第1及2圖所示之兩種QFN封裝件之導腳3 由於外側表面3a及底側表面3b皆外露於封裝膠體5之 本紙張尺度適用中@國家標準（CNS)A4規格（21Q x 297公爱〉 1 16004 經濟部智慧財產局員工消費合作社印f A7 B7 五、發明說明（2) 外’僅餘内側、上側以及兩厚度側表面係包覆於移體5中， 故因接觸面積減少而令導腳3與封裝勝體5間之黏著性降 低’使易造成導腳3與封裝膠體5間之脫層（Delaminati〇n) 現象’甚至造成切單（Singulation)後導腳3脫落等嚴重損 及產品信賴性之品質問題。 是以’為加強封裝膠體5在導腳3上之附著力，遂有 如第卜2圖所示在導腳3之上表面以例如姓刻等方式形成 至少一栓孔6之設計’使封裝膠體5亦可充滿於該栓孔6 中’俾增加導腳3與封裝膠體5間之接觸面積，並提昇其 間之黏著效果。 惟’實際上由於導腳3之尺寸極小，表面積有限，即 使有上述栓孔6之形成’其附著力仍嫌不足，而難以徹底 解決脫層或導腳脫落等問題。 因此’本發明之目的即在提供一種得在導腳與封裝膠 體之間提供絕佳之黏著效果，使無產生脫層或導腳脫落之 虞’而可確保高產品信賴性與品質之半導體裝置。 為達本發明上揭及其他目的，本發明之半導體裝置係 包括·‘晶片座；接合於該晶片座上之晶片；設置於該晶片 座周圍之多數導腳；連設於該晶片與該等導腳間之導電金 屬線，以及以使該等導腳之外側表面及底側表面外露之方 式將該等導腳、晶片、導電金屬線，以及該晶片座之至少 底側表面以外之部份加以包覆之封裝膠體；其中，該等導 腳上分別設有至少一貫穿或未貫穿該導腳厚度方向之栓 扎，且該栓孔係以沿其轴向具有不同投影截面積，且其中 本紙張尺度適用中國國家標準（CNTS)A4規格（210 X 297公釐） 16004 ------------裳--------訂---------線 {請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消费合作社印製 A7 B7 五、發明說明（3) 至少有一投影裁面積係小於位在其下方之另一投影截面積 之方式，或是以相對於鉛垂線傾斜之軸向延設之方式加以 形成’俾藉由該等栓孔内壁與充滿於該等栓孔中之封裝膠 想間之緊密嵌合作用’令該等導腳與封裝膠體間之黏著效 果大幅提昇，使無脫層或導脚脫落等問題。 以下茲參酌附圖詳細說明本發明之較佳實施例。 [圖式簡單說明] 第1圖係為已知QFN封裝件之剖視圖，其中晶片暨晶 片座係完全包覆於封裝膠體之中； 第2圖係為另一已知qfn封裝件之剖視圖，其申晶片 座之底側表面係外露於封裝膠體之外； 第3圖係為本發明第一實施例之剖視圖； 苐4a及4b圖係分別為第3®所示本發明第一實施例 之導腳之仰視圖及俯視圖； 第5圖係為本發明第二實施例之導腳之剖視圖； 第6圖係為本發明第三實施例之導腳之剖視圖； 第7圖係為本發明第四實施例之導腳之剖視圖； 第8圖係為本發明第五實施例之導腳之剖視圖； 第9a及9b圖係為本發明第六實施例之導腳之剖視 圖； 第10圖係為本發明第七實施例之導腳之剖視圖； 第11圖係為本發明第八實施例之導腳之剖視圖；以及 第12圓係為本發明第九實施例之導腳之剖視圖。 如第3、4a及4b圖所示’本發明之第一實施例係包括 --I-------[ I L - I I I f I 1 I — — — — — — — — {請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用令國國家標準（CNS)A4規格mo X 297公爱） 3 16004 、 A7 B7 五、發明說明（4) 底側表面外露之晶片座1’’接合於該晶片座1，上之晶片 2’設置於該晶片座1’周圍之多數導腳3,連設於該晶片2 與該等導腳3之間之導電金屬線4，以及以使該等導腳3 之外側表面3a及底側表面3b外露之方式將該等導腳3、 晶片2、導電金屬線4,以及該晶片座j，除底侧表面以外 之部份加以包覆之封裝膠體5’同時，在該等導腳3上則 分別設有至4' 一貫穿該導腳3厚度方向之栓孔6a，使封裝 }膠艘5亦得以充滿於該栓孔6a當中。該栓孔6a係由兩圓 柱形通孔61a及62 a所組成’且其中位於上方處之通孔6ia 之軸向投影載面積係小於位在其下方處之通孔62a之軸向 投影裁面積’如此，充滿於該检孔6a内之封裝膠體5即可 藉由其投影截面積上小下大之段差結構將該導腳3緊密地 嵌扣住（亦即藉由充滿於該栓孔6a内之封裝勝體5位於具 較大投影截面積之圓柱形通孔62a中之外緣部5a抵扣於該 導腳3上因栓孔6a上下投影載面積不同而產生段差部位 3c上之扣接機構）’使導腳3得被牢牢地固接於封裝膠體5 中’即無發生脫層或脫落之虞》 第5圖所示本發明第二實施例中之拴孔6b則係由兩同 轴之半球形凹孔6〗b及62b分別以其球狀緣部相交之方式 所形成’其中位於上方處之凹孔61b具有較下方處之凹孔 62b為小之直徑，惟此處之扣接機構係藉由凹孔61b及62b 相交處所形成之段差部位3c所提供，其中該段差部位3c 之軸向投影載面積係小於其下方之凹孔62b上之任一軸向 投影載面積，故亦可達成如上述第一實施例所述之使導腳 本紙張尺度適用申國國家標準（CNS)A4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) Γ 經濟部智慧財產局員工消費合作社印製 16004 4443 67 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（5) 3得被牢固地扣接於封裝膠體5中之效果。 第6圖之第三實施例係與第5圊之第二實施例大致相 同’惟其上、下凹孔61c、62c係以不同轴之方式加以形成， 然仍得藉其相交處所形成之段差部位3c提供使導腳3牢固 嵌接於封裝膠體5中之效果。 第7圖所示之第四實施例亦與第5圖之苐二實施例大 致相同’惟其同軸形成之上、下半球形凹孔61d、62d係具 有相同之直徑’然其相交處所形成之段差部位3c仍烊提供 將導腳3固接於封裝膠體5中之效果。 第8圖之第五實施例係將第一實施例中位於下方之圓 柱形通孔以半球形凹孔62e取代，上方則仍保持圓柱形通 孔61e之方式形成，其令該圓柱形通孔61e之軸向投影裁 面積係小於位在下方之半球形凹孔62e之任一轴向投影截 面積’故得藉由其相交處所形成之段差部位3c提供如第一 實施例所揭示之使導腳3得固接於封裝膠體5中之附著效 果。 第9a圖所示第六實施例之栓孔6f係由位在上方之由 上往下呈漸缩方式形成之漸缩孔61f，以及位在下方之圓 柱形通孔62f所組成，其中該漸縮孔61f與圓柱形通孔62f 之相交處所形成之段差部位3c之軸向投影裁面積係小於 下方之圓柱形通孔62f之軸向投影載面積，故亦可充分提 供如第一實施例所述將導腳3緊密地嵌扣於該封裝膠體5 中之效果。 此外，第9a圖所示之拴孔6f亦得以上下顛倒之方式 -------- t 裝 ----- - 訂-------I _線 <請先Μ讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS>A4規袼（210 κ 297公釐） 5 16004 A7 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明（6) 予以應用’如第9b圖所示》在此應用令，變成在上方之圓 枉形通孔02f與變成在下方之漸縮孔61f之相交處所形成 之段差部位3c之軸向投影載面積仍因小於其下方之漸縮 孔61f上之任一抽向投影載面積’故可利用該下方之漸縮 孔61f之傾斜内壁提供將該導腳3向上頂提之作用，而使 導腳3得牢固地固接於封裝膠體5中。 第10圖之第七實施例所示之检孔係為一治軸向由下 往上漸縮之楔形孔6h，其_在該楔形孔6h斜壁上任一點 6lh之軸向投影裁面積皆小於位在其下方之任一點62h之 軸向投影裁面積’故令該楔形孔6h之斜壁呈現向上頸縮之 趨勢’使該斜壁得提供將導腳3上頂之作用，俾令導腳3 得緊緊附著在封裝膠艘5之中。 第11圖所示之第八實施例之栓孔6i係以相對於鉛垂 線7傾斜之軸向7i延伸之方式予以形成，其中，充滿於該 检孔6ι内之封裝膠體得藉頂緣較接近該鉛垂線7之側斜面 όΐι提供將導腳3向上頂住之作用，使導腳3得被牢固地 定位在封裝膠體5中，而不會產生脫層或脫落之困擾。 本發明之栓孔除可以上述各種實施例所示之貫穿孔形 態加以呈現之外，亦得以未貫穿導腳3厚度方向之形態來 形成。 如第12圓所示之本發明第九實施例，其栓孔6j除了 底部未貫通之外，其形狀皆與上述第9b圈所示第六實施例 之應用完全相同。在此實施例當中，位於下方側之漸縮孔 之傾斜内壁亦得如第9b圖所示實施例一般對導腳 L紙張τ関冢標準（CNS)A4規格⑽x 297公髮） ----丨丨丨丨丨丨丨I -裝--------訂—--I---線 (請先閲讀背面之注意事項再填寫本頁) d ^ ^ Λ 7 d ^ ^ Λ 7 經濟部智慧財產局員工消費合作社印製 Α7 Β7 五、發明說明（7) 有效提供向上頂住之作用，使導腳3得緊嵌於封裝膠體5 中，故亦可有效執行如同該等實施例之得將導腳3固接於 封裝膠體5中之功效。 上述各實施例中具栓孔之導腳結構除可應用於第3圓 所示之晶片座底面外露型之QFN封裝件之外，亦得有效運 用於如第1圖所示晶片座内藏式QFN封裝件中。此外，本 發明導腳上之栓孔載面形狀並非僅侷限於第4a及4b圖所 示之圖形，其他如方形、矩形、橢圓形、多邊形等等其他 可供產業有效利用之等效截面形狀亦得加以使用》再著， 上述各種栓孔之成形皆得利用現行加工技術予以完成，例 如蝕刻、軋製、鑽孔等加工法皆可加以運用。 以上所述者，僅係用以進一步詳述本發明之特點與功 效’而非用以限定本發明可實施之範疇，故在未脫離本發 明所揭示之精神與原理所完成之任何等效改變或修飾，例 如在每個導腳上設置一個以上之拴孔，將第3圖所示之上 下兩柱形通孔、第7®所示之上下兩半球形凹孔、第8圖 所示之柱形通孔與半球形凹孔等分別以不同軸之方式加以 形成’或是將第5或第6圖所示之大小徑凹孔以上下顛倒 之方式予以組成者，皆應仍為下述之專利範圍所涵蓋β [符號說明】 1 » Γ 晶片座 2 晶片 3 導腳 3a 外側表面 3b 底側表面 3c 段差部份 4 導電金屬線 5 封裝膠體 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 16004 (請先閲讀背面之注意事項再填寫本頁) '1裂--------訂-------1·線 A7 _B7_ 五、發明說明（8) 5a 外緣部4443 6 7 A7 ______B7_____ V. Description of the invention (1) The present invention relates to a semiconductor device, in particular a semiconductor device that requires the lead pins to be tightly bonded to the encapsulation gel to prevent problems such as delamination or falling of the lead pins. Please read the precautions on the back first, and then I will follow the progress of the semiconductor device technology that is rapidly developing towards the trend of light, thin, short, small, and fast. 'QFN (Quad Flat Non- Lead) packages are also available. This QFN package is shown in FIG. 1 and mainly includes a wafer holder 1, a wafer 2 bonded to the wafer holder 1, a guide pin 3 provided around the wafer holder 1, and connected to the wafer 2 and a guide. The conductive metal wires 4 between the pins 3, and the guide pins 3, the wafer 2, the conductive metal wires 4, and the wafer holder 1 are exposed so that the outer side surfaces 3a and the bottom side surfaces 3b of the guide pins 3 are exposed. Wrapped encapsulant 5. As this QFN package is abandoning the traditional QFP (Quad Flat Package) package by using the pin (External) conductive connection with the printed circuit board (Printed Circuit Board), and instead uses the exposed surface 3b on the bottom side of its guide pin 3 It is directly conductively connected to the printed circuit board, so the lead pin configuration can be omitted, so that its size can be reduced by 60% compared with the traditional QFp package. In addition, this type of qfn package does not have a guide pin design. It is also printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs because it can provide a shorter signal value, which can achieve better electronic operation efficiency. Another QFN package is shown in Figure 2. It is to choose to expose the lower surface of the chip holder ′ ′ to the outside to obtain a more direct and effective heat dissipation path ’to improve its heat dissipation effect. The guide pins 3 of the two QFN packages shown in Figures 1 and 2 above, because the outer surface 3a and the bottom surface 3b are exposed on the packaging colloid 5. This paper size is applicable in the national standard (CNS) A4 specification (21Q x 297 Public Love> 1 16004 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs f A7 B7 V. Description of the invention (2) Outside only the inner, upper, and two thickness sides are covered in the moving body 5, so the contact Decreased area reduces the adhesion between guide pin 3 and package body 5. 'Making the delamination phenomenon between guide pin 3 and package gel 5 easy' even leads to the singulation of guide pin 3 The quality problems that seriously damage the reliability of the product, such as falling off, etc., are used to strengthen the adhesion of the encapsulating gel 5 on the guide pin 3, as shown in Figure 2 on the upper surface of the guide pin 3 in a manner such as last name engraving. The design of forming at least one bolt hole 6 allows the encapsulating gel 5 to also fill the bolt hole 6 'to increase the contact area between the guide pin 3 and the encapsulating gel 5 and improve the adhesion effect therebetween. However,' actually due to the The size of foot 3 is extremely small and the surface area is limited, even with the above-mentioned bolts The formation of the hole 6 'its adhesion is still insufficient, and it is difficult to completely solve the problems such as delamination or shedding of the guide pin. Therefore, the purpose of the present invention is to provide an excellent adhesion effect between the guide pin and the encapsulating gel. In order to ensure that there is no risk of delamination or falling of the guide pins, the semiconductor device can ensure high product reliability and quality. In order to achieve the present invention and other purposes, the semiconductor device of the present invention includes a "wafer holder; A wafer on the wafer holder; a plurality of guide pins provided around the wafer holder; a conductive metal wire connected between the wafer and the guide pins; and the outer and bottom surfaces of the guide pins are exposed Method to encapsulate the guide pins, the chip, the conductive metal wire, and the encapsulation gel other than at least the bottom side surface of the chip holder; wherein the guide pins are provided with at least one penetrating or not penetrating the respectively. Bolts in the thickness direction of the guide feet, and the bolt holes have different projected cross-sectional areas along their axial directions, and the paper size applies the Chinese National Standard (CNTS) A4 specification (210 X 297 mm) 16004 ---- -------- Shang -------- Order --------- line {Please read the notes on the back before filling this page) System A7 B7 V. Description of the invention (3) At least one projected cutting area is smaller than another projected cross-sectional area below it, or is formed by an axial extension inclined relative to the vertical line. The close fitting effect between the inner walls of the bolt holes and the encapsulation glue filled in the bolt holes greatly improves the adhesion effect between the guide pins and the encapsulation gel, so that there is no problem such as delamination or fall of the guide pins. . Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. [Brief description of the drawings] Figure 1 is a cross-sectional view of a known QFN package, in which a wafer and a wafer holder are completely enclosed in a packaging gel; Figure 2 is a cross-sectional view of another known qfn package, which The bottom surface of the Shen chip holder is exposed outside the encapsulating gel; Figure 3 is a cross-sectional view of the first embodiment of the present invention; Figures 4a and 4b are the guides of the first embodiment of the present invention shown in Figure 3®, respectively. Bottom view and top view of the foot; FIG. 5 is a sectional view of the guide foot of the second embodiment of the present invention; FIG. 6 is a sectional view of the guide foot of the third embodiment of the present invention; Cross-sectional view of the guide leg of the embodiment; FIG. 8 is a cross-sectional view of the guide leg of the fifth embodiment of the present invention; FIGS. 9a and 9b are cross-sectional views of the guide leg of the sixth embodiment of the present invention; A cross-sectional view of the guide leg of the seventh embodiment of the invention; FIG. 11 is a cross-sectional view of the guide leg of the eighth embodiment of the invention; and a twelfth circle is a cross-sectional view of the guide leg of the ninth embodiment of the invention. As shown in Figures 3, 4a and 4b, 'The first embodiment of the present invention includes --I ------- [IL-III f I 1 I — — — — — — — — {Please read first Note on the back, please fill out this page again.) This paper size is applicable to the national standard (CNS) A4 specification mo X 297. 3 16004, A7 B7. 5. Description of the invention (4) The wafer holder with the bottom surface exposed 1 '' The wafer 2 ′ bonded to the wafer holder 1 is provided with a plurality of guide pins 3 around the wafer holder 1 ′, and a conductive metal wire 4 is provided between the wafer 2 and the guide pins 3, so that the The outer side surface 3a and the bottom side surface 3b of the equal guide pin 3 are exposed, and the equal guide pin 3, the chip 2, the conductive metal wire 4, and the chip holder j are covered with a package other than the bottom side surface. At the same time, the guide pins 3 are respectively provided with 4 to 4 'bolt holes 6a penetrating through the thickness direction of the guide pins 3, so that the package 5 can be filled in the bolt holes 6a. The bolt hole 6a is composed of two cylindrical through holes 61a and 62a, and the axially projected load area of the through hole 6ia located above is smaller than the axially projected cut area of the through hole 62a located below it. 'In this way, the encapsulating gel 5 filled in the inspection hole 6a can tightly buckle the guide pin 3 (ie, by filling in the bolt hole 6a) by a step structure with a small and large projection cross-sectional area. The inner package body 5 is located in the cylindrical through hole 62a with a large projected cross-sectional area, and the outer edge portion 5a is buckled on the guide pin 3 due to the difference in the projected load area of the bolt hole 6a. Connection mechanism) 'make the guide pin 3 be firmly fixed in the encapsulant 5', that is, there is no risk of delamination or falling off "The bolt hole 6b in the second embodiment of the present invention shown in Fig. 5 is caused by The two coaxial hemispherical recessed holes 6b and 62b are formed in such a manner that their spherical edges intersect each other, wherein the recessed hole 61b located at the upper portion has a smaller diameter than the recessed hole 62b at the lower portion, but here The fastening mechanism is provided by the step portion 3c formed by the intersection of the recessed holes 61b and 62b, where the step portion 3c The axial projected load area is smaller than any of the axial projected load areas on the recessed hole 62b below it, so that the paper size of the guide script can be applied to the national standard (CNS) as described in the first embodiment. A4 size (210 X 297 mm) (Please read the precautions on the back before filling out this page) Γ Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 16004 4443 67 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (5) The effect of (5) 3 being firmly fastened in the encapsulating gel 5. The third embodiment in FIG. 6 is substantially the same as the second embodiment in FIG. 5 except that the upper and lower recessed holes 61c and 62c are formed in different axes. However, the step difference formed by the intersections is still required. The part 3c provides the effect of firmly engaging the guide pin 3 in the encapsulating gel 5. The fourth embodiment shown in FIG. 7 is also substantially the same as the second embodiment in FIG. 5 except that the coaxially formed upper and lower hemispherical concave holes 61d and 62d have the same diameter. However, the step difference formed at the intersection thereof The part 3c still provides the effect of fixing the guide pin 3 in the encapsulating gel 5. The fifth embodiment of FIG. 8 replaces the cylindrical through hole in the first embodiment with a hemispherical recessed hole 62e, and the cylindrical through hole 61e is still maintained on the upper side, which makes the cylindrical through hole The axial projected cutting area of 61e is smaller than any axial projected cross-sectional area of the semi-spherical concave hole 62e located below. The adhesion effect of the pin 3 is fixed in the encapsulating gel 5. The bolt hole 6f of the sixth embodiment shown in FIG. 9a is composed of a tapered hole 61f which is formed in a tapered manner from top to bottom, and a cylindrical through hole 62f which is located below. The axial projection cutting area of the stepped portion 3c formed at the intersection of the shrinkage hole 61f and the cylindrical through hole 62f is smaller than the axial projected load area of the cylindrical through hole 62f below, so it can also fully provide the same as in the first embodiment. The effect of tightly engaging the guide pin 3 in the packaging gel 5 is described. In addition, the bolt hole 6f shown in Figure 9a can also be turned upside down -------- t-install ------order -------- I _ line < read first Note on the back, please fill in this page again.) This paper size applies Chinese National Standards (CNS > A4 Regulations (210 κ 297 mm) 5 16004 A7 A7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of Inventions (6) "Apply as shown in Figure 9b". In this application order, the axial projection load area of the stepped portion 3c formed by the intersection of the round 枉 -shaped through hole 02f above and the tapered hole 61f below becomes due to It is smaller than any of the projected load areas on the tapered hole 61f below it, so the inclined inner wall of the tapered hole 61f below can be used to lift the guide pin 3 upward, so that the guide pin 3 is firm. The ground is fixed in the encapsulating gel 5. The inspection hole shown in the seventh embodiment of FIG. 10 is a wedge-shaped hole 6h that is tapered from bottom to top in the axial direction, which is at any point on the inclined wall of the wedge-shaped hole 6h. The axial projection cut area of 6lh is smaller than the axial projection cut area of 62h at any point below it, so the inclined wall of the wedge-shaped hole 6h is The upward necking tendency 'enables the inclined wall to provide the function of pushing the guide pin 3 up, so that the guide pin 3 is tightly attached to the encapsulating rubber boat 5. The eighth embodiment of the bolt shown in FIG. 11 The hole 6i is formed by extending in an axial direction 7i inclined with respect to the plumb line 7, wherein the encapsulating gel filled in the inspection hole 6m can be provided with a guide foot by the top edge closer to the side inclined surface of the plumb line 7. The effect of the 3 upward holding makes the guide pin 3 be firmly positioned in the encapsulating gel 5 without the problem of delamination or falling off. In addition to the pierced holes of the present invention, the through-hole shapes shown in the various embodiments described above can be used. In addition to being presented, it can also be formed in a form that does not penetrate through the thickness direction of the guide pin 3. As shown in the ninth embodiment of the present invention as shown in the twelfth circle, the shape of the bolt hole 6j is the same as that of the first embodiment except that the bottom is not penetrated. The application of the sixth embodiment shown in circle 9b is exactly the same. In this embodiment, the inclined inner wall of the tapered hole located on the lower side must also be used for the guide foot L paper τ Setsuka standard (as shown in FIG. 9b) CNS) A4 size ⑽ x 297 public hair) ---- 丨 丨 丨 丨 丨 丨 I- Packing -------- Order --- I --- line (please read the notes on the back before filling this page) d ^ ^ Λ 7 d ^ ^ 7 System A7 B7 V. Description of the invention (7) Effectively provides the upward holding effect, so that the guide pin 3 must be tightly embedded in the encapsulating gel 5, so it can also be effectively performed as in these embodiments. Encapsulation effect in colloid 5. In the above embodiments, the pin structure with pin holes can be applied not only to the QFN package with the exposed bottom surface of the wafer holder shown in the third circle, but also can be effectively applied to the built-in wafer holder shown in Fig. 1. QFN package. In addition, the shape of the carrying surface of the bolt hole on the guide leg of the present invention is not limited to the figures shown in Figures 4a and 4b. It must be used again ", the above-mentioned formation of various bolt holes can be completed using current processing technology, such as etching, rolling, drilling and other processing methods can be used. The above are only used to further detail the features and effects of the present invention, and not to limit the scope of the present invention. Therefore, any equivalent changes made without departing from the spirit and principles disclosed by the present invention Or modify, for example, set more than one bolt hole on each guide leg, and make the upper and lower two cylindrical through holes as shown in Figure 3, the upper and lower two hemispherical concave holes as shown in Figure 7®, Column-shaped through holes and hemispherical concave holes are formed in different axes respectively, or if the large-diameter concave holes shown in Figure 5 or 6 are formed upside down, they should still be as follows Covered by patent scope β [Symbol description] 1 »Γ Chip holder 2 Chip 3 Guide pin 3a Outer surface 3b Bottom side 3c Segment difference 4 Conductive metal wire 5 Encapsulating colloid (210 X 297 public love) 16004 (Please read the precautions on the back before filling in this page) '1 crack -------- order --------- 1 · line A7 _B7_ V. Description of the invention ( 8) 5a outer edge

6、6a、6b、6c、6d、6e、6f、 栓孑 L 、6h ' 6i、6j、 61a、62a圓柱形通孔 61b 、 62b 、 61c 、 62c 、 61d > 62d 半球形凹孔 61 e 圓柱形通孔 62e 半球形凹孔 61f、61j漸縮孔 61i 側斜面 62f、62j圓柱形通孔 7 鉛垂線 7i 傾斜軸 <請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210« 297公釐） 8 160046, 6a, 6b, 6c, 6d, 6e, 6f, bolts L, 6h '6i, 6j, 61a, 62a cylindrical through holes 61b, 62b, 61c, 62c, 61d &62; hemispherical recessed hole 61e cylindrical Through hole 62e Hemispherical recessed hole 61f, 61j Taper hole 61i Side bevel 62f, 62j Cylindrical through hole 7 Plumb line 7i Inclined axis < Please read the precautions on the back before filling out this page) Employees, Bureau of Intellectual Property, Ministry of Economic Affairs Paper sizes printed by consumer cooperatives are in accordance with China National Standard (CNS) A4 (210 «297 mm) 8 16004

Claims (1)

裝置 經濟部智慧財產局員工消費合作社印5取 9 443 6 7 六、申請專利範圍 i. 一種半導體裝置，包括： 晶片座； 晶片’係接合於該晶片座上； 多數導腳’係設置於該晶片座周圍，且各該導腳上 仝別設有至少一检孔’該检孔沿其抽向係具有不同之投 影裁面積’同時其中至少有一投影截面積小於位在其下 方之另一投影截面積； 導電金屬線’係連設於該晶片與該等導腳之間：以 及 封裝應想，係以使該等導腳之外側表面及底侧表面 外露之方式將該等導腳、晶片、導電金屬線，以及該晶 片座之至少底側表面以外之部份加以包覆在内。 厶如申請專利範圍第1項之半導體裝置’其中該栓孔係貫 穿於該導腳之厚度方向。 5.如申請專利範圍第1項之半導體裝置，其中該栓孔係未 貫穿該導腳之厚度方向》 4·如申請專利範圍第1、2或3項 栓孔係由位於上方之柱形通孔及位於下方之沿軸向由 下往上漸縮之漸缩孔所形成。 5.如申請專利範圍第1或2項之半導體裝置，其中該栓孔 係由位於上方之具有小軸向投影裁面積之柱形通孔及 位於下方之具有大軸向投影裁面積之柱形通孔所形 成。 ό·如申請專利範圍第1或2項之半導體裝置，其中該栓孔 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公爱） 16004 (請先閱讀背面之注意事項再填寫本頁) Ί i ---- -- 訂-- -------'' A8 B8 C8 —________m 六、·申請專利範圍 係由位於上方之具有小直徑之半球形凹孔及位於下方 之具有大直徑之半球形凹孔所形成。 7. 如申請專利範圍第2項之半導體裝置，其令該拴孔 係由位於上方之具有大直徑之半球形凹孔及位於下方 之具有小直徑之半球形凹孔所形成β 8. 如申請專利範圍第！或2項之半導體裝置，其中該栓孔 係由分別位於上方與下方之兩個具有相同直徑之半球 形凹孔所形成。 9. 如申請專利範圍第1或2項之半導體裝置，其中該栓孔 係由位於上方之柱形通孔及位於下方之具有較該上方 之栓形通孔軸向投影載面積為大之轴向投影截面積之 半球形凹孔所形成。 10. 如申請專利範圍第5項之半導體裝置，其中該上、下通 孔係以同軸方式形成。 11. 如申請專利範圍第5項之半導艘裝置，其中該上、下盪 孔係以不同轴方式形成。 12. 如申請專利範圍第6項之半導體裝置，其中該上、下四 孔係以同轴方式形成。 13·如申請專利範圍第6項之半導體裝置，其中該上、下四 孔係以不同軸方式形成。 】4,如申請專利範圍第7項之半導體裝置，其中該上、下四 孔係以同軸方式形成。 1乂如申請專利範圍第7項之半導體裝置，其中該上、Τ四 孔係以不同軸方式形成。 本紙張尺度適闬+ S㈣家標準規格（210 X 297公釐） 16004 --------------裝--- (請先閱讀背面之注意事項再填寫本頁) 訂： 經濟部智慧財產局員工消費合作社印製 10 A8SC8D8 /：* 443 6 7 六、申請專利範圍 16. 如申請專利範圍第8項之半導體裝置，其中該上、下凹 孔係以同軸方式形成。 17. 如申請專利範圍第8項之半導體裝置，其中該上、下凹 孔係以不同轴方式形成。 18. 如申請專利範圍第9項之半導體裝置，其令該通孔與該 凹孔係以同軸方式形成。 19. 如申請專利範圍第9項之半導體裝置，其中該通孔與該 凹孔係以不同轴方式形成》 20. 如申請專利範圍第2項之半導體裝置，其中該栓孔 係由位於上方之沿轴向由上往下漸縮之漸縮孔及位於 下方之柱形通孔所形成。 21，如申請專利範圍第1或2項之半導體裝置，其中該栓孔 係為沿軸向由下往上漸縮之楔形孔。 22· —種半導體裝置，包括： 晶片座； 晶片，係接合於該晶片座上； 多數導腳，係設置於該晶片座周圍，且各該導腳上 分別設有至少一栓孔，該栓孔係以相對於鉛垂線傾斜之 軸向延設； 導電金屬線，係連設於該晶片與該等導腳之間；以 及 封裝膠體，係以使該導腳之外側表面及底側表面外 露之方式將該等導腳、晶片、導電金屬線，以及該晶片 座之至少底側表面以外之部份加以包覆在内。 本紙張〜艾過用中國國家標準（CNS)A4規格⑵Q χ观公爱） 16004 1 ---I I I I--1 — -,\· I - I — —II I ί I I I--- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員Η消費合作社印t 11 經濟部智慧財產局員工消費合作杜印製 A8 B8 CS D8 六、申請專利範圍 23.如申請專利範圍第22項之半導體裝置，其令該栓孔係 貫穿於該導腳之厚度方向。 -------------裝·-------訂---------線 (請先閱讀背面之注^事項再填寫本頁) 本紙張尺度遺用中國國家標準規格（210 X 297 t釐） 12 16004Consumer Cooperatives of Intellectual Property Bureau of the Ministry of Device Economy Print 5 to get 9 443 6 7 6. Scope of patent application i. A semiconductor device includes: a wafer holder; the wafer is connected to the wafer holder; most of the guide pins are provided on the Around the chip holder, each of the guide pins is provided with at least one inspection hole 'the inspection hole has a different projection cutting area along its pumping direction', and at least one of the projection cross-sectional areas is smaller than another projection located below it Cross-sectional area; the conductive metal wire is connected between the chip and the guide pins: and the package should be such that the guide pins and chips are exposed in such a way that the outer and bottom surfaces of the guide pins are exposed , The conductive metal wire, and a portion of at least the bottom side surface of the chip holder is covered. (For example, the semiconductor device according to item 1 of the scope of patent application, wherein the bolt hole penetrates through the thickness direction of the guide pin. 5. The semiconductor device according to item 1 of the scope of patent application, wherein the bolt hole does not penetrate the thickness direction of the guide pin. The hole and the tapered hole which is located downward and tapered from the bottom to the top are formed. 5. The semiconductor device according to item 1 or 2 of the patent application scope, wherein the bolt hole is formed by a cylindrical through hole with a small axial projection cutting area located above and a cylindrical shape with a large axial projection cutting area located below. Vias are formed. If you apply for a semiconductor device with the scope of patents 1 or 2, the paper size of the bolt hole is applicable to the Chinese National Standard (CNS) A4 specification (210 x 297 public love) 16004 (Please read the precautions on the back before filling in this (Page) Ί i -----Order-------- '' A8 B8 C8 —________ m 6. The scope of patent application is composed of a hemispherical recessed hole with a small diameter located on the upper side and a lower one It is formed by a hemispherical concave hole with a large diameter. 7. For a semiconductor device with the scope of patent application No. 2, the bolt hole is formed by a semi-spherical concave hole with a large diameter located above and a semi-spherical concave hole with a small diameter located below. No. of patent scope! Or the semiconductor device of item 2, wherein the plug hole is formed by two hemispherical concave holes having the same diameter, which are located above and below, respectively. 9. For a semiconductor device according to item 1 or 2 of the scope of patent application, wherein the bolt hole is composed of an upper cylindrical through hole and a lower shaft having a larger axial projection load area than the upper through hole. It is formed by a hemispherical concave hole with a projected cross-sectional area. 10. The semiconductor device as claimed in claim 5 in which the upper and lower through holes are formed coaxially. 11. For the semi-guided ship device of the scope of application for patent No. 5, wherein the upper and lower swing holes are formed in different axes. 12. The semiconductor device according to item 6 of the patent application, wherein the upper and lower four holes are formed coaxially. 13. The semiconductor device according to item 6 of the application, wherein the upper and lower four holes are formed in different axes. [4] The semiconductor device according to item 7 of the scope of patent application, wherein the upper and lower four holes are formed coaxially. 1) The semiconductor device according to item 7 of the scope of patent application, wherein the upper and lower T-holes are formed in different axes. This paper is suitable for standard size + S family standard (210 X 297 mm) 16004 -------------- install --- (Please read the precautions on the back before filling this page) Order : Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 10 A8SC8D8 /: * 443 6 7 VI. Application for patent scope 16. For the semiconductor device with scope of patent application No. 8, the upper and lower recessed holes are formed coaxially. 17. The semiconductor device as claimed in claim 8 wherein the upper and lower recessed holes are formed in different axes. 18. For a semiconductor device according to item 9 of the scope of patent application, the through hole and the recessed hole are formed coaxially. 19. For a semiconductor device according to item 9 of the patent application, wherein the through-hole and the recessed hole are formed in different axes. 20. For a semiconductor device according to item 2 of the patent application, wherein the bolt hole is located above It is formed along the axial direction by a tapered hole that is tapered from top to bottom and a cylindrical through hole located below. 21. The semiconductor device according to item 1 or 2 of the patent application scope, wherein the bolt hole is a wedge-shaped hole that tapers from bottom to top in the axial direction. 22 · A semiconductor device comprising: a wafer holder; a wafer connected to the wafer holder; a plurality of guide pins disposed around the wafer holder, and each of the guide legs is provided with at least one bolt hole, the bolt The hole is extended in an axial direction inclined with respect to the plumb line; a conductive metal wire is connected between the chip and the guide pins; and a sealing gel is exposed so that the outer surface and the bottom surface of the guide pin are exposed In this way, the guide pins, the chip, the conductive metal wires, and the portion of the chip holder other than at least the bottom side surface are covered. This paper ~ Ai Guo used Chinese National Standard (CNS) A4 specifications ⑵Q χguan public love) 16004 1 --- III I--1 —-, \ · I-I — —II I ί II I --- (Please (Please read the notes on the back before filling out this page) Member of the Intellectual Property Bureau of the Ministry of Economic Affairs ΗConsumer Cooperative Cooperative Press 11 11 Consumer Consumption Cooperation by the Intellectual Property Bureau of the Ministry of Economic Affairs Du A8 B8 CS D8 6. Application for patent scope 23. If the scope of application for patent 22 In the semiconductor device, the bolt hole is penetrated in the thickness direction of the guide pin. ------------- Installation -------- Order --------- line (please read the notes on the back before filling this page) Legacy Chinese National Standard Specification (210 X 297 t%) 12 16004
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110133322A1 (en) * 2007-04-20 2011-06-09 Chipmos Technologies Inc. Leadframe for leadless package, structure and manufacturing method using the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110133322A1 (en) * 2007-04-20 2011-06-09 Chipmos Technologies Inc. Leadframe for leadless package, structure and manufacturing method using the same
US8106494B2 (en) * 2007-04-20 2012-01-31 Chipmos Technologies Inc. Leadframe for leadless package, structure and manufacturing method using the same

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