B7 五、發明說明（/) 發明領域： I月A有關於一種内欲導熱層之高散熱型積體電路基 板結構’特別是有關於—種可以提高散熱 二 而應用於覆晶封裝叫chip)^BGA基板。川士 發明背景： 對於電子晶片之封裝技術，在覆晶封裝形式可較一般打 金,（wire-bonding)封裝形式有較多製程優點，但其散熱性 乃疋關鍵之處’因此相關業界人士諸乡致力於此方面之努力。 請參閱圖一所示，其係美國專利U.S. patent No. 6,156,980 所揭露之覆晶封裝BGA基板結構示意圖。該基板⑴主要包 括一上電路層12、-下電路層14及複數個導熱栓. ^ 一晶片20係藉由凸塊(BumP)i§耦合於基板ίο，而因該 導熱栓16係設於基板10結構中，其主要目的係做為該基板 10之導熱者，使晶片2G所產生之熱量可以藉由導熱栓16散 發至外界。 ’、、、:而$知技術之基板1〇結構具有導熱提昇有限以及製 程複雜等缺點，究其原因主要係因為·· a·習知技術之基板10對於晶片2〇之散熱方式係藉由複數個 導熱栓Μ將熱量傳導至外界，但是導熱检1ό可供晶片2〇 散熱之截面積有限，因而導致整體封裳元件之散熱效果不 佳，相對地也就影響到晶片2〇之工作效能與穩定性。 b·習知技術之敍1G姐置導錄16時，必_過鑽孔、 鑛銅以及塞孔等複雜餘，不僅費時且增加製 此 591775 A7 五、發明說明（J ) 將產生l6^孔不"全而有許多殘留的小空隙存在， 將產生Popcorn現象，而降低導熱效能。 因此，對於從事晶片20之封梦童本替 之散熱效果之改盖以提料產口業者莫不致力於基板10 又。以“其產品之品f與市場的競爭力。 發明目的： 目的在_供—細導朗之高散熱型 ===、:係主要應用覆晶封裝方式，該基板係 層取代導熱栓對晶片直接進行散熱，_僅可以 杈南日日片之工作效能與穩定性。 本發明之次要目的在於提供—種内喪導熱層之高散熱型 ，體電路基板結構，本發明所設計之導熱層形式提供基板之 南結構強度’可敎基板變形彎曲，而具战效果者。 線 為達上述之目的’本發縣提供—_嵌雜層之高散 熱型積體電路基板結構，該基板主要包括—導熱層、一層以 ^絕緣層、一上電路層、一下電路層、保護層及複數個i電 本貫施例係將‘熱層设計為基板之整個主體部分，亦即 ，板之主體即疋-整層導熱層，該導熱層具有中央區及外圍 區;，而該導熱層之材質係為高散熱性、低膨脹係數之金屬。 在该導熱層之上、下除中央區外，為—上、下絕緣層所包覆。 在:述絕緣層外並設有上、下電路層；而另設置有若干絕緣 孔貫穿上絕緣層、導熱層以及下絕緣層，使導電栓穿過絕緣 孔，使上電路層和下電路層成為導通狀態。而最外分別覆有 本紙張尺度適財國國家標準（CNS)A4規格⑽x 297公爱_ 591775 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（$ ) 將上下保護層以保護電路避免外界環境侵蝕或銲接短路。 、此外，本發明之導熱層外圍區其周圍亦可向外延伸而形 成-凸緣；不同的是，該導熱層並未設計成整層而作為基板 之整個主體部分，碰是設計為基板之巾央區域。如此，晶 片動作時產生之熱源亦可透過直接接觸之導熱層而傳導至外 界。 為了使貴審查委員對本發明之目的、特徵及功效，有 更進一步的瞭解與認同，茲配合圖式詳加說明如後： 圖式之簡單說明： 圖一係習知技術之BGA基板結構示意圖。 圖二係本發明内嵌導熱層之高散熱型積體電路基板結構 之第一實施例圖。 圖三係本發明内嵌導熱層之高散熱型積體電路基板結構 之第二實施例圖。 圖四係本發明内嵌導熱層之高散熱型積體電路基板結構 之第三實施例圖。 圖五係本發明内嵌導熱層之高散熱型積體電路基板結構 之第四實施例圖。 圖式中之圖號說明： 10, 100, 200, 300, 400•基板 12, 130, 230, 330,430-上電路層 14, 131，231，331，431-下電路層 __ 4 紙張尺度國家標準（CNS)A4規格（210 X 297公' ----—^. ---.---：--------裝--------訂-----，----線 (請先閱讀背面之注意事項再填寫本頁) 591775 經濟部智慧財產局員工消費合作社印製 A7 B7 — --—---- 五、發明說明（f ) 16-導熱检 191，291，391，491-錫球 20, 180, 280, 380, 480-晶片 110, 210, 310, 410-導熱層 110a，210a，310a，410a-導熱層中央區 110b，210b，310b，410b-導熱層外圍區 150, 250, 350, 450-導電栓 140, 240, 340, 440•上保護層 141，241，341，441-下保護層 120, 121，220, 320, 420-絕緣層 133, 233, 333, 433-銲墊 詳細說明： 本發明係針對習知技術之缺點而改善之基板結構，由於 習知技術所佈設之導熱栓之散熱效果不足，亦會影響晶片之 工作效能與穩定性，因而提出一種具有高散熱效率之内嵌導 熱層之南散熱型積體電路基板結構改良，以改善習知技術之 缺點。 清參閱圖二所示，其係本發明内嵌導熱層之高散熱型積 體電路基板結構之第一實施例圖，該BGA基板1〇〇包括一 導熱層110、一上絕緣層12〇、一下絕緣層121、一上電路層 130、一下電路層131、一上保護層14〇、一下保護層141以 及複數個導電栓150。 本實施例係將導熱層110設計為夾設於基板100内部之 _ 5 ---------------裝--- (請先閱讀背面之注意事項再填寫本頁) . ·-線· 本紙張尺度翻中國國家標^^从4規袼⑽ 297公釐） 591775 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（f ) 整層散熱結構，亦即基板100之散熱結構主體即是一整層導 熱層110，該導熱層110具有中央區110a及外圍區11〇b，而 該導熱層110之材質係為高散熱性、低膨脹係數之金屬，係 如銅或銅合金板，及鋁或鋁合金板等；在該導熱層11〇之上 下除中央區110a外包覆住有上、下絕緣層120、121。在所 述絕緣層120、121外並設有上下電路層13〇、131 ;而另設 置有若干絕緣孔135貫穿上絕緣層12〇、導熱層外圍區u〇b 以及下絕緣層121，使導電栓15〇穿過絕緣孔，而使上電路 層130和下電路層131對應之銲墊133可成為導通狀態。且 其中導電栓150之孔徑較導熱層之絕緣孔135的孔徑小，且 以絕緣材質阻隔，彼此之間不直接接觸，因此不會有短路現 象的問題產生，而上下電路層最外分別覆有上、下保護層 140、14卜並裸露出可與晶片或外界作電性耦合之銲墊， 而且设計為整層導熱層可達到較佳之散熱效果。 本發明第-實施例之BGA基板1〇〇在進行覆晶封裝 後，晶片180可藉由複數凸塊19〇分別與基板之上電路 層130，裸露於上保護層14〇之銲塾133及導熱層ιι〇相互 麵^，又該基板110下方之下電路層131裸露於下保護層⑷ 之!干塾133，可藉複數錫j求191結合於電路板之上（圖中未 示）使曰曰片I80之工作熱源藉由導熱層no直接傳導至外 界。 凊，閱圖三所示，其係、本發_嵌導熱層之高散熱型積 -電路土板Μ冓之第二實施例圖，該BGA基板2〇〇包括」 導熱層⑽、-絕緣層220、一上電路層23〇、一下電路層231、 本纸張尺㈣㈣_ ---'--：----------------訂-------^-- (請先閱讀背面之注意事項再填寫本頁) 591775 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（έ ) 一上保護層240、一下保護層241以及複數個導電栓25〇。 該V熱層210亦為一導熱板材，包括一中央區21〇a與一 外圍區210b，其中該外圍區係中央區2舰之下方周圍向外 延伸形成之凸緣；與前述實施例不同的是，該導熱層21〇並 未設計成整層，而僅是設計為基板2〇〇•之中央區域。 該絕緣層220係環繞於該導熱層中央區210a外圍，即該 ^熱層210係鑲埋於該絕緣層220之中，該上電路声 狀該絕緣㈣之上側表面，其中上電路層2料: 盍-層上保護層240,並露出可作為與晶片電性耗合之辉塾 233居下電路層231係設於該絕緣層220之下側表面覆有一 下保護層241，並露出可作為與晶片電性耦合之銲墊幻3，複 數個導電栓250係貫穿該絕緣層22〇並連接上、下電路層 230、231對應之銲墊233使其成導通狀態。 曰 第二實施例之BGA基板200在進行覆晶封.裝時，晶片 280藉由複數凸塊290分別與基板2〇〇之上電路層23〇裸露 於上保護層240之銲墊233及導熱層210相互耦合，又該下 電路層231裸露於下保護層241之銲墊233藉由複數錫球％】 可結合於電路板之上，使晶片280之工作熱源藉由導熱層21〇 直接傳導至外界。 如此，本實施例該導熱層210未設計成整層，而僅是設 計為基板200之中央區域，然晶片動作_生之熱源亦 透過直接接觸之導熱層210而傳導出。 … 請參閱圖四所示，其係本發明内料熱層之高散埶型積 體電路基板結構之第三實施例圖，本實施例在整體之基板 7 本纸張尺度適用由國國家標準（CNS)A4規格（210 X 297公爱） ----.--^--------^--------^--------Γ 1^ (請先閱讀背面之注意事項再填寫本頁) 591775 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（/ ) 300結構上大致與第二實施例相同，因此對於元件之圖示部 分不再加以贅述，其最大之不同處係在於導熱層310之中央 區310a上、下兩側周圍係向外延伸形成凸緣31〇b，使該導 熱層310之側視圖係類似一『工』字形，其主要目的係用以 強化该基板300之整體結構強度，以避免該基板3〇〇因為受 到外力的作用而發生變形彎曲，本實施例在對於晶片380之 復曰曰封裝方式與將該基板300結合於電路板的方式均與第二 實施例相同。 請參閱圖五所示，其係本發明内嵌導熱層之高散熱型積 體電路基板結構之第四實施例圖，本實施例在整體之基板 400結構上大致均與第二實施例相同，對相同之元件在圖式 部分亦不再加以贅述，其最大之不同係在於導熱層410之中 央區410a之上側周圍向外延伸形成凸緣4i〇b，該絕緣層420 係環繞於上述導熱層中央區4l〇a之外圍，即該導熱層41〇係 鑲埋於絕緣層420之中；上電路層430係設於絕緣層420之 上側表面，該下電路層431係設於絕緣層420之下側表面， 其餘部分之基板400結構以及對於晶片48〇之覆晶封裝和將 該基板400結合於電路板之方式均與第二實施例相同。 以上所述，係為本發明内嵌導熱層之高散熱型積體電路 基板結構之不同實施例詳細說明，本發明與習知技術相較其 所增加之優點至少包括有： a·本發明基板内嵌設有導熱層之中央區域，可使晶片之工作 熱源透過導熱層迅速傳遞出去（尤其是傳導電流較高之接地 導電層（groundtrace)，並且由於導熱層之中央區域面積遠 8 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公爱） ------------------訂-----.--_—線 (請先閲讀背面之注意事項再填寫本頁) 591775 A7 五、發明說明（尸） 大於習知技術所佈設之導熱栓，故本發明運用於覆晶型封裝 可具有較佳之散熱效果。 b·本發明之BGA基板其導熱層可以大量製造之後再鑲埋於 樹脂層之中，而習知技術之導熱栓必須經過鑽孔、鍍銅和塞 孔等複雜之製程，相較之下，本發明之製造成本較低且可以 避免習知技術之導熱栓發生p〇pC〇rn的現象。 C·本發明所設計之導熱層形式提供基板之高結構強度，可避 免基板變形彎曲，而具支撐效果者。 ^ m所述僅為本發明喊導鋪之高散熱型積體 二路基板結構之較佳實施例，鱗⑽鳴發明之實施範 Γ 技藝者在蝴本發_神所做之修 改，均應屬於本發明之範圍，例 散熱型結構對於上電路層與下電路層I設S直接 路，或是多層電路但各電路層之^〜17以疋单層電 該基板可以適用於各種型式^㈣導電拴相連接’使 當以下列所述之申請專利範圍做為2此本發明之保護範圍 --------訂-----.--.— (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中_家縣（CN^J^· (2l〇 X 297 公爱B7 V. Description of the Invention (/) Field of the Invention: In January A, there is a highly heat-dissipative integrated circuit substrate structure with an internal heat-conducting layer. In particular, it relates to a type that can improve heat dissipation and is used in a flip-chip package called a chip. ^ BGA substrate. Chuanshi's invention background: For electronic chip packaging technology, chip-on-chip packaging can have more process advantages than wire-bonding packaging, but its heat dissipation is the key point. Zhuxiang is committed to this endeavor. Please refer to FIG. 1, which is a schematic diagram of the structure of a flip-chip package BGA substrate disclosed in U.S. patent No. 6,156,980. The substrate ⑴ mainly includes an upper circuit layer 12, a lower circuit layer 14 and a plurality of thermally conductive pins. ^ A wafer 20 is coupled to the substrate through a bump (BumP), and the thermally conductive pin 16 is provided on the substrate In the structure of the substrate 10, its main purpose is to be a heat conductor of the substrate 10, so that the heat generated by the wafer 2G can be dissipated to the outside through the thermally conductive pin 16. ',,, and: The substrate 10 structure of the known technology has the disadvantages of limited thermal conductivity improvement and complex manufacturing processes. The reasons are mainly because a. The substrate 10 of the conventional technology uses a heat dissipation method for the wafer 20 The plurality of thermally conductive bolts M conduct heat to the outside, but the thermal conductivity test has a limited cross-sectional area for the heat dissipation of the chip 20, which results in a poor heat dissipation effect of the overall sealing element, which relatively affects the working efficiency of the chip 20 And stability. b. Knowing technology When 1G sister sets the guide 16, it is necessary to pass through complicated drilling, ore copper and plug holes, which are not only time-consuming and increase the production of this 591775 A7 V. Description of the invention (J) will produce 16 ^ holes Without " there are many small residual voids remaining, which will cause the Popcorn phenomenon and reduce the thermal conductivity. Therefore, manufacturers who are engaged in changing the heat dissipation effect of the sealer of the chip 20 for the purpose of extracting materials are committed to the substrate 10 again. "The product f of the product and the competitiveness of the market. Purpose of the invention: The purpose is to provide high-heat-dissipation type ===,:, is mainly used for flip-chip packaging, the substrate layer instead of the thermal pin on the wafer Direct heat dissipation, can only work efficiency and stability of Nanri-Japanese film. The secondary purpose of the present invention is to provide a kind of high heat dissipation type with internal heat conduction layer, body circuit substrate structure, and heat conduction layer designed by the present invention. The form provides the strength of the south structure of the substrate. The substrate can be deformed and bent, and it has a war effect. To achieve the above purpose, the "provided by the county"-a high heat dissipation type integrated circuit substrate structure with embedded layers, the substrate mainly includes — The thermally conductive layer, an insulating layer, an upper circuit layer, a lower circuit layer, a protective layer, and a plurality of i-electric embodiments are designed to design the 'thermal layer as the entire main body of the substrate, that is, the main body of the board That is, the entire layer of thermally conductive layer, which has a central area and a peripheral area; and the material of the thermally conductive layer is a metal with high heat dissipation and a low expansion coefficient. Above and below the thermally conductive layer, except for the central area, For—upper and lower insulation Above and below the insulation layer are provided with upper and lower circuit layers; and a plurality of insulation holes are provided to penetrate the upper insulation layer, the thermally conductive layer and the lower insulation layer, so that the conductive plug passes through the insulation holes to make the upper circuit. The lower layer and the lower circuit layer are turned on. The outermost layers are covered with the paper standard National Standard (CNS) A4 size ⑽x 297 public love _ 591775 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 V. Invention Description ( $) The upper and lower protective layers are used to protect the circuit from external environment erosion or soldering short circuit. In addition, the periphery of the thermally conductive layer of the present invention can also be extended outward to form a flange; the difference is that the thermally conductive layer is not designed The entire main body of the substrate is formed into a whole layer, which is designed as the central area of the substrate. In this way, the heat source generated during the operation of the wafer can also be conducted to the outside through the direct contact of the thermally conductive layer. Purpose, characteristics and effects, have a further understanding and identification, and are explained in detail with the drawings as follows: Brief description of the drawings: Figure 1 is a BGA substrate structure of conventional technology Schematic diagram. Figure 2 is a diagram of a first embodiment of a highly heat-dissipative integrated circuit board structure with a thermally conductive layer embedded in the present invention. Figure 3 is a second embodiment of a highly heat-dissipated integrated circuit board structure with a thermally conductive layer embedded in the present invention. Figure 4. Figure 4 is a diagram of a third embodiment of a highly heat-dissipative integrated circuit board structure with a thermally conductive layer embedded in the present invention. Figure 5 is a fourth embodiment of a highly heat-dissipated integrated circuit board structure with a thermally conductive layer embedded in the present invention. Figure. Explanation of drawing numbers in the drawings: 10, 100, 200, 300, 400 • Substrates 12, 130, 230, 330, 430-Upper circuit layer 14, 131, 231, 331, 431-Lower circuit layer __ 4 Paper dimensions National Standard (CNS) A4 Specification (210 X 297 Male '-------- ^. ---.---: -------- Installation -------- Order ---- -, ---- line (please read the notes on the back before filling out this page) 591775 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 — ------- V. Description of Invention (f) 16- Thermal inspection 191, 291, 391, 491-solder ball 20, 180, 280, 380, 480-wafer 110, 210, 310, 410-thermally conductive layer 110a, 210a, 310a, 410a-central area of thermally conductive layer 110b, 210b, 310b 410b-periphery of thermally conductive layer Area 150, 250, 350, 450-Conductive plug 140, 240, 340, 440Upper protective layer 141, 241, 341, 441-Lower protective layer 120, 121, 220, 320, 420-Insulating layer 133, 233, 333 , 433-Welding pad detailed description: The present invention is a substrate structure improved for the shortcomings of the conventional technology. Due to the insufficient heat dissipation effect of the thermally conductive pin provided by the conventional technology, it will also affect the working efficiency and stability of the chip, so it is proposed The structure of a south heat-dissipating integrated circuit board with a high heat dissipation efficiency and an embedded thermal conductive layer is improved to improve the shortcomings of the conventional technology. Please refer to FIG. 2, which is a first embodiment diagram of a high heat dissipation type integrated circuit substrate structure with a thermally conductive layer embedded in the present invention. The BGA substrate 100 includes a thermally conductive layer 110, an upper insulating layer 12, The lower insulating layer 121, the upper circuit layer 130, the lower circuit layer 131, the upper protective layer 140, the lower protective layer 141, and the plurality of conductive plugs 150. In this embodiment, the thermally conductive layer 110 is designed to be sandwiched inside the substrate 100. _ 5 --------------- --- (Please read the precautions on the back before filling this page ).--Line · This paper is a Chinese standard ^^ from 4 rules 袼 ⑽ 297 mm) 591775 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (f) The whole layer of heat dissipation structure, also That is, the main body of the heat dissipation structure of the substrate 100 is an entire thermally conductive layer 110. The thermally conductive layer 110 has a central region 110a and a peripheral region 110b. The material of the thermally conductive layer 110 is a metal with high heat dissipation and a low expansion coefficient. It is, for example, copper or copper alloy plate, and aluminum or aluminum alloy plate, etc .; the upper and lower insulation layers 120 and 121 are covered on the heat conducting layer 110 except the central area 110a. Upper and lower circuit layers 13 and 131 are provided outside the insulating layers 120 and 121; and a plurality of insulating holes 135 are provided to penetrate the upper insulating layer 120, the peripheral area u0b of the heat-conducting layer, and the lower insulating layer 121 so as to conduct electricity. The plug 15 passes through the insulation hole, so that the bonding pads 133 corresponding to the upper circuit layer 130 and the lower circuit layer 131 can be turned on. In addition, the hole diameter of the conductive pin 150 is smaller than that of the insulating hole 135 of the thermal conductive layer, and is blocked by an insulating material, which does not directly contact each other, so there will be no short circuit problem, and the upper and lower circuit layers are respectively covered with the outermost The upper and lower protective layers 140 and 14 expose exposed solder pads that can be electrically coupled to the chip or the outside, and are designed as a whole thermal conductive layer to achieve better heat dissipation. After the BGA substrate 100 of the first embodiment of the present invention is subjected to flip-chip packaging, the wafer 180 can be exposed to the solder layer 133 and the upper protective layer 14 by a plurality of bumps 19 and the circuit layer 130 on the substrate, respectively. The heat-conducting layers are facing each other ^, and the lower circuit layer 131 under the substrate 110 is exposed on the lower protective layer! Dry 133, which can be combined on the circuit board by a plurality of tin j 191 (not shown) to make The working heat source of the film I80 is directly conducted to the outside through the thermal conductive layer no. That is, as shown in FIG. 3, it is a diagram of a second embodiment of a high-heat-dissipation-embedded circuit board M 冓 embedded in a thermally conductive layer. The BGA substrate 2000 includes a thermally conductive layer, an insulating layer. 220, the upper circuit layer 23, the lower circuit layer 231, the size of this paper _ ---'--: ------- order ------- ^-(Please read the precautions on the back before filling this page) 591775 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (rod) A protective layer 240, a lower protective layer 241, and a plurality of conductive Tie 25. The V thermal layer 210 is also a thermally conductive sheet material, including a central area 21a and a peripheral area 210b, wherein the peripheral area is a flange formed by extending outwardly around the lower part of the central area 2 ship; different from the foregoing embodiment Yes, the thermally conductive layer 21 is not designed as a whole layer, but is only designed as the central area of the substrate 2000. The insulating layer 220 surrounds the periphery of the central region 210a of the thermally conductive layer, that is, the thermal layer 210 is embedded in the insulating layer 220. The upper circuit is acoustically on the upper side surface of the insulating layer, and the upper circuit layer 2 : 盍 -upper protective layer 240, and exposed as the electrical consumption of the chip. 塾 Lower 233 circuit layer 231 is provided on the lower side of the insulating layer 220. The protective layer 241 is covered and exposed as For the pad 3 which is electrically coupled to the wafer, a plurality of conductive pins 250 are penetrated through the insulating layer 22 and connected to the pads 233 corresponding to the upper and lower circuit layers 230 and 231 so as to be in a conducting state. In the second embodiment, the BGA substrate 200 is subjected to flip-chip encapsulation. At the time of mounting, the wafer 280 is exposed to the solder pads 233 and thermal conduction of the upper protective layer 240 through the plurality of bumps 290 and the circuit layer 23 on the substrate 200 respectively. The layers 210 are coupled to each other, and the lower circuit layer 231 is exposed on the solder pads 233 of the lower protective layer 241 by a plurality of solder balls. It can be combined on the circuit board, so that the working heat source of the chip 280 is directly conducted through the thermal conductive layer 21 To the outside world. As such, the thermally conductive layer 210 in this embodiment is not designed as a whole layer, but is only designed as the central area of the substrate 200. However, the heat source of the wafer operation is also conducted through the thermally conductive layer 210 in direct contact. … Please refer to FIG. 4, which is a diagram of the third embodiment of the structure of the high-dissipation type integrated circuit substrate of the inner thermal layer of the present invention. This embodiment is based on the overall substrate. (CNS) A4 specifications (210 X 297 public love) ----.-- ^ -------- ^ -------- ^ -------- Γ 1 ^ ( Please read the notes on the back before filling in this page) 591775 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (/) 300 The structure is roughly the same as that of the second embodiment. No longer go into details, the biggest difference is that the upper and lower sides of the central area 310a of the thermal conductive layer 310 extend outward to form a flange 31ob, so that the side view of the thermal conductive layer 310 is similar to a "work" The shape is mainly used to strengthen the overall structural strength of the substrate 300 to avoid the substrate 300 from being deformed and bent due to the external force. This embodiment is based on the packaging method and The manner in which the substrate 300 is coupled to the circuit board is the same as that of the second embodiment. Please refer to FIG. 5, which is a diagram of a fourth embodiment of the structure of a high-heat-dissipation integrated circuit substrate with a heat-conducting layer embedded in the present invention. The overall structure of the substrate 400 is substantially the same as that of the second embodiment. The same components will not be described in the drawings. The biggest difference is that the flange 4i0b is extended around the upper side of the central area 410a of the thermal conductive layer 410. The insulating layer 420 surrounds the thermal conductive layer. The periphery of the central area 410a, that is, the thermal conductive layer 41 is embedded in the insulating layer 420; the upper circuit layer 430 is provided on the upper side surface of the insulating layer 420, and the lower circuit layer 431 is provided on the insulating layer 420. The bottom surface, the structure of the remaining substrate 400, the flip-chip package for the wafer 48 and the manner of bonding the substrate 400 to the circuit board are the same as those of the second embodiment. The above are detailed descriptions of different embodiments of the structure of the high-heat-dissipation integrated circuit substrate with the heat-conducting layer embedded in the present invention. The advantages of the present invention compared with the conventional technology include at least: a. The substrate of the present invention A central area with a thermally conductive layer embedded allows the working heat source of the chip to be quickly transmitted through the thermally conductive layer (especially the ground conductive layer with a higher conduction current, and because the central area of the thermally conductive layer is far from 8 paper sizes) Applicable to China National Standard (CNS) A4 specification (21〇X 297 public love) ------------------ Order -----.--_-- line (please first (Please read the notes on the back and fill in this page again) 591775 A7 5. The description of the invention (the body) is larger than the thermal conductive bolts provided by the conventional technology, so the present invention can have better heat dissipation effect when applied to flip-chip packages. B. The thermally conductive layer of the BGA substrate can be mass-produced and then embedded in the resin layer, and the thermally conductive plug of the conventional technology must go through complicated processes such as drilling, copper plating and plugging. In comparison, the manufacturing cost of the present invention Low thermal plugs that avoid conventional techniques The phenomenon of p0pCrn occurs. C. The thermally conductive layer designed by the present invention provides high structural strength of the substrate, which can avoid deformation and bending of the substrate, and has a supporting effect. ^ M is only for the purpose of the present invention. The preferred embodiment of the structure of the two-way substrate of the high heat dissipation type integrated body, and the implementation of the invention of the scales and sounds, all modifications made by the artist in this book should belong to the scope of the present invention. The circuit layer is directly connected to the lower circuit layer, or it is a multilayer circuit, but the circuit layers are ^ ~ 17 with a single layer of electricity. The substrate can be used for various types of connection. The scope of the patent application is 2 as the protection scope of the present invention .-------- Order -----.--.-- (Please read the precautions on the back before filling this page) Home County (CN ^ J ^ · (2l〇X 297 Public Love