43 91 84 經濟部智慧財產局員工消費合作社印製 B? 五、發明說明（I ) 發明領域： 本發明係關於一種積體電路中增加低介電常數介電層 之附著力(adhesion)，特別是關於增加HSQ與其他介電層間 之附著力。 發明背景： 隨著積體電路製程邁入進深次微米階段，金屬層間內連 線(interconnect)RC時間常數延遲(RC time delay)增加的問題 是急需改善的課題之一。由於RC時間常數延遲與金屬層間 介電層(Inter Metal Dielectric; IMD)材料的介電常數 (Dielectric Constant; k)成正比，故目前可有效解決該問題的 方法之一即是以使用低介電常數之材質作爲介電層材質來 減低電容値，目前有許多有機材質被開發出來，但仍由於 作爲金屬層間介電層除了低介電常數的考量外，還需考慮 介電層的熱穩定性(thermal stability)、附著力及高斷裂強度 (breakdown strength)等性質，目前發現以 organic SOG :如 HSQ(liydrogen silsesquioxane)可作爲金屬層間介電層的材 料，上述HSQ之介電常數介於3.0至2.8之間且熱穩定性介 於400至500°C之間，其介電常數也較原本之氧化矽3.9低， 極爲適合作爲目前替代氧化矽材質。 目前在使用HSQ作爲介電層材質時，因其材質多孔性 之氧化矽材質且硬度較小，所以在使用HSO作爲介電材質 時會在HSQ上下間加介電層於其HSQ之間，因此，整個介 電層結構至少包含三層結構，但HSQ與介電層間材質的附 著力不佳產生剝離現象(pealing)，這也是HSQ —直無法寒 ---—__1____— 本紙張尺度適用令國國家標準（CNS)A4規格（210 X 297公釐） ----^-------(^ *-------^*11 — — — — — — ^ (請先閱讀背面之注意事項再填寫本頁) 43 91 8 4 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（>) 用於金屬層間介電層製程的原因，本發明係提出一增加介 電層與HSQ附著力之方法解決習知技術中運闬HSQ降低介 電常數時所面臨之問題。 發明之槪述： 本發明之目的係提供一種改善HSQ/介電層界面剝離 現象的方法，以增進積體電路元件的金屬層間介電層中， HSQ/介電層界面的接著能力。 本發明係以下列之技術手段來達到上述之目的:首先， 提供一已完成前段電路元件製作的半導體基板，於該半導 體基板上形成第一介電層，對上述之第一介電層進行表面 電獎處理，旋塗HSQ於第一介電層後，對該HSQ層進行表 面電漿處理；最後，於該HSQ層上，形成第二介電層，如 此，於第一介電層/HSQ層界面將有較好的接著能力。 圖式簡要說明： 圖一爲本發明實施例中，對介電層表面進行電漿處理 後，再形成HSQ層。 圖號說明： 10-包含電路元件的基板 20 _金屬導線結構43 91 84 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs B. V. Description of the invention (I) Field of the invention: The present invention relates to an integrated circuit that increases the adhesion of a low dielectric constant dielectric layer. It is about increasing the adhesion between HSQ and other dielectric layers. BACKGROUND OF THE INVENTION: As the integrated circuit manufacturing process moves into the deep sub-micron stage, the problem of increasing the RC time delay of interconnects between metal layers is one of the issues that need to be improved urgently. Since the RC time constant delay is directly proportional to the dielectric constant (k) of the Inter Metal Dielectric (IMD) material, one of the methods that can effectively solve this problem is to use a low dielectric constant. The constant material is used as the dielectric layer material to reduce the capacitance. At present, many organic materials have been developed. However, as a metal interlayer dielectric layer, in addition to the consideration of low dielectric constant, the thermal stability of the dielectric layer needs to be considered. (thermal stability), adhesion, and high breaking strength (breakdown strength), organic SOG: such as HSQ (liydrogen silsesquioxane) can be used as the material of the metal interlayer dielectric layer, the dielectric constant of the above HSQ is 3.0 to Between 2.8 and thermal stability between 400 and 500 ° C, its dielectric constant is also lower than the original silicon oxide 3.9, which is very suitable as the current alternative silicon oxide material. At present, when using HSQ as the material of the dielectric layer, due to its porous silicon oxide material and low hardness, when using HSO as the dielectric material, a dielectric layer is added between the HSQ and the HSQ, so The entire dielectric layer structure includes at least a three-layer structure, but the poor adhesion between the HSQ and the dielectric layer results in peeling, which is also the HSQ — it ca n’t be cold --- — __1____ — This paper is applicable to the country National Standard (CNS) A4 Specification (210 X 297 mm) ---- ^ ------- (^ * ------- ^ * 11 — — — — — — ^ (Please read first Note on the back, please fill out this page again) 43 91 8 4 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed A7 B7 V. Description of the invention (>) For the reason for the process of the interlayer dielectric layer, the present invention proposes an increase The method of the adhesion between the dielectric layer and the HSQ solves the problems faced by the conventional technology when the HSQ is used to reduce the dielectric constant. Summary of the invention: The object of the present invention is to provide a method for improving the interface peeling phenomenon of the HSQ / dielectric layer. In order to enhance the interlayer dielectric layer of the integrated circuit element, the HSQ / dielectric layer The bonding ability of the interface. The present invention achieves the above-mentioned object by the following technical means: First, a semiconductor substrate on which the previous-stage circuit elements have been manufactured is provided, and a first dielectric layer is formed on the semiconductor substrate. The dielectric layer is subjected to a surface electrical treatment. After the HSQ is spin-coated on the first dielectric layer, the HSQ layer is subjected to surface plasma treatment. Finally, a second dielectric layer is formed on the HSQ layer. The dielectric layer / HSQ layer interface will have better bonding ability. Brief description of the drawings: Figure 1 is an embodiment of the present invention, the surface of the dielectric layer is plasma treated, and then the HSQ layer is formed. Description of the number: 10 -Substrate with circuit components 20 _Metal wire structure
30-第一介電層 40-HSQ 50-第二介電層 100-第一介電層表面 發明詳細說明： 本發明係利用在介電層之後以電漿方式處理，在接續形 成HSQ後可增加HSQ與其下介電層間之附著力，以下將以 積體電路元件的金屬層間介電層製作爲實施例，來說明本 3 ---^--------^ V裝---------訂---------^ - v\ - (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A.U見格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 4 3 91 8 4 ^ A/ _____B7________ 五、發明說明（3 ) 發明之改善HSQ/介電層界面剝離現象的方法， 第一實施例 首先’請參閱圖一，提供一已完成前段電路元件製作的 半導體基板10，在所述半導體基板10上，陸續形成一層金 屬導線結構20，其中所述金屬導線結構20爲鋁(A1)、鋁銅 合金(AlCu)或銅(Cu)之材質及其抗反射層(Anti-reflection layer ; ARC)[圖中未示]與阻障層(barrier layer)[圖中未示]， 經過微影蝕刻等步驟完成金屬導線結構20之製作。 接著，形成第一介電層30，其上述之第一介電層30可 爲爲電漿增強式化學氣相沈積法(Plasma Enhanced Chemical Vapor Deposition PECVD)所沈積之二氧化政(SiOx)，.其中 χ=2與小於2其中之一的値，其厚度係介於0.5KA到1.5KA 之間，其所形成之第一介電層30會隨順著金屬導線結構20 的輪廓沈積，可保護金屬導線結構20不會被水氣侵蝕。 接續進入本發明之重點，不同於習知技藝的是在此時加 入一額外的步驟，對第一介電層表面1〇〇使用含氮氣(Ν2) 之電漿進行處理，其電漿處理的時間係介於20秒到60秒 之間，上述之含氮氣的電漿處理，可在形成第一介電層30 後，於同一機臺中直接進行(in-situ treatment)或將沉積第一 介電層30與所述之電漿處理分開進行(ex-situ tmrment)，接 著，形成HSQ40於所述第一介電層30之上，係使用旋塗方 式(spin coating)开多成，增加金屬層間介電層之平坦度，如圖 一所示，其中所述之HSQ40的厚度係介於3KA到6 KA之 間，其最佳之厚度爲4 KA，接續步驟於習知技術相同於所 I---一-------〇 裝--------訂---------4}- {請先閱讀背面之注音心事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A-l規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 43 9184 A7 __B7_ 五、發明說明（斗） 述HSQ40上，先以含氮氣之電漿對HSQ40進行表面處理， 可使HSQ40表面粗糖化或氮化情況產生，而增加第二介電 層與HSQ40間之接觸表面積，接續，形成一層第二介電層 50，該第二介電層50的厚度係介於12KA到19KA之間， 其中最佳厚度爲1.5 KA，而上述之第二介電層50係使用電 漿增強式化學氣相沈積法(PECVD)沈積，其反應氣體係使用 四乙氧基矽烷(tetraethoxysilanes ; TEOS)，或使用次大氣壓 化學氣相沈積法（sub-atmospheric chemical vapor deposition ; SACVD )形成後，再經化學機械硏磨(chemical mechanical polishing; CMP)將使上述之金屬層間之介電層結 構形成最佳之平坦狀況。 第二實施例 首先，依然參閱圖一所示，提供一已完成前段電路元件 製作的半導體基板10，在所述半導體基板10上，陸續形成 一層金屬導線結構20，其中所述之半導體基板10與金屬導 線結構20之結構與材質與第一實施例中所述相同。 接著，形成第一介電層30，其上述之第一介電層30可 爲氮氧化砂(SiUcon-Oxy Nitride ; SiOxNy)，其中之X及y値 隨順反應條件不同而有所差異，其厚度係介於0.5KA到 1.5KA之間，其所形成之第一介電層30會隨順著金屬導線 結構20的輪廓沈積，可保護金屬導線結構20不會被水氣 侵蝕，上述之第一介電層30係使用電槳增強式化學氣相沈 積法(Plasma Enhanced Chemical Vapor Deposition ; PECVD) 沈積而成，其反應氣體爲砂烷(silane ; SH4)、一氧化氮(N20) ---1-------'裝--------訂---------^ (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 43 91 8 430-First dielectric layer 40-HSQ 50-Second dielectric layer 100-First dielectric layer surface Detailed description of the invention: The present invention uses a plasma treatment after the dielectric layer. To increase the adhesion between the HSQ and the underlying dielectric layer, the following will take the fabrication of the interlayer dielectric layer of the integrated circuit element as an example to illustrate this 3 --- ^ -------- ^ V device- ------- Order --------- ^-v \-(Please read the precautions on the back before filling in this page) The paper size is applicable to the Chinese National Standard (CNS) AU see the grid (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 3 91 8 4 ^ A / _____B7________ V. Description of the Invention (3) Invention method to improve the peeling phenomenon of the HSQ / dielectric layer interface. 'Please refer to FIG. 1, providing a semiconductor substrate 10 on which the production of the previous-stage circuit elements has been completed. On the semiconductor substrate 10, a layer of metal wire structure 20 is successively formed, wherein the metal wire structure 20 is aluminum (A1), aluminum copper The material of the alloy (AlCu) or copper (Cu) and its anti-reflection layer (ARC) [not shown] and the barrier layer (ba rrier layer) [not shown in the figure], and the fabrication of the metal wire structure 20 is completed through steps such as lithographic etching. Next, a first dielectric layer 30 is formed, and the above-mentioned first dielectric layer 30 may be a SiOx deposited by Plasma Enhanced Chemical Vapor Deposition PECVD. Where χ = 2 and 小于 less than 2, the thickness of which is between 0.5KA and 1.5KA, and the first dielectric layer 30 formed thereon will be deposited along the contour of the metal wire structure 20 to protect the metal The lead structure 20 is not eroded by water vapor. Continuing into the focus of the present invention, what is different from the conventional art is to add an extra step at this time to treat the surface of the first dielectric layer 100 with a plasma containing nitrogen (N2). The time is between 20 seconds and 60 seconds. The above-mentioned nitrogen-containing plasma treatment can be performed directly or in-situ on the same machine after the first dielectric layer 30 is formed. The electrical layer 30 is separated from the plasma treatment (ex-situ tmrment), and then, HSQ40 is formed on the first dielectric layer 30, which is spin-coated to increase the metal content and increase the metal. The flatness of the interlayer dielectric layer is shown in Figure 1. The thickness of the HSQ40 is between 3KA and 6KA, and the optimal thickness is 4KA. The subsequent steps are the same as those in conventional techniques. --- One ------- 〇 Loading -------- Order --------- 4}-{Please read the phonetic notes on the back before filling this page) This paper Standards are applicable to Chinese National Standard (CNS) Al specifications (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 43 9184 A7 __B7_ V. Description of Invention (Battle) On the HSQ40, the surface treatment of the HSQ40 with a nitrogen-containing plasma is performed first, which can cause rough saccharification or nitriding of the surface of the HSQ40, and increase the contact surface area between the second dielectric layer and the HSQ40. The thickness of the second dielectric layer 50 is between 12KA and 19KA, and the optimal thickness is 1.5KA. The above-mentioned second dielectric layer 50 is a plasma enhanced chemical vapor deposition method. (PECVD) deposition. The reaction gas system is formed using tetraethoxysilanes (TEOS), or using sub-atmospheric chemical vapor deposition (SACVD), and then subjected to chemical mechanical honing (SACVD). chemical mechanical polishing (CMP) will make the above-mentioned dielectric layer structure between the metal layers to form the best flat condition. Second Embodiment First, still referring to FIG. 1, a semiconductor substrate 10 having completed the fabrication of front-end circuit elements is provided. On the semiconductor substrate 10, a layer of metal wire structure 20 is successively formed. The semiconductor substrate 10 and The structure and material of the metal wire structure 20 are the same as those described in the first embodiment. Next, a first dielectric layer 30 is formed. The above-mentioned first dielectric layer 30 may be a silicon oxynitride (SiUcon-Oxy Nitride; SiOxNy), where X and y 値 vary with different reaction conditions, and their thicknesses are different. It is between 0.5KA and 1.5KA. The first dielectric layer 30 formed thereon will be deposited along the contour of the metal wire structure 20 to protect the metal wire structure 20 from being attacked by water vapor. The electric layer 30 is deposited by using the Plasma Enhanced Chemical Vapor Deposition (PECVD) method. Its reaction gases are silane (SH4) and nitric oxide (N20) --- 1- ------ 'Installation -------- Order --------- ^ (Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 size (210 X 297 mm) 43 91 8 4
五、發明說明（^ ) 與氮氣(N2)，但所述第一介電層30也可使用高密度電漿化 學氣相沈積(High density plasma chemical vapor deposition ; HDP CVD)形成含氟氧化矽(Fluorinated oxide ; FSG)，其反 應氣體爲四乙氧基砍院(tetraethoxysilanes ; TEOS)及四氟化 碳(CF4)或使用高密度電漿化學氣相沈積(HDP CVD)形成未 摻雜二氧化砍(Undoped silicon glass ; USG)，其反應氣體爲 矽烷。 接續進入本發明之重點，不同於習知技藝的是在此時加 入一額外的步驟，第一介電層表面100使用含氮氣(N2)之電 漿進行處理，其電漿處理的時間係介於20秒到60秒之間’ 可使第一介電層表面粗糙化，而增加第一介電層第一介電 層50與HSQ40間之接觸表面積，接續，形成HSQ40於所 述第一介電層30之上，係使用旋塗方式(spin coating)形成， 增加金屬層間介電層之平坦度，如圖一所示，其中所述之 HSQ40的厚度係介於3KA到6KA之間，其最佳之厚度爲4 KA，接續步驟於習知技術相同於所述HSQ40上，先以含氮 氣之電漿對HSQ40進行表面處理後，形成一層第二介電層 50，該第二介電層50的厚度係介於12KA到19KA之間， 其中最佳厚度爲15KA，‘而上述之第二介電層50係使用電 漿增強式化學氣相沈積法(PECVD)沈積，其反應氣體係使用 四乙氧基砂焼(tetraethoxysilanes ; TE0S)，或使用次大氣壓 化學氣相沈積法（sub-atmospheric chemical vapor deposition ; SACVD )形成後，再經化學機械硏磨(CMP)將使 上述之金屬層間之介電層結構形成最佳之平坦狀況。 (請先閱讀背面之注意事項再填寫本頁) Φ裝.—V. Description of the Invention (^) and nitrogen (N2), but the first dielectric layer 30 may also be formed using high density plasma chemical vapor deposition (HDP CVD) to form fluorine-containing silicon oxide ( Fluorinated oxide (FSG), the reaction gases of which are tetraethoxysilanes (TEOS) and carbon tetrafluoride (CF4) or use high-density plasma chemical vapor deposition (HDP CVD) to form undoped dioxide (Undoped silicon glass; USG), whose reaction gas is silane. Continuing into the focus of the present invention, unlike the conventional technique, an additional step is added at this time. The surface of the first dielectric layer 100 is treated with a plasma containing nitrogen (N2), and the plasma treatment time is medium. Between 20 seconds and 60 seconds, the surface of the first dielectric layer can be roughened, and the contact surface area between the first dielectric layer 50 and the HSQ40 can be increased, and then the HSQ40 can be formed in the first dielectric layer. The electrical layer 30 is formed using a spin coating method to increase the flatness of the metal interlayer dielectric layer, as shown in FIG. 1, where the thickness of the HSQ40 is between 3KA and 6KA. The optimal thickness is 4 KA. The subsequent steps are the same as those of the HSQ40 in the conventional technique. After the surface treatment of the HSQ40 with a nitrogen-containing plasma, a second dielectric layer 50 is formed. The thickness of 50 is between 12KA and 19KA, and the optimal thickness is 15KA, and the second dielectric layer 50 is deposited by plasma enhanced chemical vapor deposition (PECVD), and the reaction gas system is used. Tetraethoxysilanes (TE0S), or use sub-atmospheric pressure Chemical vapor deposition method (sub-atmospheric chemical vapor deposition; SACVD) after forming, and then by a chemical mechanical grinding WH (CMP) structure will dielectric layer between the metal layer is formed of the above-described optimum condition of the flat. (Please read the notes on the back before filling this page) Φ 装 .—
I I I I 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用+ 0國家標準〈CNS) A.1規恪（210 X 297公t ) 經濟部智慧財產局員工消費合作钍印製 '' 4 3 91, 8 4 " A7 ____—_B7 __ 五、發明說明（t) 利用本發明可使第一介電層與HSQ層間之拉力增加10 %至20%之間’也就是說第一介電層與HSq層間之附著力 增加。從表一中可知，分別對習知技術中，無額外使用含 氮氣之電漿處理第一介電層之表面與利用本發明所形成之 基板，分別做拉力(stud pull)、熱循環(thermal cycle : T/C)與 熱應力(thermal stress ; T/S)等測試，可知本發明可有效改善 習知技藝中HSQ/介電層界面剝離現象的問題。在下表中 所示之分數中，其中分子代表其測試結果中的失敗基板數 目，而分母代表其測試之總數目，且失敗基板之認定爲基 板角落處沈積有第一介電層與HSQ之結構，因剝離現象最 先發生於基板角落處。 表一 習知技術一 習知技術二 本發明| PEOX 0.5 KA+HSQ PEOX 0.3 KA+HSQ PEOX 0.5 KA+N2 1 min +N2+PETEOS +n2+peteos +HSQ+N2+PETEOS Stud pull (max. 190 〜225 Newton 190〜225 Newton 220〜250 Newton Strength) T/S 200 cys 3/24(失敗/總數） 2八8(失敗/總數） 0/22(失敗/總數） T/C 500 cys 6 /32 (失敗/總數） 2/32(失敗/總數） 0/32(失敗/總數） PC3 0 /32佚敗/總數） 1/32(失敗/總數） 0/32(失敗/總數） 以上所述係利用較佳實施例詳細說明本發明，而非限 制本發明的範圍，而且熟知此技藝的人士亦能明瞭，適當 本紙張尺度適用中國國家標準（CNS)A-l規格（2丨0 X 297公釐） .I-----------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 43 91 84 A7 _B7_^_ 五、發明說明（） 而作些微的改變與調整，仍將不失本發明之要義所在，亦 不脫離本發明之精神和範圍，故都應視爲本發明的進一步 實施狀況。謹請貴審查委員明鑑，並祈惠准，是所至禱。 {請先閲讀背面之注意事項再填寫本頁) 裝 訂---------^ 經濟部智慧財產局員工消費合作钍印製 本紙張尺度適用中國國家標準（CNS)A.l規格<210 X 297公釐）IIII Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. This paper is applicable to the standard + 0 National Standard (CNS) A.1. , 8 4 " A7 ______B7 __ 5. Explanation of the invention (t) The invention can increase the tension between the first dielectric layer and the HSQ layer by between 10% and 20%, that is, the first dielectric layer and the Increased adhesion between HSq layers. As can be seen from Table 1, in the conventional technology, the surface of the first dielectric layer and the substrate formed by using the present invention are not treated with an additional nitrogen-containing plasma, respectively, and are subjected to stud pull and thermal cycling. Cycle: T / C) and thermal stress (T / S) tests show that the present invention can effectively improve the problem of HSQ / dielectric layer interface peeling in conventional techniques. In the scores shown in the table below, where the numerator represents the number of failed substrates in its test results, and the denominator represents the total number of its tests, and the failure substrate is identified as the structure with the first dielectric layer and HSQ deposited at the corner of the substrate Due to the peeling phenomenon, it first occurred at the corner of the substrate. Table 1 Known technology 1 Known technology 2 The present invention | PEOX 0.5 KA + HSQ PEOX 0.3 KA + HSQ PEOX 0.5 KA + N2 1 min + N2 + PETEOS + n2 + peteos + HSQ + N2 + PETEOS Stud pull (max. 190 ～ 225 Newton 190 ～ 225 Newton 220 ～ 250 Newton Strength) T / S 200 cys 3/24 (failed / total) 2 8 8 (failed / total) 0/22 (failed / total) T / C 500 cys 6/32 (Fail / Total) 2/32 (Fail / Total) 0/32 (Fail / Total) PC3 0/32 Failure / Total) 1/32 (Fail / Total) 0/32 (Fail / Total) The preferred embodiments are used to describe the present invention in detail, but not to limit the scope of the present invention, and those skilled in the art will also understand that the appropriate paper size applies the Chinese National Standard (CNS) Al specification (2 丨 0 X 297 mm) .I ----------- install -------- order --------- line (please read the precautions on the back before filling this page) 43 91 84 A7 _B7 _ ^ _ V. Explanation of the invention (5) Minor changes and adjustments will still not lose the essence of the present invention, nor depart from the spirit and scope of the present invention, so they should be regarded as the further implementation status of the present invention. I would like to ask your reviewers to make a clear reference and pray for your sincere prayer. {Please read the precautions on the back before filling this page) Binding --------- ^ Consumption cooperation between employees of the Intellectual Property Bureau of the Ministry of Economic Affairs X 297 mm)