TW515006B - Method for removing moistured part of FSG layer after polishing treatment - Google Patents

Abstract

Usually, the FSG layer used for producing a low-k IMD, after a planarization polishing treatment, will generate HF due to moistured portion of the surface layer of the FSG, thereby causing corrosion and bubbling on the metal wire and affecting the performance of the component. Presently, even though some manufacturers propose an Ar/O2 bombardment treatment to remove the abovementioned moistured part, this treatment is liable to damage the component and cause particle contaminations. Thus, the present invention provides an improved method for removing the moistured part of a FSG layer after a planarization polishing treatment, which uses a NF3 or CnF2n+2 (e.g. CF4 and C2F6, etc.) plasma etching process of an ordinary cleaning deposition reaction chamber to remove the moistured part of the FSG layer. Thus, the invented moderate treatment procedure can reduce damage on the component and particle pollution.

Description

515006 V. Description of the invention (1) '' ------- [Field of invention] The present invention relates to the manufacture of semiconductor integrated circuits, and in particular, there are two or more kinds of low-density silicon fluoride (FSG) manufacturing An improved method for the dielectric interlayer dielectric layer (〃10w ~ k IMD), which uses a plasma etching process to remove the moist parts generated after the flattening and grinding process of the push-second glass breakage layer to improve the product. Component reliability. [Scientifically speaking, semiconductors are integrated on a small area of a specific circuit. In order to make use of the process (metall iza hunting assistant contact windows (between con wires, or multiple reduced-size wire technologies), the RC delay is still emerging, and many dielectric material layers are used to create layers. er-me ta 1 Ming】

The production of a circuit is an extremely complicated process. The various electronic components and circuits required for the purpose are reduced in size. Among them, each component on the substrate must be effectively isolated.

The interconnect is used to perform the desired function of electrical connection. This process is generally called metal 々ti on). In addition to making various layers of wire patterns, and tact / via) structure, it is used as the component contact area. The channel connecting with the conducting wire. In recent years, with the further development, not only the application of copper materials with higher conductivity is used, but in order to effectively reduce the parasitic capacitance between the wires and the element process, they have gradually switched to using low dielectric constants instead of general dielectric materials as metal interlayers. ^ Dielectric (IMD) 〇 Recently, fluorine-doped silicate glass (FSG) formed by the high-density electrochemical polymer chemical vapor deposition (HDPCVD) process has become an important material for the fabrication of low-k dielectric interlayer dielectric layers. First, can be used alone or with undoped

515006 V. Description of the invention (2) Shixi Glass (USG) coexists but has a large amount to reduce the intermediary. The chemical property for surface flattening =, but the surface layer of the fluorine-doped dream glass layer is partially ground = ^ d ^ bMHF} ^ ^ ^ ^ ^ (〇〇r: 〇sr〇f and bub 2g) and affect the properties of the element. At present, although Applied Materials proposes an improved process with Ar / min, it still has the following problems: / In addition to the above-mentioned problems of Wenhu Department. Those who are prone to buckle and particle contamination of children: Refer to Figures IA and 1D, and explain in detail the process and the problems it generates. First, as shown in the figure;;!件 ίΐίΓ is a piece of wafer, for example, which can be formed on top of it. However, in order to simplify the drawing, only two ί are shown here. A plurality of metal wires η are formed on the substrate 10, for example? The ordering belongs to the first layer; the second layer is then lithographically imaged and the last name is engraved: Yi, Yi, one of them, on the surface of the substrate 10 and the metal wire u, i: a low f dielectric constant dielectric material The layer 12 is, for example, a fluorine-doped silica glass layer 12 formed by a high-density electrodeposition process. Due to the influence of the first metal wire 11, the surface structure of the fluorine-doped silica glass layer is inferior. Next, please refer to Figure 丨 B to perform a mechanical polishing process on the fluorine-doped silica glass layer 2 to form a flat surface structure. In agriculture, beauty grinding = the characteristics of the material itself, the surface portion of the above-mentioned fluorine-doped silica glass layer 12 will be dampened by the infiltration of the grinding fluid during the process, as shown in the figure 12a in the figure. Etching substances such as hydrofluoric acid (HF), causing metals

Page 5 V. Description of the invention (3) Recording and starting of the wire, by flattening the grinding process: heavily affect the reliability of the component and other properties. Since the 1 £ table > π ^ is unavoidable, it will also inevitably cause the fluorine-doped silica glass layer to be able to improve the electrical properties of the 7L circuit. Three changes were shown in the tflc chart. The manufacturer Appiied Materiais mentioned -Α " 〇2 to remove the above :: Learn: mechanical grinding process, and then in-si tu) # 理 士 ^ rust and blister. After that, the in-situ (12 surface: product; chemical: J :: tide portion 12a fluorine-doped silica glass layer T was dampened or it was modified by the second αγ / 〇; ΓΛΪ but also caused several new problems. 'Since Ar / 〇2 splash treatment is more than A. Kawasaki Kaishu έShishi from 4 ## is the surface treatment method of J, it is often easy to make, A r / 0 ice bran + brother 1 C and 1 D It is indicated by the number 13. In addition, the dielectric layer produced by A and A affects its properties. Therefore, A has made you ^ ancestral and easy to use. It is necessary to use fluorite. The application of the glass dielectric layer technology should seek to improve the above problems. [Summary of the Invention] In view of this, the present invention has a small number of improved metal wire manufacturing processes i :: The purpose is to provide a kind of integrated circuit to reduce the wire Inter-parasitic capacitance 3 Use low-dielectric constant fluorine-doped shattered glass' gas stone Xi glass as a metal layer-a kind of low dielectric constant doped 515006 V. Description of the invention (4) Shi Xi glass layer was processed into metal wires by grinding From the beginning of the recording, the part of the present invention does not produce fluorinated acid, which makes another aspect of the present invention. Gen # Γ 卜 2 is used for a low-dielectric-constant blending method to remove the doped gas; an improved process for the layer, which can use relatively low-temperature element damage and particle contamination; the wet part of the grinding process is used to reduce After the above and hair fairy treatment is mixed with tired stone into θ μ 1, 1, 'Ben Maoming proposed an improved method to remove the grinding of the multi-sharp y wen tide part, the violent Ar / 02 splash treatment, and __ eight + Use # 乂 to stimulate the MD ^ Γ f (Η ΓΤ7) to deeply deposit the reaction tank body, and to suppress the plasma layer = CF4m2F6, etc. = the damp part of the glass layer, and use this kind of gentler to reduce the y The problem of tl pieces being damaged and particle pollution. The present invention proposes a method for removing the wetted part of the fluorite-doped glass layer after the grinding process, which is suitable for a low dielectric constant metal layer including the following steps: providing-semiconductor substrate, eight A plurality of metal wires are formed on the surface; formation-low-dielectric constant ventilation = glass layer 'covers the above metal wires and the surface of the semiconductor substrate; the flat "surface structure' of which the flat aerated stone glass: surface grinding Deal with and get wet NF34CF: C2F6, etc.) Plasma etching procedure to remove fluorite-doped n2: 40 minutes; and forming a oxidized broken cover layer to cover the treated fluoro-doped glass layer ^ A metal interlayer dielectric layer is formed. Furthermore, the metal wire may be a metal layer or copper

(CU) metal layer, μ, +, and M high-density plasma and fluorine-doped silica glass layer with ^ phase = number of suspensions are based on an oxygen… layer; procedure, or Enhanced chemical vapor deposition (PECVD). In addition, the upper chemical vapor deposition (HDPCVD) program is used to remove the two I's S1 tU from the HDPCVD program to remove Ux-Slt: f. The fossil evening cover layer needs to be placed in another independent reaction tank. [Simplified description of the figure] In order to make the above and other objects, features, and advantages of the present invention more obvious and understandable, 'a preferred embodiment is given below, It is explained in detail with the accompanying drawings' as follows: Figures 1A to 1D are a series of cross-sectional views showing the conventional manufacturing process of using a fluorine-doped silica glass to make a metal interlayer dielectric layer, which is expressed in Ar / 〇2 The sputtering process removes the portion of the dielectric layer that is wetted by the polishing process; and Figures 2A to 2D are a series of cross-sectional views' for showing the manufacturing process according to a preferred embodiment of the improved method of the present invention to remove the polishing Moisture of the fluorine-doped silica glass layer after treatment. [Preferred Embodiment] Now referring to Figs. 2A to 2D, a preferred embodiment of the improved method according to the present invention will be described. First, as shown in FIG. 2A, a semiconductor is provided.

Page 8 515006 V. Description of the invention (6) The substrate 20 'is, for example, a silicon wafer (si 1 icon wafer), and any desired semiconductor element can be formed on it. Here again, in order to simplify the drawings, only The base 20 of the flat iE ′ is shown. A plurality of metal wires 21 are formed on the semiconductor substrate 20, for example, an aluminum metal layer or a copper metal layer is deposited first, and then its pattern is defined by a U & G imaging and etching procedure. A person 'covers a layer of low-k dielectric material 22 on the surface of the semiconductor substrate 20 and each metal wire 21, for example, a high-density plasma chemical vapor deposition (HDPCVD) process is used to form a fluorine-doped silicon glass (FSG) The layer 22 has a thickness of, for example, between 7000 angstroms and 20,000 angstroms. As shown in Fig. 丨 A ', the fluorine-doped silicon # glass layer 22 has a fluctuating surface structure due to the influence of the previously formed metal wires 2 丨. Next, referring to FIG. 2B, a chemical mechanical polishing (CMP) process is performed on the fluorine-doped silica glass layer 22 to form a flat surface structure. Wherein 'based on the characteristics of the material, the surface portion of the above-mentioned fluorine-doped silica glass layer 22 will be moisturized due to the infiltration of the grinding fluid during the grinding process. The area shown by reference numeral 22a in the figure will be removed if it is not removed. The reaction generates hydrogen etched materials such as hydrogen acid, which causes problems such as rusting and blistering of metal wires, which seriously affects the reliability of product components. As mentioned above, the Ar / 〇 splash treatment method proposed by the manufacturer Applied Materials can effectively remove the wetted part 2 2 a, but it is also 2❶ because its processing conditions are more intense and it is easy to cause damage to the component structure and Problems such as particle contamination. Therefore, it is necessary to replace it with other milder handling methods. As a result of research by the inventors, it has been found that ML or (: Λη + 2 (such as eh and ^^, etc.) X /

515006

V. Description of the invention (7) The TC removes the wetted part of the above-mentioned fluorite-doped glass layer 22 (as shown in Figure 2C), which can not only avoid gas rust and blistering caused by acid, but also plasma treatment. The program is gentler than the leather bucket, and it can reduce the problem of damage to components and particle pollution. Who should pay attention to the above NF3 or dagger? 2 ... Plasma etching process. Depending on the deposition method of the silicon oxide cap layer, the in-situ (丨 丨 忉) or ex-situ (eX-Sltu) processing method is selected to remove the fluorine-doped silicon glass layer. Moisture part 22a: If it is used to remove the oxidized stone seedling layer formed by the PECVD process, it can be performed in the same reaction tank in which the oxidation system cap layer is deposited (in: situ); if it is used to remove the HDPCVD process, The silicon oxide cap layer can be implemented in another independent reaction tank (e X-situ). In addition, the above CnF2n + 2 may be a clean gas of a PECVD deposition reaction tank, or a #etch gas of a last name groove. And at this moment, the tank can be hung on the same platform as the above [jDpcvd or PECVD deposition reaction tank, or it can be separated on different platforms / ends. See the production machine deployment considerations, which is quite flexible. Thereafter, "as shown in Fig. 2D", a silicon monoxide cap layer 24 is deposited on the surface of the fluorine-doped silica glass layer 22 from which the moisture-receiving portion 22a is removed to further protect the fluorine-doped silica glass layer 22 from moisture or damage. For example, the silicon oxide capping layer 24 is formed by using an electropolymerization enhanced chemical vapor deposition (PECVD) process or a high-density plasma chemical vapor deposition (HDPCVD) process. The thickness of the silicon oxide capping layer 24 is, for example, 100 angstroms. And between 2 0 0 0 Angstroms. At this point, the fluorine-doped glass layer 22 and the silicon oxide cap layer 24 together form a metal interlayer dielectric layer. Compared with the conventional technology, the improved process of the present invention is the same as the process proposed by Applied Materials, which can damp the fluorine-doped silica glass layer.

Page 10 515006 V. Partial removal of the description of the invention (8) 'to avoid the generation of hydrofluoric acid and cause the metal wire to remain and bubbles. And because the present invention uses a milder NL or Cj2 to replace the plasma etching process Known "% splashing treatment", so it has the advantages of reducing component damage and particle contamination, and can further improve the reliability of product components. Cleanliness or changes in equipment strips. Although, it can be used as a supplement, and it is currently used to react to the gas path and a reaction tank. The present invention will not increase the scope of the present invention. The scope should be adjusted according to the pipeline components of the reaction tank equipment used in the future. Or, you can choose a technology that can be mixed with students and have better familiarized with this technology. The patented NF3 or (; the main body is similar, and its application, and it is easy to choose the real estate cost in another independent. Artists, the steps defined in the motion and retouching circle do not need to add new rows, and can be performed in the vertical reaction tank in which the fluorine-doped silica glass layer is actually deposited. Instead of the existing The combination of process technology can be said to be extremely practical. As shown above, it is not intended to not depart from the spirit of the present invention ′ so the protector of the present invention shall prevail.

Claims (1)

515006 6. Scope of patent application1. A method for removing the mo 1 stured part of the fluorine-doped silica glass (FSG) layer after the grinding process, which is suitable for the production of low-k IMD. The method comprises the following steps: providing a semiconductor substrate with a plurality of metal wires formed on the surface; forming a low-dielectric constant fluorine-doped silica glass layer covering the metal wires and the surface of the semiconductor substrate; the fluorine-doped silica glass layer A chemical mechanical polishing process is performed to pass to a flat surface structure 'wherein the flat fluorite-doped glass layer has a surface layer due to the above-mentioned polishing process, and the wet part; < An NFS electro-etching process is performed to remove the wetted portion of the fluorine-doped silicon slope soil layer; and a silicon oxide cap layer is formed on the surface of the fluorine-doped silicon glass layer to jointly form a metal layer Dielectric layer. Shirt 2 · As described in item 1 of the scope of the patent application, a method for removing the wet portion of the doped silica glass layer after grinding treatment, wherein the material of the metal wires is metal (A1) or copper (Cu). 1-3 · A method of removing moisture from the doped layer after grinding treatment as described in item 1 of the Shenjing patent scope, wherein the low dielectric constant is doped for two days by using a high-density plasma chemical vapor deposition ( HDpcVD) Formed by deposition. ） 狂 斤 户 # As described in item 1 of the scope of the patent application, a method of removing the wetted part after the grinding process is used ... The oxidized stone cap layer is deposited using the-° Denso Chemical Vapor Deposition (HDPCVD) program. Forming. • A method for removing 515006 after grinding treatment as described in item 4 of the scope of the patent application. 6. Method of applying the patent scope of the fluorosilicon f glass layer to the damp part, wherein the nf3 plasma etching process is performed in another independent reaction tank. of. A method for removing the doped part after the grinding process described by the “Li Jianyi” member, wherein the silicon oxide cap layer is deposited by using the electro-water enhanced chemical vapor deposition (PECVD) process. A method for removing the Jit part of the ground layer described in the above item, wherein the HuaN 3? 3 electric poly surname engraving process' is performed in the same reaction tank of Shen and edge lice silicon cover. 8.-After removing the grinding treatment The fluorine-doped silicon glass layer includes a plurality of steps as follows: κ 1MD) A semiconductor substrate is provided on the surface of which a plurality of metal wires are formed. Formation-low-dielectric constant fluorite-doped glass; On the surface of the semiconductor substrate; θ coating 1 performs a chemical treatment on the fluorine-doped silica glass layer on these metals to obtain-a flat surface structure grinding process procedure. The layer is subjected to the above-mentioned grinding treatment * yes-damp 3 #fluoro 石 夕 玻璃The layer surface is subjected to a CnF2n + 2 plasma etching process to the wetted part of the glass layer; and the fluorine-doped silica glass is removed to form a silicon oxide cap layer and the fluorine-doped layer is formed to form a metal interlayer dielectric layer. On the surface of the layer , Common 9 · Rushen Method for moisture-retaining part of a fluorosilicone glass layer according to item 8 of the patent scope, wherein / does not include aluminum (A1) metal or copper (Cu) metal after grinding treatment. Μ2. The material of the wire is 515006 6. Application Patent scope I 0 · A method for removing the damp part of a fluorite-doped glass layer after grinding treatment as described in item 8 of the scope of the patent application, wherein the low-dielectric constant fluorite-doped glass layer uses a high-density electrode It is formed by the slurry chemical vapor deposition (HDPCVD) process. II. A method for removing the wetted portion of the fluorine-doped silica glass layer after the grinding treatment as described in item 8 of the patent application scope, wherein the silicon oxide capping layer uses a high Formed by the density plasma chemical vapor deposition (HDpcvD) program. 1 2 · A method for removing a wetted part of a doped stone glass layer after grinding treatment as described in item 11 of the patent application scope, wherein the CnF2n + 2 The plasma etching process is performed in another independent reaction tank. 1 3 · A method for removing a wetted portion of a fluorine-doped silica glass layer after abrasion treatment as described in item 8 of the scope of the patent application, wherein the silicon oxide cap layer It is formed by a plasma enhanced chemical vapor deposition (p EC v D) procedure. 1 4 · A method for removing the wet part of the glass layer doped with fluorite after grinding treatment as described in item 3 of the patent application scope In which, the CnF2n + 2 plasma etching process is performed in the same reaction tank of Shen Jibian gasification stone cover. Page 14