TW439153B - Method for performing an erasing process by using the gate/source and substrate/channel of the floating gate memory device - Google Patents

Abstract

There is provided a method for performing an erasing process by using the gate/source and substrate/channel of the floating gate memory device, wherein the floating gate memory device is formed on a substrate having a well region, and the gate/source and channel are located in the well region. The method comprises the steps of: erasing the gate/source by providing a voltage gradually increasing to 4.3V to the source of the floating gate memory device, and simultaneously providing a voltage gradually decreasing to -10V to the control electrode of the floating gate memory device; then grounding the source of the floating gate memory device; providing a 5V voltage to the well region having the gate/source; next, erasing the source by grounding the well region having the control electrode and the gate/source, and simultaneously providing a voltage gradually increasing to 10V to the source of the floating gate memory device; and erasing the channel by providing a -10V voltage to the control gate, providing a 5V voltage to the well region having the gate/source, and simultaneously grounding the source.

Description

V. Description of the invention (1) The gate / this is an improvement of the patent No. 86112042 "the method of erasing the gate / source, substrate / channel of the floating interrogation memory device". π 罝 沔 Polar: bottom / zhi | mother # The method disclosed in the case of (floating gate / memory gate /: pole base / channel for erasing, mainly including Ming. 眚 ：: t: fla Figure, which shows a schematic diagram based on the 5 'removal step of the floating idler memory unit, the floating gate memory unit 5- general removal and programmable read-only memory (EEPROMs), which includes a semiconductor area 50 and-stacked Gate ㈤. The above semiconductor region 50 is generally a p-type substrate, or is a p-type substrate with a? -Type well region and isolated by an N-type well region (if this structure is described below, the substrate voltage VP- Sub refers to the voltage of the p-type well region. In addition, double-diffused n-type source region 52 and # -type drain region 54 are implanted at predetermined positions on the substrate. A channel region 56 is formed between them. Among them, the double-diffused n-type source region 52 includes a doped implanted region 55 with a relatively deep diffusion depth but belonging to a lightly doped, and a n-doped implanted region with a shallow diffusion depth but belongs to a heavily doped Region 53 ° Secondly, the ink stack gate 60 is formed between the source region 52 and the drain region 54 of the semiconductor substrate 5Q. On the channel region 56, and the above-mentioned stacked gate 60 is a tunneling oxide layer 62, a floating gate 64, an inter-gate dielectric layer 66, and a control gate 68 'tunneling oxide layer 62 in this order. It is located between the surface of the tomb bottom 50 and the floating gate 64. Its thickness is relatively thin. The floating gate 6 $ is mainly composed of a polycrystalline chopped conductive layer. The control gate 68 is located on the floating gate 64. Up 'and separated by an insulating layer 6 S, such as a dream oxide layer / nitrogen

Page 4 5. Description of the invention (2) '--- Siliconized layer / Silicon oxide layer (ΟΝΟ). In addition, 'terminal 61 is used to provide the source voltage Vs and the source region 52, terminal ⑸ is used to provide the gate voltage Vg to control the gate 68', terminal 65 is used to provide the drain voltage VDT drain region 54, and terminal 67 is provided through A p + -type doped region provides a substrate voltage VP-Sub to the substrate 50. 'Tu Ming see Figure 1b' shows a stylized step implemented according to floating gate memory unit 5 of Figure 1a_, and provides different voltages to source region one, drain region 54, stacked gate Waveform timing diagrams of 60 and substrate 50. When the floating gate memory cell 5 is programmed, a higher voltage is applied to the control gate 68 and the drain region 54 than the source region 52. For example, _ by The terminal 63 provides a relatively high gate voltage pulse Vg = 10.5V to the control gate 68, and the terminal 65 provides a relatively high-drain voltage pulse Vd = 6v to the drain region 54, and the terminal 6 1 provides Ground to provide a relatively low source voltage Vs = 0v to the source region 5 2 'terminal 6 7-Generally, it is grounded to provide a relatively low, bottom voltage VP_Sub = 0v to the substrate 5 〇 . As mentioned earlier, the high electric field formed by the high gate voltage pulse VG = 10.5V will cause the ambivalent hot electrons to be generated in the channel region 56 close to the drain region 54 and further accelerate the hot electrons across the tunneling oxidation described above. The object layer 62 is injected to the floating gate 64. Because the floating gate 64 is surrounded by an insulating layer such as 62 and 66, after the hot electrons are injected into the floating gate 64, they will fall into it and cannot be separated. In the case where the floating gate 64 is stored, The threshold value ahres ^ mldj is increased by about 3 to ⑼. As a result, when the floating gate memory unit 5 is to read the shell material and the control gate 68 is pressurized to 5V, the channel is not turned on. Take the data as (1), that is, the above floating gate memory unit 5 has been

Page 5 r-139153 ___ V. Invention ^ (3) '' Stylized, as for the general stylized time, about sec shows that He Ming is also unavoidable. During the above stylized period, as shown in Figure 5a, when The memory unit 5 re-processed a predetermined number of times, such as 丨 〇, 〇〇〇, after approaching the a & ce red is more important than the catch phenomenon, so that the negative electricity and m-oxygen H62 ' ^ Substantially improved after wiping step. TA m — Please refer to Figure 1c, which shows an erase step performed according to the floating gate memory unit shown in Figure 丨 a, and provides different voltages to the source, drain, gate, and substrate. Waveform timing diagram. When erasing the memory unit 5, it is mainly divided into two stages, which are described below. Please refer to the first erasing stage e 1 in Figs. 1 d and 1 c. The period is about -5 to 100 msec, preferably 50 msec. It is a source erasing method, that is, the source is first The region 52 applies a higher voltage than the control gate 68, for example, a relatively higher source voltage pulse Vs = 5v is provided to the source region 52 through the terminal 61, and a relatively lower gate voltage vG = _1 is provided through the terminal 63. v to control the gate 68, and the terminal 67 is grounded to provide a base voltage Vp sub = 0 v to the base 50 ′. The drain voltage VD of the drain region 54 is brought to a floating state f (floating) by the terminal 65. In this way, a high electric field will be formed between the floating gate 64 and the source region 52 across the oxide layer 62, so that the negative charge trapped in the floating gate 64 (1) will be located opposite the source region 5 2 Gather, and then by

The Fowler-Nordheim (F-N) tunnel effect causes part of the negative charge (a) in the floating gate 64 to be extracted to the source region 52. In the same way, since a hole trapping pattern is induced between the source 5 2 and the tunneling oxide layer 62, a positive charge is trapped in the tunneling oxide layer 62, so it is added in a short time.

4 3 915 3 V. Description of the invention (4) The flow of hot electrons in the floating gate electrode 6 4 is accelerated, but with the continuous attraction of the holes trapped in the penetrating compound layer 6 2, more and more The negative charge is drawn out and trapped in the tunneling oxide layer 62, blocking the outflow of hot electrons and slowing down the erasing speed. However, during the second erasing stage E2 of this embodiment, the foregoing phenomenon will eliminate the holes trapped in the tunnel oxide layer 62, so more and more negative charges will not be attracted and trapped in the tunnel. The phenomenon of the oxide layer 62 is as described below. Please refer to the second erasing stage E2 in FIG. 1e and FIG. 1c. The period is about 5 ~ 100msec, preferably 50msec. It is a channel erasing method, that is, the substrate 5 is firstly used. -0 is applied to control the gate 68 to a high voltage, for example, a relatively high base voltage pulse Vp_Sub = 5V is provided to the base 50 through the terminal 67, and a relatively low gate voltage pulse% = 0v is provided to the terminal 63 to control Gate 6 8 ′ As for the drain voltage vD of the drain region 5 4 and the source voltage Vs of the source region 5 2, they are brought into a floating state by terminals 65 and 61 f (f ioating) ^ This is the floating gate 64 A high electric field across the tunnel oxide layer 62 will be formed between the channel region 56 and the negative electric charge (-) trapped in the floating gate 64 to collect toward the channel region 56 and further, by Fowler_Nórdheim (F_N ) Tunneling effect, the remaining negative charges (a) in the floating gate 64 are extracted to the channel area 56 ° ^ At the same time, the negative charges trapped in the tunnel oxide layer 62 during the programming period will also be caused by the above The high electric field formed between the floating gate 64 and the channel region 56 is sucked out, eliminating blocking hot electrons The phenomenon. In addition, in the first erasing stage E1., The positive charges (holes) trapped in the tunneling oxide layer 62 are also sucked into the float by the negative voltage (Vg = -10 volts) of the control gate 68.

Page 7 91 53 V. Description of the invention (5) Yu Ji 64, because Ye Yu—Hui Qisheng made more and more texts when he repeatedly performed the program erasing action. Phenomenon of tunneling oxide layer 62. However, the problem with this combination is that when the erasing action is performed, the initial erasing electric field across the tunneling oxide layer often forms an excessively high peak field, resulting in the generation rate of the charge trapping center of the oxide layer. xide trapping centers generatifl rate). At this time, as shown in Figure 1f, in the traditional erasing voltage form, the characteristic curve shown by the reference = pole current ID (erasing conductance value Gm) is the vertical coordinate, and the control gate voltage is the horizontal coordinate. , And compare the initial program / erase curve init of the memory unit and the program / erase cycle times more than 100,000 times. ^ Of = line 100k, you can find that the program / erase cycle times are more than 100,000 times. The time curve 1001 ^ shifts to the right, indicating the drain current 11) and the erase conductance value (^ at the program / erase cycle number of more than 100,000 times has tended to decay. &Amp; The purpose of the present invention is In order to improve the foregoing phenomenon, it provides a method of erasing with the gate / source and substrate / channel of the strict inter-electrode c-memory device, and using the method of gradually increasing and decreasing the voltage during the entire erasing cycle, provides: : The averaged tunneling electric field reduces ^ = of the oxide charge trapping center, so that the drain current ID and the erased conductance value Gro are not degraded when the program / erase cycle times are more than 100,000 times.

On page 8 of the gate, the 'floating gate memory device is formed on a substrate with a well area, and the source and channel are located in this well area.' This method includes the following steps: It gradually provides a voltage that gradually increases to 4 · 3V to the source of the idle memory device, and gradually provides the electricity reduced to -i ov. V. Description of the invention (6) J to control the floating gate memory device 记忆 ' After that, the source of the floating gate memory device is grounded, and then a voltage of 5V is provided to the area where the gate / source is located. Next, the source is erased, which controls the gate and the gate / source. The well area is grounded, while gradually increasing the voltage to 10v to the floating gate = the source of the device; secondly, the channel is erased, which provides a voltage of -ινν to the control gate and 5V to The gate / source is located in the well area, and the source is also grounded. Erase of Floating Gate Memory Device The following embodiment of the drift and stylization method of the present invention will be described with reference to the drawings. Brief description of the drawing 1 Figure la shows the patent No. 86 1 1 204Γ • Sectional view of the floating gate in the 7G 〇

Figure 1b is a timing diagram of waveforms of different voltages provided to the source region, drain region, gate, and substrate in the stylized steps performed in accordance with the floating gate memory cell of Figure 1a. Figure lc shows a waveform timing diagram of providing different voltages to the source region, the drain region, the gate, and the substrate during the erasing step performed by the floating gate memory cell according to the figure ia. Figure Id is a cross-sectional view showing the floating closed-pole memory unit of the magic a picture after erasing according to the erasing stage of the brother of the ic picture. FIG. Le is a cross-sectional view showing the floating gate memory cell in FIG. La after being erased in the second erasing stage. · Figure If shows that in the traditional erase voltage form, the reference drain current π (erased conductance Gm) is the vertical coordinate, and the control gate voltage is the horizontal coordinate.

3 915 3 V. Description of the invention (7) The characteristic curve diagram shown. Figures 2a and 2b show a floating gate memory list, one of the additional inventions.

Figures 3a and 3b are waveform timing diagrams of providing different voltages to the source region, drain, gate, well region, and substrate during the erasing step performed according to the floating inter-electrode elements of 2a and _. Fig. 3c is a characteristic curve diagram in which the reference current ID (erased conductance Gm) is the vertical coordinate and the control gate voltage coordinate in the erasing voltage form of this embodiment. Horizontal [with explanation]

5 ~ memory cell; 50'70 ~ semiconductor substrate; 52,72 ~ source region; 54 and pole region; 56'76 ~ channel region; 60,80 ~ stacked gate electrode; 62,82 with perforation layer; 64 '84 ~ floating gate; 66, 86 ~ inter-gate dielectric layer 68' 88 ~ control gate; 71, 73 ~ well area S, you! Please refer to FIG. 2a, which shows a schematic diagram of implementing the erasing step of the additional invention according to a floating gate memory unit. The floating gate memory unit is generally a flash memory unit with stacked gate 80, such as an electrically erasable Formable read-only memories (EEPROMs) are formed on a first type substrate 70. The first type substrate is generally a P-type substrate P-sub.

Secondly, the above-mentioned stacked gate 80 is formed on the channel region 76 between the source region 72 and the drain region 74 of the P-type substrate p-Sub, and the above-mentioned stacked inter-electrode 80 is sequentially a tunnel oxidation. The physical layer 82, a floating gate 84, an inter-gate dielectric layer 86, and a control gate 88, the tunneling oxide layer 8 2 is interposed between the p-type base

Page 10- · ν V. Description of the invention (8) '--- The surface between f p-sub and floating gate 84 is relatively thin and floating. The pole 84 is mainly composed of a polycrystalline broken conductive layer. The control idler electrode 88 is located above the sweating electrode 84 and is isolated by an insulating layer 86, such as a silicon oxide layer / silicon nitride layer / silicon oxide layer (ONO). In addition, the terminal 81 is used to provide the source voltage and the source region, the terminal 83 is used to provide the gate electric dust% to control the gate 88, the terminal 85 is used to provide the drain voltage, and the drain region is 74 to the terminal 87 Provide substrate voltage Type base. In the erasing phase of this embodiment, the drain region 74 is floated. Free U'r, 'It's displayed-according to the erase step of the gate memory π according to the material of Figure 2a, and provide different voltages to the source region, drain ^, gate and substrate waveform timing diagram. When Erase erase) of the memory unit, which is mainly divided into three stages, which are described below. "The first erasing stage E1 is the gate / source erasing method, that is, the first 2 sources and the second area? It is mentioned that a relatively higher and gradually increasing relative to the control gate 88: "If measures are provided by the terminal 81, a voltage region 72 'that gradually increases to Vs = 4.3V is provided by the terminal 83 at the same time-relatively low Step by step, reduce the voltage to Vm to control the idler 88, and then ground the source voltage Vs of 5 ^ 72 to 'provide a 5V voltage to the terminal' to provide the substrate voltage vp_Sub = 5v to the substrate 70. Its dead weight = i has entered the second erasing stage of this embodiment. £ 2 to strengthen the application of the source erasing method, that is, to gradually increase the voltage directly to the source region 72, for example, via terminal 81 Provide a gradually increasing source voltage pulse ms = m to the source region 72, and terminal ⑽ ...

4391 53 V. Description of the invention (9) Grounding to provide the P-type substrate 70 and the control gate Ve, Vp_sub = 〇 \ ^ In this way, a crossing flow will be formed between the floating gate 8 4 and the source region 7 2 The high electric field of the oxide layer 82 causes the negative charges (-) trapped in the floating gate 84 to accumulate toward the source region 72, and further

The Fowler-Nordheim (F-N) tunnel effect causes part of the negative charge (a) in the floating gate 84 to be extracted to the source region 72. : Due to the hole trapping phenomenon between source 72 and tunneling oxide layer 82, which causes positive charges to trap in tunneling oxide layer 8 2 ', the outflow of hot electrons in floating gate 84 is accelerated in a short time, but With the continued attraction of the holes trapped in the tunneling oxide layer 8 2, more and more negative charges are drawn out and trapped in the j-passing oxide layer 82, blocking the outflow of hot electrons and slowing down the erasure. Speed, degree. However, during the third erasing phase | E3 of the present embodiment, the hole trapped in the tunneling oxide layer 62 will be eliminated during the third erasing phase of this embodiment, so more and more negative charges will not be attracted and trapped in The phenomenon of penetrating the oxide layer 62 is as follows. Please refer to Fig. 2a and the third erasing stage E3, which adopts the channel erasing method, that is, firstly applying a higher voltage to the p-type substrate 7 than the control gate 8 8 'for example, by borrowing The terminal 87 provides a relatively high voltage pulse ', sub = 5V to the P-type substrate 70, and the terminal provides a relatively low gate voltage pulse: _VG = -10V to the control gate 88, as for the source voltage of the source region 72 ^ Is grounded. In this way, a high electric field across the tunnel oxide layer 8 2 will be formed between the floating gate 84 and the channel region 76, so that the negative charges trapped in the floating gate 84 ((-) gather toward the channel region 76. , And then by

Page 12 4 3 91 5 3 V. Description of the invention (ίο)

The Fowler-Nordheim (F-N) tunnel effect causes the remaining negative charges (a) in the floating gate 84 to be extracted to the channel region 76. At the same time, 'the negative charge trapped in the tunneling oxide layer 82 during the stylization was also sucked out due to the high electric field formed between the floating gate 84 and the channel region 76, eliminating the phenomenon of blocking hot electron injection. In addition, in the first and second erasing stages E1 and E2, the positive charges (holes) trapped in the tunnel oxide layer 82 are also controlled in the third stage E3 by the negative voltage of the gate 88 (VG = -l OV) is sucked into the floating gate 84, so that when repeated program erasing operations are repeatedly performed, more and more negative charges are attracted and trapped in the tunnel oxide layer 82. I — Please refer to Figure 2b, which shows another schematic diagram of the erasing steps based on the floating gate memory unit. The floating gate memory unit is generally a flash memory unit with stacked gates 80, such as Electrically erasable and programmable read-only memory (EEPKOMs), this embodiment provides a three-layer well structure formed on a first type substrate 70 having a first plastic semiconductor region 7 I. Isolated by a second type semiconductor region 73. The above-mentioned first type substrate is generally a P-type substrate 'which isolates the P-type substrate 70 and the p-type well region 71 with an N-type well region 73. In addition, the p-type well region 71 is implanted into a ^ -type source region 72 and an n-type non-polar region 74 at predetermined positions, and a channel region 76 is formed between the source region 72 and the drain region 74. t-Secondly, the above-mentioned stacked gate 80 is formed on the channel region 76 between the source region 72 and the drain region 74 of the p-type well region 71, and the above-mentioned stacked gate 80 is sequentially a tunnel Through oxide layer 8 2. A floating gate 84, a dielectric > layer 86 and a control gate 88. The tunneling oxide layer 82 is located in the p-type well region.

Page 13 V. Description of the invention (π) --1 71 The surface and floating gate 84 are relatively thin. The floating gate 84 is mainly composed of a polycrystalline silicon conductive layer, and the control gate is located in a floating state. The gate 84 is separated by an insulating layer 86 therebetween, such as a silicon oxide layer / silicon nitride layer / silicon oxide layer (ONO). In addition, 'terminal 8 1 is used to provide the source voltage κ and the source region 7 2, terminal 83 is used to provide the gate voltage ^ to control the gate 88, and terminal 85 is used to provide the drain' voltage VD to the drain region 74, the terminal The 89 series provides the well voltage, and the terminal terminal 90 provides the well voltage Vff_w to the ^ well 73, and the terminal 8? Provides a substrate voltage Vp_Sub to the substrate 7 through a P + doped region. . In the erasing phase of this embodiment, the voltage of the well 1 of the N-type well-area 7 3 and the drain voltage vD of the pre-drain and area 74 are floated, and the base voltage Vp s ^ remains grounded. Refer to Figure 3b, which shows an erase step performed by the floating gate memory unit according to Figure 2b, and provide different voltages to the source region, drain region, gate, well region, and substrate. Waveform timing diagram. When erasing the memory unit, it is mainly divided into three stages, which are described below. In the first erasing stage, E1 is a gate / source erasing method, that is, first, a relatively higher voltage is gradually provided to the source region 72 than the control gate 88. For example, it is provided by terminal 8 1 A voltage is gradually increased to vs = 4.3 V to the source region 72, and a relatively lower gate voltage is provided by the terminal 83 and gradually reduced to a voltage of VG = ~ 10V to the control gate 88, and then to Jiang The source voltage Vs is grounded, and then a 5V voltage VpwTp-type well region PW is provided through the terminal 89, and the terminal 87 is grounded to provide a base voltage of VP-Sub = 0V.

V. Description of the invention (12) As for the isolation well region 73 and the drain region 74, the terminals 90 and 85 are used to make the electric block νΐΜϊ and VD of the well region in a floating state f (floating). Secondly, perform the second erasing stage of the performance after this embodiment. £ 2 to strengthen its erasing ability, which is the source erasing method, that is, directly applying a gradually increasing voltage to the source region 72, such as by A gradual increase from the terminal 81 to the source electric dust pulse Vs = 10 V is provided to the source region 7 2 and the terminals 8 3 and 8 9 are grounded to provide the ρ-type well region 71 and the control gate Ve, = . In this way, a high electric field across the buzz oxide layer 82 will be formed between the floating gate 84 and the source region 72, so that the negative charge trapped in the floating gate 84 (a) is toward and opposite the source region 72. ~ Gather and enter. And by ρ

The Fowler-Nordheim (F-N) tunnel effect causes part of the negative charge (a) in the floating gate 84 to be extracted to the source region 72. Due to the hole trapping phenomenon induced between the source 72 and the tunneling oxide layer 82, the positive charge is trapped in the tunneling oxide layer 8 2, so the outflow of hot electrons in the floating gate 8 4 is accelerated in a short time. Under the continuous attraction of the holes trapped in the tunneling oxide layer 8 2, more and more negative charges are drawn out and trapped in the tunneling oxide layer 82, blocking the outflow of hot electrons and slowing down the erasing speed. However, during the third erasing stage E3 of the present embodiment, the foregoing phenomenon will 'can eliminate the holes trapped in the tunnel oxide layer 62, so it will not occur.) More and more negative charges are attracted and trapped in The phenomenon of tunneling the oxide layer 62 is as described below.凊 Refer to the second erasing stage E 3 in Fig. 2b and Fig. 3b, which is the erasing method, that is, firstly, the control gate 88 is applied to the P-type well area 7 丨

Page 15 V. Explanation of the invention (13) u voltage, for example, a relatively high voltage pulse ϋ-1 is provided by terminal 89 (IV f well area 71 'terminal 83 provides a relatively low interpolar voltage pulse idle pole 88' The source voltage of the source region 72 is grounded by t. In this way, a high electric field in the shape of ft crossing the oxide layer 82 between the floating gate 84 and the channel region causes the negative charge trapped in the floating gate (― ) Gathered towards the opposite channel area 76, and then by

Fr2 = Nordheim (F_N) follows the channel effect, so that the residual negative current (~~) in the floating gate 8 ~ 4 is extracted to the channel area 76. When, ==, originally during the stylization, it was trapped by the tunneling oxide layer 82. It will also be sucked out due to the high electricity formed between the floating gate 84 and the channel region 76 above. phenomenon. In addition, in the first and second erasing stages E1 and E2, the positive charges (holes) trapped in the tunnel oxide layer are also controlled by the negative gate f 88 (Vg = ~ 1〇) in the third stage E3. (V) The floating gate 84 is sucked in, so that the phenomenon of causing more and more negative charges to be attracted to trap the penetrating oxide layer 82 during the repeated ergonomic erase operation will not occur. In addition, 'as shown in FIG. 3c', in the erasing voltage form of this embodiment, the reference electrode current ID (erasing conductance value Gm) is the vertical coordinate, and the control gate voltage Vg is the horizontal coordinate. The characteristic curve chart, and compare the initial program / erase curve init of the memory unit and the curve 100k when the program / erase cycle number is more than 100,000 times, you can find that when the program / erase cycle number is more than 100,000 times The curve 1000k has not shifted to the right, that is, the oxide layer can be reduced because it provides an averaged electric field in the teeth by gradually increasing and decreasing the voltage during the entire erasing week. The generation rate of the charge trapping center makes

Page 16 43 91 5 3 Five 'invention description (14)' --------- The conductance value "in the program / erasing cycle number is more than ㈣-people will not be attenuated. Limitation ΐΐΐ invention has been The above is disclosed in the preferred embodiment, but it is not used in the embodiment ^ 丨 = For example, the memory structure used in the present invention is not limited to change, and the present invention: Equipment :: 〒 Therefore, 'Pack II: ϋ' is not limited to the voltage cited in the examples. 1 α None, ^ This artisan can change it without departing from the spirit and target of the present invention :::; The scope of protection of the patent application attached to Deshi is as follows:

Page 17

Claims (1)

Scope of Six Application Patents-Line L A method of using gates / sources, substrates / channels of a floating gate memory device to enter the well, where 'the' floating gate memory device is formed on a substrate with openings, including: The first step of the idler step is increasing-the source is relatively high voltage to the floating phase 1+, a source, and at the same time, a gradually decreasing first gate 1 voltage is provided to one of the floating gate memory devices. Grounding L supply—the relatively high voltage of the first well area to the well, ri) ± the gradually increasing second source relatively high voltage to the source while grounding the control gate and the well area simultaneously; and A first -H supply to the first well area with a relatively high voltage was supplied to the well area, and at the same time a relatively low voltage was provided to suspend a gate to suffocate the ground. I control the gate electrode and remove the source electrode during the erasing period. As described in the second application period of the patent application scope, the separation period will keep the floating closed electrode in mind. The drain of the floating idler memory device: then one or two: the method described in item i of the scope of the patent application ': the base where the sub-gate memory device is located and the gateway: the well area is another isolation The well area, at the same time, I and the two well areas are kept floating. 4. According to the inspection method described in item 1 of the scope of patent application, the relative high voltage of the Long source is gradually increased from about 0V. 5. According to the method described in item 1 of the scope of patent application, the relatively low voltage of the first gate gradually decreases from about 0V to about 10V. In 4391 5 3 6. Scope of patent application 6. As mentioned in item 1 of the scope of patent application, wherein the first well area has a relatively high voltage of about 5 V. Old 7. The building method described in item 1 of the scope of patent application, wherein the relatively high voltage of the second source is gradually increased from about 0 V. 8. The wiping method described in item 1 of the scope of patent application, wherein the relatively low voltage of the second gate gradually decreases from ον to about -10V. 9. The kneading method described in item 1 of the scope of patent application, wherein the second well area has a relatively high voltage of about 5V. ΙϊίΙ 1 0. A method for erasing a gate / source, substrate / channel of a floating gate memory device, wherein the floating gate memory device is formed on a substrate, including: (a) providing a gradual increase The first source is relatively high voltage to a source of the floating gate memory device, while a gradually decreasing first gate relatively low voltage is provided to one of the floating gate memory devices to control the gate, and then, The source is grounded while providing a relatively high voltage of the first substrate to the substrate; (b) providing a gradually increasing second source of relatively high voltage to the source while grounding the control gate and the substrate; And (c) providing a second substrate with a relatively high voltage to the substrate, while providing a second gate with a relatively low voltage to the control gate, and grounding the source at the same time. The said method, wherein the floating gate memory device and the pole are kept in a floating state during the erasing. Page 19 43 9 ": 6. Scope of Patent Application 1 2. The relatively high voltage of the first source as described in item 10 of the scope of the patent application is gradually increased from about 0 V. 1 3. The relatively low voltage of the first gate as described in item 10 of the scope of the patent application. Gradually decreased from 0V to about -10V. 14. The method according to item 10 of the scope of patent application, wherein the relatively high voltage of the first well area is about 5 V. 15. The method / item described in item 10 of the scope of patent application, wherein the relatively high voltage of the second source is gradually increased from about 0V to about 10V. 16. The wiping method as described in item 10 of the scope of the patent application, wherein the relatively low voltage of the second gate is gradually reduced from about 0V to about Ga0V. 17. The copying method described in item 10 of the scope of patent application, wherein the relatively high voltage of the second well area is about 5 V. Page 20