TW466775B - Method for erasing by using gate/source and substrate channel of floating gate memory device - Google Patents

Abstract

A method for erasing by using gate/source and substrate channel of floating gate memory device comprises the steps of: first, performing a first stage of erasing source by providing a 10V voltage to the source area of the floating gate memory device, and grounding the substrate where the floating gate memory device is located and its control gate; next, performing a second stage of erasing channel by keeping the substrate grounded and simultaneously providing a 12V voltage to the control gate.

Description

A7 B7 ^ 66775 V. Description of the invention (l) ----- The present invention is the application No. 86112 () 42 "Method for erasing with gate / source, substrate / channel of floating closed-pole memory device" Of addition. The "method of erasing by using the 7 poles of the floating interpolar memory device and the substrate / channel" disclosed in the mother case of the present. Ming mainly includes the following explanations. Refer to Figure 1, which shows a conventional flash memory unit. Section view. The conventional flash memory cell i includes a semiconductor substrate 10 and a stacked gate 20. The upper semiconductor substrate J 〇 is generally a p-type substrate (P-SUbstrate). At its predetermined position, it is pushed into a doubly-diffused n-type source region (s.⑽e) i2 and n + type substrate. The electrode region 14 forms a channel region (Channe1) 16 between the source region 12 and the drain region. The double-diffusion n-type source region 12 includes a deep diffusion but a light doping. • The doped region 15 and a n + doped region 13 with a shallow diffusion depth but a strong doping. The purpose of forming a double-diffused source region / 2 is to avoid erasing data in the memory cell 丨12 generates an excessively strong electric field. Secondly, the above-mentioned stacked gate 20 is formed on the channel region 16 between the source region 12 and the drain region 14 of the semiconductor substrate 10, and the stacked gate 20 is sequentially A tunnel oxide layer (tunnel 〇χί (^) 22), a floating gate (floating gate) 24, an inter-gate dielectric layer 26, and a control gate (control gate) 28, the tunnel oxide layer 22 is between Between the surface of the substrate 10 and the floating gate 24, the thickness is relatively thin. The floating gate 24 is mainly composed of a polycrystalline silicon conductive layer (co nductive p〇lysmc〇n), the control gate 28 is located above the floating gate 24, and in accordance with a paper size applicable to the Chinese National Standard (CNS) M specification (2 丨 0x297 mm) Please read The matters needing attention are then set by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs to print 4ββ? 75. V. Description of the invention (2 Insulation layer 26 isolation.

In addition, terminal (terminaI pin) 2! Is used to provide source power to source 予 12, terminal 23 is used to provide idle voltage ^ to control gate 28, and terminal 25 is used to provide non-polar voltage% to non-polar region 14, As for the substrate 10, it is generally grounded (grGUnd), so the substrate voltage VP_Sub is 0vV. The conventional program / erase operation on the conventional flash memory unit 1 described above is shown in Figs. 2a, 2b and 3a, Figure 3b. According to Figures 2a and 2b, when the flash memory unit is programmed (prog), the control pole M and the non-polar area of the flash memory unit i are applied to the source pure 12 It is a high voltage, for example, a relatively high voltage pulse is provided by the terminal 23, 〇5 ν is used to control the idler μ, and a relatively next high voltage pulse is provided by the terminal 25, ν〇 = 6ν, is provided to the drain region 14; It is grounded to provide a relatively low voltage Vs = 0v to the source region 12 (not shown). The high electric field formed in this way will generate high-energy hot electrons in the channel region 16 close to the drain region 14, and then accelerate the hot electrons through the tunnel oxide layer 22 and injection. ) To the above floating gate electrode 24. Because the floating gate 24 is surrounded by an insulating layer such as 22 and 26, the hot electrons are injected into the floating gate 24, and then they will fall into the trap and cannot be separated. The negative charge (1) is stored in the floating gate. In the case of pole 24, 'the threshold voltage value thereof is increased by about 3 to 5V, and the result is that when the control gate 28 is pressurized to 5V to read data from this flash memory unit, the channel is not Is turned on, so the data is read, that is, the above flash memory unit 1 has been programmed, as for the general programming time

'' 46671 5 V. Description of the invention (about 1 Opsec. In addition, according to Figures 3a and 3b, when erasing the flash memory unit i, it is tied to the source region of the flash memory unit 1丨 2 Apply a higher voltage than the control gate 28, for example, by providing a relatively high voltage pulse φV to the source region 12 through the terminal 21, and the terminal 23 to ground to provide a relatively low electrical voltage 0V to the control gate 28. As for the non-polar region 14, the floating state is f (floating) (not shown). In this way, a high electric field across the tunneling oxide layer 22 will be formed between the floating gate 24 and the source region 12, so that the negative charges (-) trapped in the floating gate 24 will be concentrated toward the source region 12, Furthermore, through the Fowier_Nórdheim (F_N) tunnel effect, the negative charge (-) in the floating gate 24 is extracted to the source region 12, that is, the above-mentioned flash memory unit has been erased. As for general The erasing time is about 0.1 sec. In addition, 'because the number of program / erase cycle of a memory unit is generally required to be maintained at a predetermined threshold voltage Vth more than 100,000 times, otherwise the entire memory array may be possible. An error occurred during the program / erase operation. In other words, if the endurance is defined as the number of times the memory cells in the array can be reprogrammed / erased, it should not be less than 100,000. However, if the “erase and prgram operation methods are used according to the conventional method”, the tolerance of the memory cell will not easily exceed 100,000 times at a predetermined threshold voltage Vth, for the reasons described below. (1) Stylization period: As shown in Figure 2a and Figure 4, when the memory unit 1 is re-processed-Formula 彳 ^ After a predetermined number of times such as 10, 000, it will be applicable to nearly 5 paper sizes in China National Standard (CNS) Α4 Specification (210 × 297 mm) ---- ^ " ------ 1T ------ '(Please read the notes on the back before filling this page) Printed by the Consumer Cooperative of the Prospective Bureau 46677 5 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 The oxide layer 22 prevents the injection of hot electrons, thereby slowing down the programming speed, so that the threshold voltage Vth value of the memory cell decreases accordingly. (2) Erase period: As shown in Fig. 3a and Fig. 4, when the memory unit 1 is erased again for a predetermined number of times, such as 10,000 times, initially due to the electrical The hole trapping phenomenon causes the positive charge to trap in the tunneling oxide layer 22, and therefore accelerates the outflow of hot electrons in a short time. However, the continuous attraction of the holes trapped in the tunneling oxide layer 22 causes more and more Negative charges are sucked out and trapped in the tunneling oxide layer 22, blocking the outflow of hot electrons, and slowing down the erasing speed, and the threshold voltage Vth value increases accordingly. To sum up, if the traditional erasing and program operation methods are used, then due to the slowing down of the programming / erasing speed 'and the threshold voltage value Vth being too close during the programming / erasing period (eiose), The pressure difference is indistinguishable (as shown in Figure 4), and these phenomena will cause the tolerance of the memory unit to decrease. ^ In addition, in the case of using the substrate bias to improve the erasing effect, as shown in Fig. 1b, if a bias is directly applied to the substrate, for example, a relatively high substrate voltage pulse vp_Sub = 5v is provided by the terminal 27. A bottom contact region 17 'is to keep other semiconductor components such as the substrate of the transistor still grounded, so an additional process must be used to form a three-layer well area structure as shown in the figure, that is, P-type substrate 10, N-type well The area 10a and the p-type well area 10b function to isolate the substrate of other semiconductor components to maintain the grounded state of the substrate of the normal component. = 6 This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm) f Please read the notes on the back before filling in this page) ---------------:- ----: 丨 ^ -I i ------ Order --------- Λ .——— 1 ^-.. · ——1

-------I nm · 46677 5 B7 Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (5 This is the purpose of the present invention is to solve the above problems in order to eliminate the tunneling due to stylization Oxygen permeation is trapped with oxidizing C and θ is the same as the source erasing. A method for erasing the floating gate memory device is provided. The method includes the following steps. Where it is—the substrate is grounded, and—the first relative local voltage is provided to the source region of the floating gate memory device, and at the same time—the first relatively low voltage is provided to the control idler of the floating gate memory device; and then Maintaining “the base money ground and leaving the source region in a floating state” while providing a second negative voltage to the control gate. According to the present invention, the base on which the floating gate is located is set. When grounded, at the same time, the non-electrode region of the floating gate memory device is in a floating state. In addition, according to the present invention, when a second negative voltage is provided to the control gate, the drain region is also in a floating state. Which is based on this That is, the first relatively high voltage providing the source region is about 5 to 15 V, preferably about 10 ν. According to the present invention, the first relatively low voltage providing the control gate is about 0V.-According to the present invention, the second negative voltage of the control gate is about -8 ~ -18V, preferably about _ 丨 2 ν. Another object of the present invention is to provide a floating Method for erasing gate memory device, wherein the floating gate memory device includes a first type source region and a first type drain region, both of which are formed in a second type semiconductor region, and a channel region is The source region extends to the drain region, a floating interpole, (Please read the precautions on the back before filling in this page. J Order> ml In ml This paper size applies to Chinese National Standard (CNS) Α4 · (210X297 mm ^ Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4 6 677 5 V. Description of the invention (6 is located on the channel area, and-the control gate is located on the floating gate, which includes the following steps: first the semiconductor area Ground and provide-the first relative south voltage pulse to the At the same time, a first relatively low voltage is provided to the control gate; at the same time, the drain region is in a floating state; and then the semiconductor region is kept grounded; at the same time, a second negative voltage pulse is provided to the control gate; And at the same time, the polar region and the source region are in a floating state. 'Another purpose of the present invention is to provide a flash-type electrically erasable and programmable read-only memory device erasing method, including-the first- An erasing stage and a second erasing stage, wherein the first erasing stage includes: providing a voltage pulse of about ιον A to a source region of the read-only memory device, and at the same time the read-only memory device is located A substrate and a control gate are grounded 'and the read-only memory I is set at the same time-the drain region is in a floating state = and the first: the erasing phase includes: continuously keeping the substrate grounded, as provided by b-about M2V The voltage pulse is applied to the control gate electrode, and at the same time, the > and the pole region and the source region are in a floating state. According to the present invention, the first erasing phase lasts about 50 msec. & The second erasing phase lasted about 50 msec. Hereinafter, an embodiment of a method for erasing and programming a floating gate memory device according to the present invention will be described with reference to the drawings. The diagram briefly illustrates that the la diagram shows the cross-section of the conventional flash ERepROM unit; the lb diagram shows the cross section of the three-layer well area structure of the conventional flash ERepROM unit; 1 ..---- -1--. Clothing ---------- Order (Please read the precautions on the back before filling this page)

No. 46677 5 A7 B7, Invention Description (7) " ~~ --——-… The second-2a is a diagram showing the schematic diagram of the traditional stylized steps according to the conventional flash eeprom 70 in the first figure. ; Figure 2b shows a conventional stylization step based on Figure 2a, providing different voltage μ, drain, gate, and substrate sequence diagrams; * Figure Ja shows a knowledge based on Figure 1 Schematic diagram of flash EEPROM unit's traditional erasing steps; Figure 3b shows a waveform diagram of different voltages to the source region, the non-electrode region, the gate and the substrate according to the traditional erasing step of Figure 3a; Figure 4 shows a test chart of memory cell tolerance when the traditional stylization / erase step is performed according to Figure 2b and Figure%; Figure 5a shows a floating gate memory unit; Figure 5b shows a Floating closed-pole memory cell according to Fig. 5a = stylized step towels in solid red, providing different waveform timing diagrams of source region, non-electrode region, gate and substrate; Fig. 5c shows a diagram according to Fig. 5a The erase steps implemented by the floating gate memory list provide different voltages Waveform timing diagrams of the source and drain gates and substrates; and Fig. 5d is a sectional view showing the floating gate memory cell of Fig. 5a after erasing according to the first erasing stage of Fig. 5c; Fig. 5e The figure is a cross-sectional view of the floating gate memory unit in FIG. 5a after being erased according to the second erasing stage of FIG. 5c; and FIG. 6 shows the floating gate memory unit in accordance with FIG. 5b. 9 gray paper Zhang scale is applicable to China-standard (CNS) A4 specification (centimeter

466775 Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs Α7 Β7 V. Description of the invention (8) ---- The test chart of tolerance of floating gate memory unit when the stylized / erased step of the invention is implemented. [Symbol description] 1, 5 to memory cell 10, 50 to semiconductor substrate 12 (13, 15), 52 (53, 55) to dual-region 14, 54 to drain region [6, 56 to channel region 20, 60 ~ Stacked gates 22, 62 ~ Tunneling oxide layers 24, 64 ~ Floating gates 26, 66 ~ Inter-gate dielectric layers 28, 68 ~ Control gates to implement you 丨 please refer to Figure 5a, which shows-based on floating The gate memory unit 5 is a schematic diagram of the erasing steps of the present invention. The floating gate memory unit $ is generally a flash memory unit, such as electrically erasable and programmable read-only EEPROMs. A semiconductor region 50 and a stacked gate 60. The semiconductor region 50 is generally a p-type substrate, or a p-type substrate having a P-type well and isolated by an N-type well (if this structure is used, the substrate voltage VP-Sub described below refers to the p-type substrate. Well voltage). In addition, double-diffused n-type source regions 52 and n + -type and electrode regions 54 are implanted at predetermined positions of the substrate, respectively, and a channel region 56 is formed between the source region 52 and the non-electrode region 54. Among them, the double-diffusion n-type source region 52 includes a 10-degree paper scale that applies the Chinese National Standard (CNS) A4 specification (210'〆297 mm) I -------.! I —— *-.. (Please read the notes on the back before filling out this page) Order, • Bundle, 46677 5

46677 5

Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs

ον 予 Substrate 50. For example, ... the high electric field formed by Vg = 10.5V will cause high-energy hot electrons to be generated in the channel region 56 close to the drain region 54 and further accelerate the hot electrons to pass through the tunnel oxide layer 62 and implant ( injection) to the floating gate electrode 64 described above. Because the floating gate 64 is surrounded by insulating layers such as 62 and 66, hot electrons are injected into the floating gate 64 and then cannot be separated. The negative charge (-) is stored in the floating gate 64. In this case, the threshold value is increased by about 3 to 5V. As a result, when the gate electrode 68 is to be pressurized to $ v by reading data from the gate memory unit 5, the channel is not turned on. The read data is ⑴, that is, the above floating pole memory 5 has been programmed, and the general programming time is about ⑼. -It is also unavoidable that during the above-mentioned stylization, as shown in the dimensional diagram, when the memory unit 5 is stylized, the electron capture phenomenon will be induced near the electrode ^ f, causing some hot electrons to trap. In the tunneling layer 62, these negative charges will block the injection of hot electrons in the next programming process. However, the above phenomenon will have a considerable improvement effect after the erasing step of the present invention is implemented. ": Refer to Fig. 5c, which shows an erasing step performed according to the floating gate u70 of Fig. 5a, and provides different voltages to the source region 5 to 2, the pole region M, the stacked gate 60, and the substrate. Waveform timing diagram of 50. When E Tian erases (己 e) °° 己 the single fan 5, it is mainly divided into two stages, which are described below.-Please refer to Figure 5d and Figure 5c first The erasing stage m -------- L ^ ---------- order ------ qi .———— IJ -------- ΓΓ • / ι \ ( (Please read the notes on the back before filling out this page)

The Central Bureau of Standards and Consumer Goods Cooperative is 100msec 'better is 50msec, which is the source erasing method', that is, the source region 52 is first applied higher than the control gate 68 The voltage 'for example, provides a relatively high source voltage pulse 10V to the source region 52 through the terminal 61', and the terminal 63 'is grounded to provide a relatively lower gate voltage Vg = 0V to the control gate 68, as for the drain of the drain region 54 The terminal voltage VD is brought to a floating state f (^ 〇) by the terminal η, and the terminal 67 is first grounded to provide a relatively low substrate voltage Vp. Sub-〇V to the substrate 50. So the floating gate A high electric field across the tunneling oxide layer 62 will be formed between 64 and the source region 52, so that the negative charges trapped in the floating gate 64 (a) will be concentrated toward the source region 52, and then by Fowler- The Nordheim (FN) tunnel effect causes a portion of the negative charge (-) in the floating gate 64 to be extracted to the source region 52. Similarly, the hole trapping phenomenon is induced between the source electrode 52 and the tunneling oxide layer 62, and the positive charge is trapped in the tunneling oxide layer 62. Therefore, the outflow of hot electrons in the floating gate 64 is accelerated in a short time, but With the continuous attraction of the holes trapped in the tunneling oxide layer 62, more and more negative charges are drawn out and trapped in the trailing oxide layer 62, blocking the outflow of hot electrons and slowing down the erasing speed . However, during the second erasing stage E2 of this embodiment, the foregoing phenomenon will eliminate the holes trapped in the tunnel oxide layer 62, so more and more negative charges will not be attracted and trapped in the through The phenomenon of the oxide layer 62 is as follows. Please refer to the second erasing stage e 2 in FIG. 5e and FIG. 5c. The period is about 5 ~ 100msec, preferably 50msec. It is a channel erasing method, that is, firstly grounding the substrate 50, such as by 13 paper provided by terminal 67. Applicable to Chinese national standard (CNS> A4 size (210X297mm) (Please read the precautions on the back before filling in this page)

46677 5 C7 D7 Printed by the Consumers 'Cooperatives of the Central Procurement Bureau of the Ministry of Economic Affairs V. Creative Instructions () ~' 12

Vp-sub = 0V voltage to the substrate 50 to avoid the additional complicated three-layer well structure process. Terminal 63 provides a relatively low gate voltage pulse G 10V to control the gate 68, as for j: and pole 54 The terminal voltage and the source voltage ν $ of the source region 52 are brought into a floating D floating state by the terminal 65′61. In this way, a high electric field across the tunneling oxide layer 62 will be formed between the floating gate 64 and the channel region 56, so that the negative charges (-) trapped in the floating gate 64 will be collected toward the channel region 56. The Fowler-Nordheim (FN) tunneling effect causes the residual negative charge (-) in the floating gate 64 to be extracted to the channel area%. At the same time, during the stylization period, the negative electricity trapped in the tunneling oxide layer 62 will also be sucked out due to the high electric field formed between the floating gate 64 and the channel region 56 to eliminate the phenomenon of blocking hot electron injection. In addition, in the first erasing stage E1, the positive charges (holes) trapped in the tunneling oxide layer 62 are also drawn into the floating gate 64 by the negative voltage (Vg = _1〇v) of the control gate 68, so it will not occur. When the program erasing operation is repeatedly performed multiple times, more and more negative charges are attracted and trapped in the tunneling oxide layer 22. The erasing / programming and reading operation range of the floating gate memory device of the present invention are as shown in Table 1. _____ 14 Standard for Postman (CNS) A4 (21 () \ 297mm —> ---------- (Please read the precautions on the back before filling this page)

* 1T line 46677 5 C7 D7 13 V. Creation instructions (

裎 忐 ^ Table. »Rr. I ----

Ε1 Channel erase Ε2 Read -8V—18V ~ 0 · 5 V ~ Vcc Floating ~~~~ _ Floating 0V 0V ~~ 1 ^ Known as 3_5V. Table C shows the voltage of the power supply. For example, the current used electricity is fully clear. Refer to Figure 6, which shows the display. The memory unit implements the invention according to the floating chart of Figure%. Also, when the formulating / erasing step, the floating gate Memory sheet ::::: Test chart 'From this figure, we can know the program / erasing of the memory unit ^ Person: Maintained at a predetermined threshold voltage—under ultra-low_ :, that is, during the programming, the threshold voltage Yang maintains During the erasing period around MV, the threshold voltage vth is maintained at Q ~ iv, and a close phenomenon (clOse) occurs, such as I _ Tao Xiang and his appearance, which shows that the traditional erasing β = and the current consistent application At the time of application, the approach ratio of the material / erase f Vth is at the center U. ), From Figure 4, Figure 6, and Table-we can see that 'the approach ratios after the program / erase cycle are 76.8% and 5.3%, respectively' and this example is close after the program / erase cycle The ratio is only 3.5%, so the entire memory array is less prone to errors during program / erase operations. In other words, according to the erasing (_e) and program operation method of the present invention, its tolerance, that is, the number of times the memory unit in the array can be reprogrammed / erased, will be no less than 100, _ times. . (Please read the notes on the back before filling out this page) ----------: --1 / ------- ιτ --- ^ ---_-- 泉-_.- 〆-: #-^ -------------- 15 Using Chinese National Standards (CNS) 8 4 threats (210X297) • U-1 46677 5 5. Invention Description ") A7 B7 __ ------ Initial program / erase threshold voltage difference Only erase 5.14V in this embodiment 7- 5.69V Last program / erase threshold voltage difference 119V (20K times) 5.49V (100K times) Proximity ratio. /〇76.8% 3.5%, although the indigenous invention has been disclosed as above with a good example, it is not used to limit the invention. For example, the application of the invention is not limited to implementation. Those cited in the examples can be replaced by a variety of appropriate characteristics: and the erasing method of the present invention is not limited to the voltage used in the embodiment I. Because of A, anyone skilled in this art will not depart from the present invention. Within the spirit and scope, it can be modified and retouched. Therefore, the scope of protection of the present invention is regarded as the scope of the patent application attached is defined by the Ministry of Economic Affairs, the Central Standards Bureau, the staff consumer cooperative printed the standard I standard for a country-international use -Fit-degree ruler Sheet-Paper 6 I cm (Please read the notes on the back before filling out this page)

Claims (1)

46677 5 Apply for a patent Fan Yuan to carry out the leisure / source, base / channel of the floating floating-pole memory device / include · Provide one or two 1: official: where the gate memory device is located-the base is grounded, and the zone is connected, and 2 voltages are applied to the pole A relatively low voltage of one of the source gates is recorded to the floating gate memory device state, grounded to the bottom, and the pole region is in a floating state, and a second negative voltage is applied to the control gate. The erasing method described in item 1 of the proposed scope, wherein, leisure irr: control of the low-electricity dust to the floating interpolar memory device. The area of the floating miscellaneous floating gate memory is in drift 3. The erasing method according to item fi of the patent scope, wherein, when the gate: 々: Γ negative voltage is applied to the control gate, at the same time, one of the floating electrodes is floating. β 4 • As described in item 1 of the patent application, the first relatively high voltage of the source region providing the source region is about 5 to 15 ν. 5. The erasing method according to item 1 of the scope of patent application, wherein the-relatively low voltage of the control gate provided is about GV. 6. The erasing method according to item 1 of the patent application scope, wherein the second negative voltage provided by the control gate is about _8 ~ _18V. 7. A method for erasing a floating gate memory device, wherein the floating gate memory device includes a first type source region and a first type drain region, both of which are formed in a second type semiconductor region, a The channel area is from the source area 17 (please read the precautions on the back before filling out this page). Standards for this paper (m) A4 ^ m (210X297 ^) ----- A8 B8 C8 D8 VI. Application · # · 利 顾 '-Extend to the non-polar area,-floating gate, located in the The control gate on the channel area is located on the floating pole, which includes the following steps: Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, printed 46677 5 and first grounded the second type semiconductor area while providing -s-relatively high voltage Pulse to the source region; at the same time provide a first relatively low voltage to the control gate; at the same time make the drain region float; then keep the second type semiconductor region grounded; and simultaneously provide a second negative voltage The pulse is applied to the control gate; and the drain region and the source region are both in a floating state at the same time. The erasing method described in item 7 of the scope of patent application, wherein the first relatively high voltage pulse providing the source region is about left and right. ^ 9. The erasing method according to item 7 of the scope of the patent application, wherein the first relatively low voltage of the control gate is about 0v. / 〇 · The erasing method described in item 7 of the scope of patent application, wherein the second negative voltage pulse of the control gate is provided approximately = * 11. The erasure as described in item 7 of scope of patent application The method, wherein the first type includes an N type and the second type includes a P. type. ▲ The erasing method according to item 7 of the scope of patent application, wherein the source region includes a double-diffused N-type source region. ^ = The erasing method as described in item 12 of the scope of the patent application, wherein the double-diffused N-type source region includes a N-doped planting region with a deeper diffusion depth but belonging to Awasaki, and a shallower but deeper diffusion depth. Planting area. Chen Doping 14 · —A kind of flash-type electrically erasable and programmable read-only memory device This paper is applicable from China National Standards (cns) Age q χ 297 public envy (Please read the precautions on the back before (Fill in this page) 4 6 677 5 A8 B8 C8 D8 6. The method of erasing the scope of patent application, including the first erasing stage and the second erasing stage. The Central Standards Bureau of the Ministry of Economic Affairs, Industrial and Consumer Cooperatives printed the first erasing stage. The method includes: grounding a substrate on which the read-only memory device is located, and providing a voltage pulse of about 10V to the source region of the read-only memory, and grounding a control gate of one of the read-only memory devices, And at the same time, a drain region of one of the read-only memory devices is in a floating state; the second erasing stage includes: keeping the second type semiconductor region grounded, and simultaneously providing a voltage pulse of about _12V to the control interrogator, At the same time, the drain region and the source region are in a floating state. > 15. The erasing method according to item 14 of the scope of patent application, wherein the " first erasing stage > lasts approximately 5 to 100 msec. ^ I6. The erasing method according to item 15 of the scope of application for a patent, wherein the second erasing stage lasts about 5 to 100 msec. VIII 17. According to the erasing method described in item 14 of the scope of the application for a patent, the first erasing stage should preferably last approximately 50 msec. Eight '^ The erasing method as described in item 17 of the scope of patent application, wherein the first-erasing stage lasts approximately 50 msec. 19 This paper _ Use t country (dirty 297i (please read the precautions on the back before filling out this page) · -—Order-