經濟部中央揉準局貝工消费合作社印製 33460ϊ Α7 ___Β7 _ 五、發明説明（1 ) 本發明係有關於一種漂浮閘極（floating gate)記憶裝 置之抹除（erase)方法，特別有關於一種快閃記憶單元 (flash memory cell)如可電性抹除及可程式化唯讀記憶體 (flash electrically erasable and programmable read-only memory devices ； flash EEPROMs )之抹除方法。 請參照第1圖，其係顧示習知快閃記憶單元的剖面 圓》習知快閃記憶單元1包括一半導體基底1〇以及一堆 疊閘極（stacked gate)20 »上述半導體基底1〇—般為p型 基底（P-substracte)，於其既定位置則分別摻植成雙擴散 (double-diffused)n 型源極區（source)12 及 n+型没極（drain) 區14，同時於上述源極區12與上述汲極區14之間形成 通道區（channel)16 »其中，雙擴散n型源極區12包括一 擴散深度較深但屬於淡摻雜之η·摻植區15，及一擴散深 度較淺但屬於濃摻雜之η+摻植區13。形成雙擴散Ν型源 極區12之目的在於對記憶單元1進行資料抹除時，避免 於源極區12產生過強之電場。 其次，上述堆疊閘極20係形成於上述半導體基底1〇 之源極區12與ί及極區14之間的通道區16上，且上述堆 4閘極20係依序為一隧穿氧化層（tunnel oxide)22、一漂 浮閘極（floating gate)24、一閘間介電層26以及一控制閘 極（control gate)28，隨穿氧化層22係介於基底1〇表面及 漂浮閘極24之間，其厚度則相對為薄，漂浮閘極24主 要是由複晶梦導電層（conductive polysilicon)組成，控制 閘極28則位於漂浮閘極24之上，其間並以一絕緣層26 本紙張尺度適用中國國家標準（CNS > A4規格（210X297公釐） ----------装------^------^ 』 一 ί (請先«讀背面之注$項再填寫本頁) 334601 A7 B7 經濟部中央標準局員工消費合作社印裝 五、發明説明（2 隔離。 此外，端子（terminal pin)21係用以提供源極電壓Vs 予源極區12 ’端子23係提供閘極電壓VG予控制閘極 28，端子*25則用以提供汲極電壓VD予汲極區14 ,至於 基底10 —般均予以接地(gr〇und)，故基底電壓Vp為 0V » 另有關對上述習知快閃記憶單元1進行傳統之程式/ 抹除操作，係如第2a、2b圖及第3a、3b圖所示。 依據第2a、2b圏，當對快閃記憶單元1進行程式化 (program)時，係於上述快閃記憶單元i的控制閘極28及 汲極區14施加較源極區12為高的電壓，例如藉由端子 23提供相對較高電壓脈衝1〇 5V予控制閘極28 ,且藉由 端子25提供相對次高電壓脈衝6V予汲極區14，端子21 則予以接地以提供相對較低電壓〇V予源極區丨2(未顯 示）。如此所形成之高電場，將使在通道區16接近汲極區 14處產生高能（high energy)之熱電子（hot electron)，進 而’使熱電子加速越過上述随穿氧化物層22並注入 (injection)至上述漂浮閘極24 » 由於漂浮閘極24周圍均由絕緣層如22、26所包 圍’故熱電子注入至上述漂洋閘極24後，便陷入（trapped) 其中而無法脫離’在負電荷（一）儲存於漂浮閘極24之情 況下，其臨限電壓值（threshold voltage)約提高3至5V， 結果，當欲對此快閃記憶單元1讀取資料而將控制閘極 28加壓至5V時，通道並未導通，故讀取資料為（1)，亦 4 本紙張尺度通用中國國家揉準（CNS ) A4規格（2I0X297公麓） -----^—---—裝------訂-----：丨線 ~ - (請先聞讀背面之注$項再填寫本頁) 經濟部中央標準局員工消費合作社印装 A7 B7 五、發明説明（3 ) 即上述快閃記憶單元1已被程式化，至於一般程式化時 間則約lOpsec左右》 另依據第3a、3b圊，當對快閃記憶單元1進行抹除 (erase)時，係於上述快閃記憶單元1的源極區12施加較 控制閘極28為高的電壓，例如藉由端子21提供相對較 高電壓脈衝10V予源極區12，端子23則予以接地以提 供相對較低電壓0V予控制閘極28，至於汲極區14則使 之處於漂浮狀態f(fl〇ating)(未顯示）。如此在漂浮閘極24 與源極區12之間會形成一橫越隧穿氧化物層22之高電 場，使陷於漂浮閘極24之負電荷（一）朝相對源極區12之 位置聚集，進而藉由Fowler-Nordheim(F-N)随道效應，使 漂浮閘極24内之負電荷（一）被吸出（extracted)至源極區 12，亦即上述快閃記憶單元1已被抹除，至於一般抹除 時間則約0.1 sec左右。 此外，由於一記憶單元之程式/抹除循環次數（the number of program/erase cycle)—般均要求維持在一既定 臨限電壓Vth下超過100,000次，否則整個記憶陣列 (memory array)便有可能在程式/抹除操作期間發生失 誤。換言之，若定義容忍度（endurance)為陣列中之記憶 單元能重新程式/抹除的次數，則其不應少於100,000次。 煞而，若依據傳統抹除（erase)及程式（program)操作 方法，則記憶單元之容忍度將不易在一既定臨限電壓Vth 下超過100,000次，理由如下所述。 (一）程式化期間：如第2a圖及第4圖所示，當記憶 本紙張又度適用中國國家標準（CNS ) A4規格（210X297公釐） -—-I— H I I I I I 裝— I I I I I 訂— I I I __ —線 - i ~ 乂請先阶讀背面之注意事項再填寫本頁) 3346〇χ 經濟部中央棣準局貝工消費合作衽印袋 A7 B7 五、發明説明（4 ) 單元1重新程式化一既定次數如10,〇〇〇次後，將在接近 沒極14處引發（induced)電子捕獲現象，使負電荷陷於隧 穿氧化物層22，阻擋了熱電子的注入，進而減緩程式化 速度’以-至於記憶單元之臨限電壓vth值隨之下降。 (二）抹除期間：如第3a圖及第4囷所示，當記憶單 元1重新抹除一既定次數如1〇,〇〇〇次後，初始由於在源 極12與隧穿氧化物層22之間引發電洞捕獲現象，使正 電荷陷於隧穿氧化物層22，因此短期内加速了熱電子之 流出，但隨之在陷於隧穿氧化物層22之電洞的持續吸引 下’使愈來愈多之負電荷被吸引而陷於隧穿氧化物層 22 ’阻擋了熱電子的流出，並減緩了抹除速度，且臨限 電壓Vth值隨之上昇。 综由上述’若採用傳統之抹除及程式操作方法，則 由於程式化/抹除速度的減緩，及程式化/抹除期間之臨限 電壓值Vth的過於靠近（ci〇se)造成兩者之壓差不可分辨 (如第4囷所示），此些現象均將導致記憶單元的容忍度下 降。 有鑑於此，本發明之目的係為了解決上述問題，以 消除因程式化陷於隧穿氧化層之電子，及因源極抹除而 陷於隧穿氧化層之電洞，而提供一種以漂浮閘極記憶裝 置之閘/源極、基底/通道進行抹除之方法，其包括：首先 提供一第一相對高電壓予該漂浮閘極記憶裝置之一源極 區，同時提供一第一相對低電壓予該漂浮閘極記憶裝置 之一控制閘極，同時將該漂浮閘極記憶裝置所在之一基 I— I-丨^tr「"Ί (請先閲讀背面之注意事項再填寫本頁)Printed by the Peking Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs, 33460 ϊ Α7 ___ Β7 _ V. Description of the invention (1) The present invention relates to an erase method of a floating gate memory device, in particular to a method The method of erasing flash memory cells (flash memory cells) such as flash electrically erasable and programmable read-only memory devices (flash EEPROMs). Please refer to FIG. 1, which shows the cross-sectional circle of the conventional flash memory unit. The conventional flash memory unit 1 includes a semiconductor substrate 10 and a stacked gate 20. The above-mentioned semiconductor substrate 10— Generally, it is a p-substracte, which is implanted into a double-diffused n-type source region 12 and an n + -type drain region 14 at the predetermined positions, and at the same time A channel 16 is formed between the source region 12 and the drain region 14 »wherein, the double-diffused n-type source region 12 includes an η-doped region 15 with a deep diffusion depth but belonging to light doping, and A η + doped region 13 with a shallow diffusion depth but belonging to a strong doping. The purpose of forming the double-diffused N-type source region 12 is to avoid generating an excessive electric field in the source region 12 when erasing data from the memory unit 1. Secondly, the stacked gate 20 is formed on the channel region 16 between the source region 12 and the electrode region 14 of the semiconductor substrate 10, and the stack 4 gate 20 is a tunnel oxide layer in sequence (Tunnel oxide) 22, a floating gate (floating gate) 24, an inter-gate dielectric layer 26 and a control gate (control gate) 28, along with the through oxide layer 22 is between the surface of the substrate 10 and the floating gate Between 24, the thickness is relatively thin, the floating gate 24 is mainly composed of a conductive polysilicon (conductive polysilicon), the control gate 28 is located above the floating gate 24, and an insulating layer 26 The paper standard is applicable to Chinese national standard (CNS & A4 specification (210X297mm) ---------- install ------ ^ ------ ^ 』一 ί (please read« Read (Note $ item on the back to fill in this page) 334601 A7 B7 Printed by the Consumers ’Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of invention (2 isolation. In addition, terminal pin 21 is used to provide source voltage Vs to the source In the region 12 ', the terminal 23 provides the gate voltage VG to the control gate 28, and the terminal * 25 is used to provide the drain voltage VD to the drain region 14. The substrate 10 is generally grounded, so the substrate voltage Vp is 0V »In addition, the conventional programming / erasing operation of the above-mentioned conventional flash memory unit 1 is shown in FIGS. 2a, 2b and 3a 3b. According to paragraphs 2a and 2b, when the flash memory unit 1 is programmed, the control gate 28 and the drain region 14 of the flash memory unit i are applied with a higher source Region 12 is a high voltage, for example, a relatively high voltage pulse of 105V is provided to control gate 28 through terminal 23, and a relatively high voltage pulse of 6V is provided to drain region 14 through terminal 25, and terminal 21 is grounded. In order to provide a relatively low voltage 〇V to the source region 丨 2 (not shown). The high electric field formed in this way will cause high energy hot electrons to be generated in the channel region 16 close to the drain region 14 ), And then 'accelerate the hot electrons across the follow-through oxide layer 22 and inject (injection) into the floating gate 24 »Because the floating gate 24 is surrounded by insulating layers such as 22, 26', the hot electron is injected into After drifting above the gate pole 24, it trapped into it and could not escape In the case where negative charge (1) is stored in the floating gate 24, its threshold voltage is increased by about 3 to 5V. As a result, when the data of the flash memory unit 1 is to be read, the gate will be controlled When the 28 is pressurized to 5V, the channel is not connected, so the reading data is (1), and the size of the paper is 4 Chinese National Standard (CNS) A4 specifications (2I0X297 Gonglu) ----- ^ ---- -—Install ------ order ----- ： 丨 line ~-(please read the $ item on the back and then fill in this page) A7 B7 printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Invention Explanation (3) That is, the above flash memory unit 1 has been programmed, and the general programming time is about 10Opsec. According to paragraphs 3a and 3b, when erasing the flash memory unit 1, A higher voltage is applied to the source region 12 of the flash memory unit 1 than the control gate 28, for example, a relatively high voltage pulse 10V is provided to the source region 12 through the terminal 21, and the terminal 23 is grounded to provide a relatively high voltage. The low voltage 0V pre-controls the gate 28, and the drain region 14 makes it float (f〇ating) (not shown). In this way, a high electric field across the tunnel oxide layer 22 will be formed between the floating gate 24 and the source region 12, so that the negative charge (1) trapped in the floating gate 24 will gather toward the position opposite to the source region 12, Furthermore, by the Fowler-Nordheim (FN) tracking effect, the negative charge (1) in the floating gate 24 is extracted to the source region 12, that is, the flash memory unit 1 has been erased. The general erasing time is about 0.1 sec. In addition, since the number of program / erase cycle of a memory unit generally requires more than 100,000 times under a predetermined threshold voltage Vth, otherwise the entire memory array may be possible An error occurred during the program / erase operation. In other words, if endurance is defined as the number of times a memory cell in the array can be reprogrammed / erased, it should not be less than 100,000 times. Moreover, if the conventional erase and program operation methods are used, the tolerance of the memory unit will not easily exceed 100,000 times under a given threshold voltage Vth, for the reasons described below. (1) During the programming period: as shown in Figure 2a and Figure 4, when the memory paper is again applicable to the Chinese National Standard (CNS) A4 specification (210X297mm)---I-HIIIII installation-IIIII order-III __ —Line-i ~ Please read the precautions on the back first and then fill out this page) 3346〇χ The Ministry of Economic Affairs Central Bureau of Industry and Economics Beigong Consumer Cooperative Printing Bag A7 B7 V. Description of Invention (4) Unit 1 Reprogramming After a predetermined number of times, such as 10,000 times, an electron trapping phenomenon will be induced near the electrode 14, causing negative charges to trap in the tunneling oxide layer 22, blocking the injection of hot electrons, thereby slowing the programming speed 'Yes- As for the threshold voltage vth of the memory unit drops accordingly. (2) Erase period: As shown in Figures 3a and 4th, when the memory unit 1 is erased again for a predetermined number of times, such as 10,000 times, initially due to the source electrode 12 and the tunneling oxide layer The hole trapping phenomenon is caused between 22, causing the positive charge to trap in the tunnel oxide layer 22, so the outflow of hot electrons is accelerated in a short period of time, but then under the continuous attraction of the hole trapped in the tunnel oxide layer 22 More and more negative charges are attracted and trapped in the tunnel oxide layer 22 'to block the outflow of hot electrons and slow the erasing speed, and the threshold voltage Vth value increases accordingly. In summary, if the traditional erasing and programming methods are used, the speed of programming / erasing is slowed, and the threshold voltage Vth during programming / erasing is too close (ci〇se). The pressure difference is indistinguishable (as shown in Chapter 4). All these phenomena will lead to a decrease in the tolerance of the memory unit. In view of this, the purpose of the present invention is to solve the above problems, to eliminate electrons trapped in the tunnel oxide layer due to programming, and holes trapped in the tunnel oxide layer due to source erasure, and to provide a floating gate electrode The method for erasing the gate / source and substrate / channel of the memory device includes: firstly providing a first relatively high voltage to a source region of the floating gate memory device and simultaneously providing a first relatively low voltage to One of the floating gate memory devices controls the gate, and at the same time, the base of the floating gate memory device is I-I- 丨 ^ tr "" Ί (please read the precautions on the back before filling this page)
經濟部中央標準局貝工消費合作社印製 A7 B7 五、發明説明（5 ) 底接地；及隨後提供一第二相對高電壓予該基底，同時 提供一第二相對低電壓予該控制閘極。 其中依據本發明，在同時將該漂浮閘極記憶裝置所 在之一基底接地時，同時使該漂浮閘極記憶裝置之一汲 極區處於漂浮狀態。 此外依據本發明，在提供一第二相對低電壓予該控 制閘極時，同時使該汲極區及該源極區處於漂浮狀態。 其中依據本發明，提供該源極區之該第一相對高電 壓約為0.5V至Vcc左右，較佳者約為5V。 其中依據本發明，提供該控制閘極之該第一相對低 電壓約為-6〜-15V左右，較佳者約為-10V。 其中依據本發明，提供該基底之該第二相對高電壓 約為0.5V至Vcc左右，較佳者約為5 V » 其中依據本發明，提供該控制閘極之該第二相對低 電壓約為-6〜-15V左右，較佳者約為-10V。 本發明之另一目的係提供一種漂浮閘極記憶裝置之 抹除方法，其中該漂浮閘極記憶裝置包括一第一型源極 區及一第一型汲極區，兩者形成於一第二型半導趙區， 一通道區則自該源極區延伸至該汲極區，一漂浮閘極， 位於該通道區上，及一控制閘極，位於該漂浮閘極上， 其包括下列步驟：首先提供一第一相對高電壓脈衝予該 源極區；同時提供一第一相對低電壓予該控制閘極；同 時使該該半導體區接地；同時使該汲極區處於漂浮狀 態；隨後提供一第二相對低電壓脈衝予該控制閘極；同 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） ----------^------,tT------0 - - 一 ί (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作社印製 A7 B7 五、發明説明（6 ) 時提供一第二相對高電壓脈衝予該半導體區；及同時使 該汲極區及源極區處於漂浮狀態》 本發明之又一目的係提供一種快閃式可電性抹除及 可程式唯-讀記憶裝置之抹除方法，包括一第一抹除階段 及一第二抹除階段，其中，該第一抹除階段包括：提供 一約5V左右之電壓脈衝予該唯讀記憶裝置之一源極 區，同時提供一約-10V左右之電壓脈衝予該控制閘極， 同時將該唯讀記憶裝置所在之一基底接地，同時使該唯 讀記憶裝置之一汲極區處於漂浮狀態；及該第二抹除階 段包括：提供一約5V左右之電壓脈衝予該基底，同時提 供一約-10V左右之電壓脈衝予該控制閘極，同時使該汲 極區及該源極區處於漂浮狀態》 其中依據本發明，該第一抹除階段約持續50msec。 此外該第二抹除階段則約持續50msec。 以下，就圖式說明本發明之漂浮閘極記憶裝置之抹 除及程式化方法的實施例。 圖式簡單說明 第1圖係顯示習知快閃EEPROM單元的剖面圖； 第2a圖係顯示一依據第1圖之習知快閃EEPROM單 元，實施傳統程式化步驟之示意圖； 第2b圖係顯示一依據第2a圖之傳統程式化步驟，提 供不同電壓予源極區、汲極區、閘極及基底之波形時序 QE) · 圃， 第3a圖係顯示一依據第1圖之習知快閃EEPROM單 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） --^------ΐτ----- (請先閱讀背面之注意事項再填寫本頁) A7 ---—----—____^__ 五、發明説明（7) 元’實施傳統抹除步驟之示意圖； 第3b圖係顯示一依據第3a圖之^傳統抹除步驟，提供 不同電壓予源極區、汲極區、閘極及基底之波形時序圓； 第4圓係顯示一依據第2b圖及第3b圊實施傳統程式 化/抹除步驟時，記憶單元容忍度之測試圖； 第5a圖係顯示一漂浮閘極記憶單元； 第5b圖係顯示一依據第5a圖之漂浮閘極記憶單元 所實施之程式化步驟中’提供不同電壓予源極區、汲極 區、閘極及基底之波形時序圖； 第5c圖係顯示一依據第5a圖之漂浮閘極記憶單元 所實施之抹除步驟中，提供不同電壓予源極區、没極區、 閘極及基底之波形時序圖；及 第5d圖係顯示第5a圖之漂浮閘極記憶單元依據第 5c圖之第一抹除階段進行抹除後之剖面圖； 第5e圖係顯示第5a圖之漂浮閘極記憶單元依據第 5c圖之第二抹除階段進行抹除後之剖面圖；及 經濟部中央標準局貝工消費合作社印製 ί·- m# ^mn v^m - . (請先閲讀背面之注意事項再填寫本頁) 第6圖係顯示一依據第5b圓之漂浮閘極記憶單元實 施本發明程式化/抹除步驟時，漂浮閘極記憶單元容忍度 之測試圖》 [符號說明] 1，5〜記憶單元 - 10，50〜半導體基底 12(13、15)，52(53、55)〜雙擴散源極區 14，54〜汲極區 本紙張尺度適用中國國家標準（CNS > A4说格（210X297公釐） 〇346〇ι Α7 Β7 經濟部中央標準局貝工消費合作社印製 五、發明説明（8 ) 16 ，56〜通道區 20 ，60~堆疊閘極 22 ，62〜隧穿氧化物層 24 ，-64〜漂浮閘極 26 ，66〜閘間介電層 28 實施例 ，6 8〜控制閘極 請參照第5a圖，其顯示一依據漂浮閘極記憶單元 5，實施本發明抹除步驟之示意圖，漂浮閘極記憶單元5 一般為快閃記憶單元，例如可電性抹除及可程式化唯讀 記憶體（EEPROMs)，其包括一半導體區50以及一堆疊閘 極60。上述半導體區50—般為P型基底，或者為一具有 一 P型井，並以一 N型井隔離之P型基底（若為此結構則 以下所述之基底電壓VP_Sub係指P型井電壓）。另於基底 既定位置則分別摻植成雙擴散η型源極區52及n+型汲極 區54，同時於上述源極區52與上述汲極區54之間形成 通道區56。其中，雙擴散η型源極區52包括一擴散深度 較深但屬於淡摻雜之η摻植區55，及一擴散深度較淺但 屬於濃摻雜之η+摻植區53。 其次，上述堆疊閘極60係形成於上述半導體基底50 之源極區52與汲極區54之間的通道區56上，且上述堆 疊閘極60係依序為一隧穿氧化物層62、一漂浮閘極64、 一閘間介電層66以及一控制閘極68，隧穿氧化物層62 係介於基底50表面及漂浮閘極64之間，其厚度則相對 本紙張尺度適用中國國家標準（CNS ) Α4洗格（210X297公釐） I-------一--^-----------^ (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（9 ) 為薄，漂浮閘極64主要是由複晶矽導電層組成，控制·閘 極68則位於漂浮閘極64之上，其間並以一絕緣層66隔 離，例如一氧化矽層/氮化矽層/氧化矽層（ΟΝΟ)。 此外，端子61係用以提供源極電壓Vs與源極區52， 端子63係提供閘極電壓VG予控制閘極68，端子65係提 供汲極電壓VD予汲極區54，端子67則透過一 p+型摻雜 區以提供基底電壓VP.Sub予基底50。 請參閱第5b圖，其顯示一依據第5a圖之漂浮閘極記 憶單元5所實施之程式化步驟，而提供不同電壓予源極 區52、汲極區54、堆疊閘極60及基底50之波形時序圖， 當對漂浮閘極記憶單元5進行程式化時，係對控制閘極 68及汲極區54施加較源極區52為高的電壓，例如藉由 端子63提供相對較高閘極電壓脈衝VG=10.5V予控制閘 極68，且藉由端子65提供相對次高汲極電壓脈衝Vd=6V 予汲極區54，端子61則予以接地以提供相對較低源極 電壓Vs=0V予源極區52，端子67 —般於程式化時則均 予以接地，以提供相對較低基底電壓VP_Sub=0V予基底 50。如前所述，由高閘極電壓脈衝VG=10.5V形成之高電 場，將使在通道區56接近汲極區54處產生高能之熱電 子，進而，使熱電子加速越過上述隧穿氧化物層62並注 入（injection)至上述漂浮閘極64。 由於漂浮閘極64周圍均由絕緣層如62、66所包 圍，故熱電子注入至上述漂浮閘極64後，便陷入其中而 無法脫離，在負電荷（一）儲存於漂浮閘極64之情況下， 11 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ! I I I I I 裝— — I I I I 訂....I I I —線 ί i (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作社印製 A7 ____B7_ 五、發明説明（1〇 ) 其臨限值（threshold)約提高3至5V，結果，當欲對此漂Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 B7 V. Description of the invention (5) Bottom ground; and then provide a second relatively high voltage to the substrate, and at the same time provide a second relatively low voltage to the control gate. According to the present invention, when a substrate on which the floating gate memory device is located is grounded at the same time, a drain region of the floating gate memory device is simultaneously in a floating state. In addition, according to the present invention, when a second relatively low voltage is provided to the control gate, the drain region and the source region are simultaneously in a floating state. According to the present invention, the first relatively high voltage providing the source region is about 0.5V to about Vcc, preferably about 5V. According to the present invention, the first relatively low voltage providing the control gate is about -6 ~ -15V, preferably about -10V. According to the present invention, the second relatively high voltage providing the substrate is about 0.5V to about Vcc, preferably about 5V »Wherein according to the present invention, the second relatively low voltage providing the control gate is about -6 ~ -15V, preferably about -10V. Another object of the present invention is to provide a method for erasing a floating gate memory device, wherein the floating gate memory device includes a first type source region and a first type drain region, both of which are formed in a second In the semi-conducting Zhao region, a channel region extends from the source region to the drain region, a floating gate is located on the channel region, and a control gate is located on the floating gate, which includes the following steps: Firstly, a first relatively high voltage pulse is provided to the source region; at the same time, a first relatively low voltage is provided to the control gate; at the same time, the semiconductor region is grounded; at the same time, the drain region is in a floating state; then a The second relatively low voltage pulse is given to the control gate; the same paper size applies to the Chinese National Standard (CNS) A4 specification (210X 297mm) ---------- ^ ------, tT ------ 0--YiLu (please read the precautions on the back before filling in this page) A7 B7 is printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. A description of the invention (6) provides a second relative High voltage pulses to the semiconductor region; and at the same time the drain and source regions "Floating state" Another object of the present invention is to provide a flash-type electrically erasable and programmable read-only memory device erasing method, including a first erasing stage and a second erasing stage, wherein, The first erasing stage includes: providing a voltage pulse of about 5V to a source region of the read-only memory device, and simultaneously providing a voltage pulse of about -10V to the control gate, and simultaneously reading the read-only memory One of the substrates where the device is located is grounded, and at the same time one of the drain regions of the read-only memory device is in a floating state; and the second erasing stage includes: providing a voltage pulse of about 5V to the substrate, while providing a about -10V The left and right voltage pulses are given to the control gate, and at the same time, the drain region and the source region are in a floating state. According to the present invention, the first erasing stage lasts about 50 msec. In addition, the second erasing phase lasts about 50msec. Hereinafter, an embodiment of the method for erasing and programming the floating gate memory device of the present invention will be described with reference to the drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a conventional flash EEPROM cell; FIG. 2a is a schematic diagram of a conventional flash EEPROM cell according to FIG. 1, which implements conventional programming steps; FIG. 2b is a display 1. According to the traditional programming steps in Figure 2a, provide different voltages to the source region, drain region, gate and substrate waveform timing QE) · Garden, Figure 3a shows a conventional flash according to Figure 1 The standard of EEPROM single paper is in accordance with Chinese National Standard (CNS) Α4 specification (210Χ297mm)-^ ------ lsτ ----- (please read the precautions on the back before filling this page) A7- ---------____ ^ __ V. Description of the invention (7) Yuan's schematic diagram of implementing traditional erasing steps; Figure 3b shows a ^ traditional erasing step according to Figure 3a, providing different voltages to the source Waveform timing circle of the region, drain region, gate and substrate; circle 4 shows a test chart of the tolerance of the memory cell when the traditional programming / erasing steps are implemented according to Figure 2b and 3b; Figure 5a It shows a floating gate memory cell; Figure 5b shows a floating gate note according to Figure 5a In the programming steps implemented by the unit, the waveform timing diagrams of providing different voltages to the source region, the drain region, the gate and the substrate are shown. Figure 5c shows an implementation of a floating gate memory cell according to Figure 5a. In addition to the step, provide different voltages to the source region, the non-electrode region, the gate and substrate waveform timing diagram; and Figure 5d shows the floating gate memory cell of Figure 5a according to the first erasing stage of Figure 5c Cross-sectional view after erasing; Figure 5e shows the cross-sectional view of the floating gate memory unit of Figure 5a after erasing according to the second erasing stage of Figure 5c; and Beigong Consumer Cooperative of the Ministry of Economic Affairs Printed ί ·-m # ^ mn v ^ m-. (Please read the precautions on the back before filling in this page) Figure 6 shows a floating gate memory cell based on the 5th circle to implement the present invention program / wipe Except for the steps, the test chart of the tolerance of the floating gate memory cell "[Symbol Explanation] 1,5 ~ Memory cell-10,50 ~ Semiconductor substrate 12 (13,15), 52 (53,55) ~ Double diffusion source Area 14, 54 ~ Jiji area This paper scale is applicable to China National Standards (CNS & g t; A4 said grid (210X297 mm) 〇346〇ι Α7 Β7 Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (8) 16, 56 ~ channel area 20, 60 ~ stack gate 22, 62 ~ Tunneling oxide layer 24, -64 ~ floating gate 26, 66 ~ inter-gate dielectric layer 28 embodiment, 6 8 ~ control gate please refer to FIG. 5a, which shows a floating gate memory cell 5, A schematic diagram of implementing the erasing steps of the present invention. The floating gate memory unit 5 is generally a flash memory unit, such as electrically erasable and programmable read-only memory (EEPROMs), which includes a semiconductor region 50 and a stack gate极 60. The above-mentioned semiconductor region 50 is generally a P-type substrate, or a P-type substrate with a P-type well and separated by an N-type well (if this structure is used, the following substrate voltage VP_Sub refers to the P-type well voltage ). In addition, a double-diffused n-type source region 52 and an n + type drain region 54 are respectively implanted into a predetermined position on the substrate, and a channel region 56 is formed between the source region 52 and the drain region 54 at the same time. Among them, the double-diffused n-type source region 52 includes an n-doped region 55 with a deep diffusion depth but light doping, and an n + doped region 53 with a shallow diffusion depth but strong doping. Secondly, the stacked gate 60 is formed on the channel region 56 between the source region 52 and the drain region 54 of the semiconductor substrate 50, and the stacked gate 60 is a tunnel oxide layer 62 in sequence. A floating gate 64, an inter-gate dielectric layer 66 and a control gate 68, the tunnel oxide layer 62 is between the surface of the substrate 50 and the floating gate 64, and its thickness is suitable for the country of China relative to the paper size Standard (CNS) Α4 wash grid (210X297mm) I ------- 一-^ ----------- ^ (Please read the precautions on the back before filling this page) Economy Printed by the Ministry of Standards and Staff's Consumer Cooperative of the Ministry of Standards A7 B7 V. Invention description (9) is thin, the floating gate 64 is mainly composed of a polycrystalline silicon conductive layer, and the control gate 68 is located above the floating gate 64, And separated by an insulating layer 66, such as a silicon monoxide layer / silicon nitride layer / silicon oxide layer (ΟΝΟ). In addition, the terminal 61 is used to provide the source voltage Vs and the source region 52, the terminal 63 is used to provide the gate voltage VG to the control gate 68, the terminal 65 is used to provide the drain voltage VD to the drain region 54, and the terminal 67 is passed through A p + -type doped region provides the substrate voltage VP.Sub to the substrate 50. Please refer to FIG. 5b, which shows a programming step implemented according to the floating gate memory unit 5 of FIG. 5a to provide different voltages to the source region 52, the drain region 54, the stacked gate 60, and the substrate 50 Waveform timing diagram, when the floating gate memory unit 5 is programmed, a higher voltage is applied to the control gate 68 and the drain region 54 than the source region 52, for example, a relatively higher gate is provided by the terminal 63 The voltage pulse VG = 10.5V is provided to the control gate 68, and a relatively high drain voltage pulse Vd = 6V is provided to the drain region 54 through the terminal 65, and the terminal 61 is grounded to provide a relatively low source voltage Vs = 0V The source region 52 and the terminal 67 are generally grounded during programming to provide a relatively low base voltage VP_Sub = 0V to the base 50. As mentioned above, the high electric field formed by the high gate voltage pulse VG = 10.5V will cause high-energy hot electrons to be generated in the channel region 56 close to the drain region 54 and further accelerate the hot electrons across the tunneling oxide Layer 62 is also injected into the floating gate 64 described above. Since the floating gate 64 is surrounded by insulating layers such as 62 and 66, the hot electrons are injected into the floating gate 64 and fall into it without being detached. In the case where negative charges (1) are stored in the floating gate 64 Next, the 11 paper scales are applicable to the Chinese National Standard (CNS) A4 specification (210X297mm)! IIIII Packing — IIII Order .... III — Line i (Please read the precautions on the back before filling this page) Economy A7 ____B7_ printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Education. 5. Description of the invention (1〇) The threshold is increased by about 3 to 5V.
浮閘極記憶單元5讀取資料而將控制閘極68加壓至5V 時’通道並未導通，故讀取資料為（1)，亦即上述漂浮閘 極記憶單《元5已被程式化，至於一般程式化時間則約 lOpsec 左右。 同樣不可避免的，在上述程式化期間，如第5a圖所 示，當記憶單元5重新程式化一既定次數如10,〇〇〇次後， 將在接近汲極54處引發（induced)電子捕獲現象，使負電 荷陷於隧穿氧化層62，然而上述現象，將在後續實施本 發明抹除步驟後得到相當的改善效果。 請參閱第5c圖，其顯示一依據第5a囷之漂浮閘極記 憶單元所實施之抹除步驟，並提供不同電壓予源極區、 汲極區、閘極及基底之波形時序圖。當對記憶單元5進 行抹除（erase)時，其主要係分成兩階段進行，現分述如 下。 請參閱第5d圖及第5c圖之第一抹除階段E1，期間 約為5〜100msec，較佳者為50msec，其係採源極抹除方 式’亦即首先為對源極區52施加較控制閘極68為高的 電壓’例如藉由端子61提供相對較高源極電壓脈衝 VS=5V予源極區52 ’藉由端子63提供相對較低閘極電 壓VG=-10V予控制閘極68，端子67則予以接地，以提 供基底電壓VP-Sub=〇V予基底50 ’至於汲極區54之没極 電壓Vd則藉端子65使之處於漂浮狀態f(fl〇ating)。如此 在漂浮閘極64與源極區52之間會形成一橫越随穿氧化 12 本紙張尺度適用中國國家揉準（CNS ) A4規格（2丨0 X 297公釐） —— -- --------^—^------1T------· (請先聞讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（11 ) 物層62之高電場，使陷於漂浮閘極64之負電荷（一）朝相 對源極區52之位置聚集，進而藉由Fowler-Nordheim(F-N)隧道效應，使漂浮閘極64内之部份負電荷（一)被吸出 (extracted)至源極區 52。 同理，由於在源極52與隧穿氧化物層62之間引發 電洞捕獲現象，使正電荷陷於隧穿氧化物層62，因此短 期内加速了漂浮閘極64内熱電子之流出，但隨之在陷於 隧穿氧化物層62之電洞的持續吸引下，使愈來愈多之負 電荷被引出而陷於隧穿氧化物層62，阻擋了熱電子的流 出，並減緩抹除速度。然而前述現象在進行本實施例之 後續的第二抹除階段E2時，將可消除陷於隧穿氧化物層 62之電洞，因此不會發生愈來愈多之負電荷被吸引而陷 於隧穿氧化物層62的現象，如以下所述。 請參閱第5e圖及第5c圖之第二抹除階段E2，期間 約為5〜100msec，較佳者為50msec，其係採通道抹除方 式，亦即首先為對基底50施加較控制閘極68為高的電 壓，例如藉由端子67提供相對較高基底電壓脈衝VP. Sub=5V予基底50，端子63則提供相對較低閘極電壓脈 衝VG=-10V予控制閘極68，至於汲極區54之汲極電壓 VD和源極區52之源極電壓Vs則藉端子65、61使之處 於漂浮狀態f(floating)。如此在漂浮閘極64與通道區56 之間會形成一橫越隧穿氧化物層62之高電場，使陷於漂 浮閘極64之負電荷（一）朝相對通道區56之位置聚集，進 而藉由Fowler-Nordheim(F-N)随道效應，使漂浮閘極64 13 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） n 裝 i 線 i i (請先聞讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（12 ) 内之剩餘負電荷（一）被吸出（extracted)至通道區56。 同時，原先在程式化期間，陷於隧穿氧化層62之負 電荷，也會因上述漂浮閘極64與通道區56之間形成的 高電場而-被吸出，消除阻擋熱電子注入的現象。 此外，在第一抹除階段E1 ，陷於隧穿氧化物層62 之正電荷（電洞）也被控制閘極68之負電壓（VG=-10V)吸 入漂浮閘極64，因此不會發生在重複進行多次程式抹除 動作時，使愈來愈多之負電荷被吸引而陷於隧穿氧化物 層62的_現象。 上述本發明之漂浮閘極記憶裝置之抹除/程式及讀 取之操作範圍，係約如表一所示。 表一 程式化 源極抹除Ε1 通道抹除E2 讀取 控制閘極 8-15V -6—15V -6V 〜-15V Vcc 汲極 3〜6V Floating Floating 1〜2V 源極 0V 0.5V 〜Vcc Floating ον 基底 0V 0V 0.5V 〜Vcc ον 熱載子注入 FN隧道效應 其中Vcc表一系統電源電壓，例如目前使用之電源 約為3-5V。 請參閱第6圖，其顯示一依據第5b圖之漂浮閘極記 憶單元實施本發明程式化/抹除步驟時，漂浮閘極記憶單 元容忍度之測試圖，由此圖可知，記憶單元之程式/抹除 循環次數均維持在一既定臨限電壓Vth下超過100,000 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） ---------裝------訂-----『線 - - (請先閲讀背面之注意事項再填寫本頁) Β7 五、發明説明（13 ) 次，亦即在程式化期間，臨限電壓Vth維持在6〜7 V左右， 在抹除期間，臨限電壓Vth維持在1〜2V左右，兩者並未 發生靠近現象（close)，如表二所示，其係顯示以傳統抹 除方法及本實施例之抹除方法中，其程式/抹除循環之臨 限電壓Vth的靠近比率（close ratio)，依據表二，本實施 例於程式/抹除循環100,000次後之靠近比率僅6%，因此 整個記憶陣列在程式/抹除操作期間不易發生失誤。換言 之，依據本發明之抹除（erase)及程式（program)操作方 法，其容忍度，即陣列中之記憶單元能重新程式/抹除的 次數，將不少於100,000次。 (請先閲讀背面之注意事項再填寫本頁) •澤· 表二 初始程式/抹除 臨限電壓差 最末之程式/抹除臨 限電壓差 靠近比率％ 傳統抹除 5.14V 1.19V(20K 次） 76.8% 本實施例 5.06V 4.75V(100K 次） 6% 、νβ Γ 經濟部中央標準局員工消費合作社印製 雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明，例如，本發明中所應用之記憶結構，並 不限於實施例所引述者，其能由各種具恰當特性之裝置 所置換，且本發明抹除方法亦不限於實施例引用之電壓 大小。因此，任何熟習此項技藝者，在不脫離本發明之 精神和範圍内，當可對其作更動與潤飾，故本發明之保 護範圍係視後附之申請專利範圍界定者為準。 15 本紙張尺度適用中國國家標準（CNS ) A4规格（210 X 297公釐）When the floating gate memory unit 5 reads data and presses the control gate 68 to 5V, the channel is not connected, so the read data is (1), that is, the floating gate memory unit "Element 5 has been programmed As for the general programming time, it is about 10Opsec. It is also inevitable that during the above programming, as shown in Figure 5a, when the memory unit 5 is reprogrammed a predetermined number of times, such as 10,000 times, it will induce electron capture near the drain 54 This phenomenon causes the negative charge to trap in the tunnel oxide layer 62. However, the above phenomenon will have a considerable improvement effect after the erasing step of the present invention is implemented later. Please refer to Fig. 5c, which shows an erasing step implemented according to the floating gate memory unit of Fig. 5a, and provides waveform timing diagrams of different voltages for the source region, the drain region, the gate and the substrate. When erasing the memory unit 5, it is mainly divided into two stages, which are described below. Please refer to the first erasing stage E1 in FIG. 5d and FIG. 5c, the period is about 5 ~ 100msec, preferably 50msec, which adopts the source erasing method. The control gate 68 is at a high voltage. For example, the terminal 61 provides a relatively high source voltage pulse VS = 5V to the source region 52. The terminal 63 provides a relatively low gate voltage VG = -10V to the control gate. 68, the terminal 67 is grounded to provide the substrate voltage VP-Sub = 0V to the substrate 50 '. The terminal voltage Vd of the drain region 54 is brought into a floating state f (fl〇ating) by the terminal 65. In this way, a cross-over oxide will be formed between the floating gate 64 and the source region 52. This paper size is applicable to China National Standard (CNS) A4 (2 丨 0 X 297 mm) ——-- ------ ^ — ^ ------ 1T ------ · (Please read the precautions on the back first and then fill out this page) A7 B7 printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 1. Description of the invention (11) The high electric field of the object layer 62 causes the negative charge trapped in the floating gate 64 (1) to accumulate toward the position of the relative source region 52, and the Fowler-Nordheim (FN) tunnel effect is used to Part of the negative charge (1) in the pole 64 is extracted to the source region 52. Similarly, since the hole trapping phenomenon is induced between the source 52 and the tunnel oxide layer 62, the positive charge is trapped in the tunnel oxide layer 62, so the outflow of hot electrons in the floating gate 64 is accelerated in a short time, but With the continuous attraction of the holes trapped in the tunnel oxide layer 62, more and more negative charges are drawn out and trapped in the tunnel oxide layer 62, blocking the outflow of hot electrons and slowing the erasing speed. However, the aforementioned phenomenon will eliminate the holes trapped in the tunnel oxide layer 62 during the subsequent second erasing phase E2 of this embodiment, so that more and more negative charges will not be attracted and trapped in the tunnel The phenomenon of the oxide layer 62 is as follows. Please refer to the second erasing phase E2 in FIG. 5e and FIG. 5c, the period is about 5 ~ 100msec, preferably 50msec, which adopts the channel erasing method, that is, firstly applying a more controlled gate to the substrate 50 68 is a high voltage, for example, by providing a relatively high base voltage pulse VP. Sub = 5V to the base 50 through the terminal 67, and a relatively low gate voltage pulse VG = -10V to the control gate 68 at the terminal 63. The drain voltage VD of the pole region 54 and the source voltage Vs of the source region 52 are brought into a floating state f (floating) via the terminals 65 and 61. In this way, a high electric field across the tunnel oxide layer 62 will be formed between the floating gate 64 and the channel region 56, so that the negative charge (1) trapped in the floating gate 64 will gather toward the position opposite to the channel region 56, and then By the Fowler-Nordheim (FN) follow-up effect, the floating gate is 64 13 This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) n Install i line ii (please read the precautions on the back before filling in This page) A7 B7 printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. The remaining negative charge (1) in the description of the invention (12) is extracted to the passage area 56. At the same time, the negative charge trapped in the tunnel oxide layer 62 during the programming process will also be drawn out due to the high electric field formed between the floating gate 64 and the channel region 56 to eliminate the phenomenon of blocking hot electron injection. In addition, in the first erasing phase E1, the positive charge (hole) trapped in the tunnel oxide layer 62 is also drawn into the floating gate 64 by the negative voltage (VG = -10V) of the control gate 68, so it will not occur in When the program erasing operation is repeated several times, more and more negative charges are attracted and trapped in the tunnel oxide layer 62. The operation range of the erasing / programming and reading of the floating gate memory device of the present invention is shown in Table 1. Table 1 Programmable source erase E1 channel erase E2 read control gate 8-15V -6—15V -6V ~ -15V Vcc Drain 3 ~ 6V Floating Floating 1 ~ 2V source 0V 0.5V ~ Vcc Floating ον Substrate 0V 0V 0.5V ~ Vcc ον Hot carrier injection FN tunnel effect where Vcc represents a system power supply voltage, for example, the currently used power supply is about 3-5V. Please refer to FIG. 6, which shows a test chart of the tolerance of the floating gate memory unit when implementing the programming / erasing steps of the present invention according to the floating gate memory unit of FIG. 5b. From this figure, the program of the memory unit / Erase cycle times are maintained at a predetermined threshold voltage Vth exceeding 100,000. The paper standard is applicable to the Chinese National Standard (CNS) Α4 specification (210X297mm) --------- installed ------ Order ----- "Line--(Please read the precautions on the back before filling out this page) Β7 5. Invention description (13) times, that is, during programming, the threshold voltage Vth is maintained at 6 ~ 7 V In the erasing period, the threshold voltage Vth is maintained at about 1 ~ 2V, and there is no close phenomenon between the two. As shown in Table 2, it shows that the traditional erasing method and the embodiment of the erasing In the method, the close ratio of the threshold voltage Vth of the program / erase cycle is only 6% according to Table 2 in this embodiment after 100,000 program / erase cycles, so the entire memory array is Errors are not likely to occur during the program / erase operation. In other words, according to the erase and program operation methods of the present invention, the tolerance, that is, the number of times the memory cells in the array can be reprogrammed / erased, will not be less than 100,000. (Please read the precautions on the back before filling in this page) • Ze · Table 2 Initial program / last program of erasure threshold voltage difference / erasure threshold voltage difference close ratio% Traditional erasure 5.14V 1.19V (20K Times) 76.8% This embodiment is 5.06V 4.75V (100K times) 6%, νβ Γ Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economics Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the invention For example, the memory structure used in the present invention is not limited to those cited in the embodiments, and can be replaced by various devices with appropriate characteristics, and the erasing method of the present invention is not limited to the voltage levels cited in the embodiments. Therefore, anyone who is familiar with this skill can modify and retouch it without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention is subject to the definition of the scope of the attached patent application. 15 This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm)