TW432651B - Continuous wire bonding structure and method - Google Patents

Continuous wire bonding structure and method Download PDF

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Publication number
TW432651B
TW432651B TW88117632A TW88117632A TW432651B TW 432651 B TW432651 B TW 432651B TW 88117632 A TW88117632 A TW 88117632A TW 88117632 A TW88117632 A TW 88117632A TW 432651 B TW432651 B TW 432651B
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TW
Taiwan
Prior art keywords
solder joint
wire
line segment
scope
patent application
Prior art date
Application number
TW88117632A
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Chinese (zh)
Inventor
Yu-Fang Tsai
Su Tao
Original Assignee
Advanced Semiconductor Eng
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Priority to TW88117632A priority Critical patent/TW432651B/en
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Publication of TW432651B publication Critical patent/TW432651B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Wire Bonding (AREA)

Abstract

A continuous wire bonding structure is provided. The wire comprise a first welding point, a first segment, a second welding point, a second segment and a third welding point. The first segment is connected between the first welding point and the second welding point. The second segment is connected between the second welding point and the third welding point. The first segment is connected to the second segment through the second welding point to form the wire. The first segment and the second segment comprises suitable curvatures respectively to prevent too close condition between the end of the first segment and the start of the first segment around the second welding point from resulting in the unnecessary contact for the end of the first segment and the first segment with each other. A continuous wire bonding method includes: after a wire bonding with a first welding point, moving toward a second welding point for bonding so that the wire will form a first segment with suitable curvature at the first and the second welding points; after a wire bonding with a second welding point, moving toward the third welding point for bonding so that the wire will form a second segment with suitable curvature at the second and the third welding points.

Description

4 32 6 5 五、發明說明（1) 【發明領域】 右ί 5::ί關於一種導線連續打線構造及方*，特別是 f綠 土 三個以上的焊墊上連續打線.形成的導線構造 及打綠万法。 【先前技術】 以導二電性連；：：^:件〔如：“、導線架等〕之間 κ ^ β 成通路。該積體電路元件之數個晶片則 〇 Γ ，體 '〔stacked die〕或複晶模組〔multi-chip 7 J ί構造。在堆叠體之上晶片打線必須延伸跨過下 晶片並5亥導線與下s y说4士 . /興卜θ曰片保持一適當距離以避免該導線碰觸 該下晶片而受指g尤你a 谓 在複阳杈組之一部分功能相同的焊墊往 相：的接腳進行打線1而不須要另設置接腳，進而減少 δ玄複晶模組需要的接腳數量。 於1991年4月30日頒予梵伍德（Farnw〇rth)之美國專利第 5, Ο/2’ 323號揭示一積體電路晶片堆疊體，如第&及二^ 所示 導線架1 0 0上方黏貼一上晶片丨I 〇及其下方黏貼一 下晶片1 2 0以形成一晶片堆疊體。該上晶片^ i 〇及下晶片 120分別設有數個第一焊墊丨n及數個第二焊墊121。該導 線架1〇〇設有數個第一内接腳101及數個第二内接腳1〇2。 該第一内接腳1 0 1位於該第一焊墊丨i丨及第二焊墊丨2丨並往 該堆疊體兩側延伸形成相對應的數個第一外接腳丨〇 3。該 第二内接腳1 〇2位於該第一焊，ηι及第二焊墊12ι之附近 並往遠堆疊體兩端延伸形成相對應的數個第二外接腳 104。該上晶片110及下晶片120之功能相同的第一焊塾hi4 32 6 5 V. Description of the invention (1) [Field of invention] Right ί 5 :: ί Concerning a continuous wire structure and a square wire, especially continuous wire on three or more pads of f green clay. The structure of the wire and Fight green. [Prior art] Connected by two electric conductors :: ^: pieces [such as ", lead frame, etc." to form a path between κ ^ β. Several chips of the integrated circuit element are Γ, body '[stacked die] or multi-chip module [multi-chip 7 J ί structure. The chip wire on the stack must extend across the lower chip and the 5 wire and the lower sy say 4 shi. To prevent the wire from touching the lower chip and being criticized, especially if you say that the pads with the same function in one part of the Fuyang branch group are connected to the pins: 1 does not need to be set separately, thereby reducing δ The number of pins required for a polycrystalline module. US Patent No. 5, 0/2 '323, issued to Farnworth on April 30, 1991, discloses an integrated circuit chip stack, such as No. & And two ^ shown above the lead frame 100 is pasted an upper chip 丨 I 0 and a lower chip 1200 is pasted to form a wafer stack. The upper wafer ^ i 〇 and the lower wafer 120 are respectively provided with a plurality of first wafers. A solder pad 丨 n and a plurality of second solder pads 121. The lead frame 100 is provided with a plurality of first inner pins 101 and a plurality of second inner pads. The first internal pin 1 0 1 is located on the first pad 丨 i 丨 and the second pad 丨 2 丨 and extends to both sides of the stack to form corresponding first external pins.丨 〇3. The second internal pin 1 〇2 is located near the first solder, η and the second solder pad 12ι, and extends to two ends of the far stack to form corresponding second external pins 104. The upper The first bonding pad hi having the same function as the wafer 110 and the lower wafer 120

C:\Program Files\patent\PK6965.ptd 第5頁 Γ 1432651 五、發明說明（2) ~ -- 及第二焊墊1 2 i以導線i 3 〇共同電性連接至相對應的第一内 接腳101或第二内接腳102。然而，將該上晶片“ο及下日 片12〇之功能相同的第-料⑴及第：料⑵以導線^曰 共同電性連接至相對應的第一内接腳1〇1或第二内接 時，該第5, 0 1 2, 32 3號主要將共同連接於内接腳的導線“ο 分別 進行打線，在同一内接腳的焊墊上打線二次， 該第5，0 1 2 ’ 3 2 3號具有增加打線次數及打線時間之缺點。 由於後打線撞擊容易影響前打線的品質，因而使該第 5，0 1 2，3 2 3號具有打線品質〔b〇ndab i 1 i ty〕及產品可靠卢 〔reliability〕。 又 有鑑於此，本發明改良以上缺點，將需要打線二次的導 線構造以連續打線的導線構造替代，使本發明半導體元件 的打線次數降低及提高該半導體元件的打線品質及產品可 靠度。 【發明概要】 t 本發明之主要目的係提供—種導線連續打線構造及方 法’其半導體元件之數個焊墊以連續打線形成導線構造， 使本發明半導體元件的打線次數降低及提高該半導體元件 的打線品質及產品可靠度。 根據本發明之導線連續打線構造，該導線包含一第一焊 點、一第一線段、一第二焊點、一第二線段及—第三焊 點。該第一線段位於該第一焊點及第二焊點之間，而該第 二線段位於該第二焊點及第三焊點之間，該第—線段經由 第二焊點連接至第二線段而形成該導線。該第—線段及第C: \ Program Files \ patent \ PK6965.ptd Page 5 Γ 1432651 V. Description of the Invention (2) ~-and the second pad 1 2 i are electrically connected to the corresponding first inner portion with a wire i 3 〇 Pin 101 or second inner pin 102. However, the first material and the second material having the same function as the upper chip "ο and the next day film 120" are electrically connected to the corresponding first internal pins 101 or 2 with wires ^. In the case of internal connection, the No. 5, 0 1 2, 32 3 mainly wire the wires commonly connected to the internal pins "ο, respectively, and wire twice on the pads of the same internal pin, the No. 5, 0 1 2 '3 2 No. 3 has the disadvantages of increasing the number of times and time. Because the impact of the rear wire is easy to affect the quality of the front wire, the No. 5, 0 1 2, 3 2 3 has the wire quality [b〇ndab i 1 i ty] and the reliability of the product [reliability]. In view of this, the present invention improves the above disadvantages, and replaces the wire structure that needs to be wired twice with a wire structure that is continuously wired, so that the number of times of wiring of the semiconductor element of the present invention is reduced and the quality and reliability of the wiring of the semiconductor element are improved. [Summary of the invention] The main purpose of the present invention is to provide a continuous wire bonding structure and method. The bonding pads of a semiconductor element are formed by continuous wire bonding, so that the number of times of wiring of the semiconductor element of the present invention is reduced and the semiconductor element is improved. Wire quality and product reliability. According to the continuous wire bonding structure of the present invention, the wire includes a first solder joint, a first wire segment, a second solder joint, a second wire segment, and a third solder joint. The first line segment is located between the first and second solder joints, and the second line segment is located between the second and third solder joints. The first line segment is connected to the first solder joint via the second solder joint. The two wires form the wire.该 第 — 线段 和 第 The line segment and the

C:\Program Fi lcb\pateiu\PK6965.ptd 第6頁 143265 1 五、發明說明（3) 二線段分別具有適當弧度以避免在第二焊點附近該第一線 段末端與第二線段起端過於接近而導致該第一線段末端與 第二線段起端之間產生不必要的相立碰觸。 根據本發明之導線連續打線方法，該導線連續打線方法 包含步驟如下：一導線打線連接於/第一焊點後往一第二 焊點移動進行打線，使該導線在該第一焊點及第二焊點形 成具有適當弧度的一第一線段；該導線打線連接於第二焊 點後往一第三焊點移動進行打線，使該導線在該第二焊點 及第二焊點形成具有適當弧度的一第二線段。 【圖式說明】 為讓本發明之上述和其他目的、特徵、和優點能更明顯 易懂’下文特舉本發明之較佳實施例，並配合所附圖式， 作詳細說明如下： .第1圖·習用美國專利第5, 0 1 2, 3 23號半導體元件、之上 視圖； 第2圖：習用美國專利第5, 0 1 2, 3 23號半導體元件第1 圖沿2 — 2線剖視圖； 、第3圖’本發明第一較佳實施例導線連續打線構造之側 ^ 4圖:本發明第二較佳實施例球塾之側視圖； 5 =·本1¾明第二較佳實施例導線連續打線構造之側 圓，及 f 6圖本發明第二較佳實施例導線連續打線構造之側C: \ Program Fi lcb \ pateiu \ PK6965.ptd Page 6 143265 1 V. Description of the invention (3) The two line segments have appropriate radians respectively to avoid the end of the first line segment and the start of the second line segment near the second welding point. Too close results in unnecessary opposing contact between the end of the first line segment and the beginning of the second line segment. According to the continuous wire bonding method of the present invention, the continuous wire bonding method includes the following steps: a wire is connected to the / first solder joint and moved to a second solder joint to wire, so that the wire is connected to the first solder joint and the first solder joint; The two solder joints form a first line segment with an appropriate radian; the wire is connected to the second solder joint and moved to a third solder joint for wiring, so that the wire is formed at the second solder joint and the second solder joint. A second line segment of appropriate radians. [Illustration of the drawings] In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiments of the present invention and the accompanying drawings in detail, as follows: Figure 1 · Conventional US Patent No. 5, 0 1 2, 3 23, top view; Figure 2: Conventional US Patent No. 5, 0 1 2, 3 23, semiconductor device. Figure 1 along line 2-2 Sectional view; Figure 3 'Side side of the first preferred embodiment of the present invention continuous wire structure ^ 4 Figure: Side view of the second preferred embodiment of the ball of the present invention; Example: The side circle of a wire continuous wire structure, and f6 Figure 2. The side of the wire continuous wire structure of a second preferred embodiment of the present invention

C:\Program Files\patent\PK6965.ptd f 1432651C: \ Program Files \ patent \ PK6965.ptd f 1432651

五 '發明說明（4) 圖號 說 明 ] 100 導 線 架 101 第 一 内 接 102 第 '— 内 接腳 103 第 * 外 接 104 第 二 外 接腳 110 上 晶 片 111 焊 塾 120 下 晶 片 121 焊 墊 130 導 線 200 第 一 晶 片 201 第 一 焊 點 202 第 一 凸 球 203 第 — 線 段 210 接 腳 211 第 二 焊 點 220 第 二 晶 片 221 第 -·~一 焊 點 222 第 二 凸 球 223 第 二 線 段 300 第 一 晶 301 第 一 焊 點 302 第 一 凸 球 310 接 腳 311 第 二 焊 點 312 第 二 凸 球 313 平 頂 320 第 — 晶 321 第 二 焊 點 322 第 二 凸 球 400 第 一 晶 片 401 第 一 焊 點 402 第 一 凸 球 410 第 二 晶 片 411 第 — 焊 點 412 第 凸 球 413 平 頂 420 接 腳 421 第 — 焊 點 發明 說 明Five 'invention description (4) Drawing number description] 100 lead frame 101 first internal connection 102 first'—internal pin 103 first * external 104 second external pin 110 upper chip 111 solder pad 120 lower chip 121 solder pad 130 wire 200 The first wafer 201, the first solder joint 202, the first bump 203, the first-line segment 210, the pin 211, the second solder joint 220, the second wafer 221, the first solder joint 222, the second bump 223, the second line segment 300, and the first crystal. 301 first solder joint 302 first bump 310 pin 311 second solder joint 312 second bump 313 flat top 320 first — crystal 321 second solder joint 322 second bump 400 first wafer 401 first solder joint 402 First convex ball 410 Second wafer 411 No. — solder joint 412 No. convex ball 413 Flat top 420 Pin 421 No. — solder joint invention description

C:\Program Files\patent\PK6965.ptd 第8頁C: \ Program Files \ patent \ PK6965.ptd Page 8

「_43265 -J ____ _ 五、發明說明（5) 本發明主要將半導體元件之數個焊墊以連續打線形成導 線構造’使本發明半導體元件的打線次數降低及提高該半 導體元件的打線品質及產品可靠度，其在三個以上的焊墊 上連續打線开；> 成導線。本發明之導線至少包含一第一線 段、一焊點及一第二線段’該焊點連接該第一線段及第二 線段。 凊參照第二圖所示’本發明第一較佳實施例之一第一晶 >1 200上設有一第一焊點201，該第—焊點2〇ί上則設有一 第一凸球2 0 2供打線。一第二晶片2 2 〇上設有一第三焊點 221 ’該第三烊點221上則設有一第二凸球222供打線。該 第一晶片200及第二晶片220之間設有一接腳21〇，該接腳 2 1 0上設有一第二焊點21 1 ’因此，該第二焊點2 11位於該 第一焊點201及第三焊點221之間。一導線之第一線段2 03 連接於該第一焊點2 〇 1及第二焊點2 1 1之間，而該導線之第 二線段2 2 3連接於該第二焊點211及第三焊點2 2 1夺間_，因 而該導線從該第一焊點2 〇 1經第一線段2 〇 3、第二丨H.2J 1 及第二線段2 23電性連接至該第三焊點221形成通路。該導 線之第一線段20 3及第二線段223分別具有適當弧度以避免 在第二焊點211附近該導線之第一線段203末端與第二線段 223起端過於接近，因而導致該第一線段203末端與第二線 段2 2 3起端之間產生不必要的相互碰觸。該導線連續打線 方法包含步驟如下：在一第三焊點221形成一第二凸球 2 2 2 ; —導線打線〔b a 11 b ο n d ]連接於一第一焊點2 〇 1後 往一第二焊點2 1 1移動進行打線，使該導線在該第一焊點"_43265 -J ____ _ V. Description of the invention (5) The present invention mainly uses a plurality of bonding pads of a semiconductor element to form a conductive wire structure in a continuous manner to reduce the number of times the semiconductor element of the present invention is wired and improve the quality and product of the semiconductor element Reliability, which is continuously opened on more than three welding pads; > into a wire. The wire of the present invention includes at least a first line segment, a welding point and a second line segment 'the welding point is connected to the first line segment And the second line segment. 凊 Referring to the second figure, 'a first crystal of the first preferred embodiment of the present invention is provided with a first solder joint 201 on the first crystal, and the first solder joint 20 is provided on the first solder joint 201. There is a first convex ball 202 for wiring. A second wafer 2220 is provided with a third solder joint 221 ', and a third bump 221 is provided with a second bump 222 for wiring. The first wafer 200 A pin 21 is provided between the second chip 220 and the second chip 220, and a second solder joint 21 1 'is provided on the pin 2 10. Therefore, the second solder joint 2 11 is located at the first solder joint 201 and the third solder joint. Between points 221. The first segment 2 03 of a wire is connected to the first solder joint 2 01 and the second solder joint 2 1 1 and the second segment 2 2 3 of the wire is connected to the second solder joint 211 and the third solder joint 2 2 1 夺, so the wire passes from the first solder joint 201 to the first wire Segment 2 〇3, the second 丨 H.2J 1 and the second line segment 2 23 are electrically connected to the third solder joint 221 to form a path. The first line segment 20 3 and the second line segment 223 of the wire have appropriate radians to Avoid that the end of the first line segment 203 of the wire and the start of the second line segment 223 are too close to the second solder joint 211, resulting in unnecessary unnecessary between the end of the first line segment 203 and the start of the second line segment 2 2 The method of continuous wire bonding includes the following steps: forming a second convex ball 2 2 2 at a third solder joint 221;-wire bonding [ba 11 b ο nd] connected to a first solder joint 2 〇 After 1, move to a second solder joint 2 1 1 to wire, so that the wire is at the first solder joint

C:\Program Files\patent\PK6965.ptd 第9頁 P432651C: \ Program Files \ patent \ PK6965.ptd Page 9 P432651

五、發明說明（6) 201及第二焊點211形成具有適當弧度及高度的一第一線段 2 0 3 ;該導線打線〔s t丄t ch b〇nd〕連接於第二焊點2丨丄後 往該第三焊點221往第二凸球2 2 2移動進行打線，使該導線 在該第二焊點211及第三焊點221形成具有適當弧度及高度 的一第二線段223。本發明之導線連續打線方法應用於晶 片200及220共同電性連接於接腳21〇，其打線機台之鋼嘴 〔capi 1 lary〕祇需衝擊該接腳21〇 一次，因而本發明半導 體元件的打線次數降低及提高該半導體元件的打線品質及 產品可靠度。 請再參照第四及五圖所示，本發明第二較佳實施例之一 第一晶片3 0 0上設有一第一焊點3 〇 1，該第一焊點3 〇 1上則 設有一第一 ώ球3 0 2供打線。一第二晶片3 2 0上設^一第三 焊點32 1 ’該第三焊點32 1上則設有一第三凸球3 2 2供打 線。該第一晶片3 0 0及第二晶片3 2 0之間設有一接腳31 0， 該接腳3 10上設有一第二焊點311，該第二焊點311上則設 有一第二凸球31 2供打線，該第二凸球31 2設有一平頂 ϋ 3 1 3 ’該平頂3 1 3具有一長度及一寬度，該長度至少不小於 一距離D ’該距離使該第二凸球3 1 2之平頂31 3延伸於該第 一焊點3 0 1與第三焊點3 2 1之間。此時，該第二焊點3 11位 於該第一焊點301及第三焊點321之間。一導線之第一線段 3 0 3連接於該第一焊點3 〇 1及第二焊點3 11之間，而該導線 之第二線段3 2 3連接於該第二焊點31 1及第三焊點321之 間，當該導線之第一線段3〇 3往第二線段323延伸打線時， 該第二凸球3 1 2之平頂31 3長度沿著該第二焊點3 11及第三V. Description of the invention (6) 201 and the second solder joint 211 form a first line segment 2 0 3 with an appropriate radian and height; the conductor wire (st 丄 t ch b〇nd) is connected to the second solder joint 2 丨After that, the third solder joint 221 is moved to the second convex ball 2 2 2 to wire, so that the wire forms a second line segment 223 with appropriate radian and height at the second solder joint 211 and the third solder joint 221. The continuous wire bonding method of the present invention is applied to the chips 200 and 220 to be electrically connected to the pin 21, and the steel cap [capi 1 lary] of the wire bonding machine only needs to impact the pin 21 once. Therefore, the semiconductor of the present invention The number of bonding times of the device is reduced and the bonding quality and product reliability of the semiconductor device are improved. Please refer to FIG. 4 and FIG. 5 again. According to the second preferred embodiment of the present invention, a first solder joint 300 is provided on the first wafer 300, and a first solder joint 300 is provided on the first wafer 300. The first free ball 3 0 2 is for playing. A second wafer 3 2 0 is provided with a third solder joint 32 1 ′, and a third convex ball 3 2 2 is provided on the third solder joint 32 1 for wiring. A pin 3 10 is provided between the first wafer 300 and the second wafer 3 2 0, a second solder joint 311 is provided on the pin 3 10, and a second bump is disposed on the second solder joint 311. The ball 31 2 is provided for hitting the line, and the second convex ball 3 12 is provided with a flat top 3 1 3 'The flat top 3 1 3 has a length and a width, the length is at least not less than a distance D', the distance makes the second The flat top 31 3 of the convex ball 3 1 2 extends between the first solder joint 3 0 1 and the third solder joint 3 2 1. At this time, the second solder joint 3 11 is located between the first solder joint 301 and the third solder joint 321. A first segment 3 0 3 of a wire is connected between the first solder joint 3 0 1 and a second solder joint 3 11, and a second segment 3 2 3 of the wire is connected to the second solder joint 31 1 and Between the third solder joint 321, when the first wire segment 30 of the wire extends to the second wire segment 323, the flat top 31 3 of the second convex ball 3 1 2 runs along the second solder joint 3 11 and third

C:\Program Files\patent\PK6965.ptd 第10頁 i 43265 1 五、發明說明（7) 焊點321之方向延伸。本發明之導線連續打線方法應用於 複晶模組之晶片3 0 0及3 2 0共同電性連接於接腳3 1 〇，惟該 第二較佳實施例必須將該第二凸球3 1 2先形成於該第二焊 點3 11上。打線機台之鋼嘴〔cap丨丨I ary〕祇需衝擊該接腳 3 1 0 —次，因而本發明半導體元件的打線次數降低及提高 該半導體元件的打線品質及產品可靠度。 請再參照第四及六圖所示’本發明第三較佳實施例之一 第一晶片400及一第二晶片4 1 0相互堆疊形成一堆疊體。該 第一晶片4 0 0上設有一第一焊點4 01，該第一焊點4 〇 1上則 設有一第一凸球4 0 2供打線。該第二晶片4 1 〇上設有一第二 焊點41 1。該堆疊體一側設有一接腳4 2 〇，該接腳4 2 0上設 有一第三烊點42 1供打線。此時，該第二焊點41 1位於該第 一焊點401及第三焊點421之間。一導線之第一線段4〇3連 接於該第一焊點40 1及第二焊點4 11之間，而該導線之第二 線段42 3連接於該第二焊點4 11及第三焊點421之間，當該,一 導線之第一線段4 03往第二線段423延伸打線時，沿著該 二凸球4 1 2之平頂。該第一線段4 〇 3及第二線段4 2 3分別具 有一適當高度’以避免該第一線段4 〇3及第二線段4 23過於 接近s玄弟·一晶片400及苐一晶片41〇之邊緣。本發明之導線 連續打線方法應用於晶片堆疊體之晶片4 〇 〇及4 1 0共同電性 連接於接腳4 2 0，惟該第三較佳實施例必須將該第一凸球 402及第二凸球412先形成於該第—焊點4〇1及第二焊點411 上。該第三較佳實施例尤其將導線從第一晶片4 〇 0經第二 晶片4 1 0之第二焊點4 11電性連接於接腳4 2 0。該晶片堆疊C: \ Program Files \ patent \ PK6965.ptd Page 10 i 43265 1 5. Description of the invention (7) The direction of the solder joint 321 extends. The method for continuously wiring the wires of the present invention is applied to the chips 300 and 3 2 of the multi-crystal module in common and electrically connected to the pins 3 1 0, but the second preferred embodiment must use the second convex ball 3 1 2 is first formed on the second solder joint 3 11. The cap of the wire bonding machine [cap 丨 丨 Iary] only needs to impact the pin 3 10 times, so the number of wire bonding of the semiconductor element of the present invention is reduced and the wire bonding quality and product reliability of the semiconductor element are improved. Please refer to FIG. 4 and FIG. 6 again to illustrate one of the third preferred embodiments of the present invention. The first wafer 400 and a second wafer 4 10 are stacked on each other to form a stacked body. A first solder joint 401 is provided on the first wafer 400, and a first bump 402 is provided on the first solder joint 401 for wire bonding. A second solder joint 41 1 is provided on the second wafer 4 10. A pin 4 2 0 is provided on one side of the stack, and a third pin 42 1 is provided on the pin 4 2 0 for threading. At this time, the second solder joint 41 1 is located between the first solder joint 401 and the third solder joint 421. A first wire segment 403 of a wire is connected between the first solder joint 401 and a second solder joint 4 11, and a second wire segment 423 of the wire is connected to the second solder joint 411 and third Between the solder joints 421, when the first line segment 4 03 of a wire extends to the second line segment 423, a flat top is formed along the two convex balls 4 1 2. The first line segment 4 03 and the second line segment 4 2 3 have a proper height, respectively, to avoid that the first line segment 4 03 and the second line segment 4 23 are too close to the Xuandi · a chip 400 and a chip. 41〇 the edge. The continuous wire bonding method of the present invention is applied to the wafers 400 and 4 10 of the wafer stack in common and electrically connected to the pins 4 2 0, but the third preferred embodiment must use the first convex ball 402 and the first Two convex balls 412 are formed on the first solder joint 401 and the second solder joint 411. In the third preferred embodiment, the wires are electrically connected to the pins 4 2 0 from the first chip 400 through the second solder joint 4 11 of the second chip 4 10. The wafer stack

-P432C5-4 五、發明說明（8) 體内-部分的上晶片導線不直接跨接 近的上晶>ί導線利用遙结.產 、腳而將過於鄰 今u , 彳用導線連續打線方法隔齙拄 V線的水平間距獲得充分的命η ' 使上晶片 產生沖線。 充刀的：間，以避免上晶片導線之間 請再參照第二、三、五及六 323號具有需要較本發明更多打 美:專利第5,。12, 導體元件的打線次數降低，而減少了同一焊點。本發明半 的次數減少，進而本發明提高該半 $點被鋼嘴衝擊 產品可靠度。 _ 件的打線品質及 雖然本發明已以較佳實施例揭示，缺 發明，任何熟習此技藝*，在不脫離：發；；用以限定本 内，當可作各種之更動與修改，因此本，精神和範圍 視後附之申請專利範圍所界定者為準。β之保護範圍當-P432C5-4 V. Explanation of the invention (8) In-vivo-part of the upper chip wire does not directly cross the approaching upper chip > the wire uses telejunction, production, and feet will be too close to the current u, using the wire continuous wire method A sufficient interval η 'is obtained for the horizontal spacing of the V lines to cause punch lines on the upper wafer. Filling the knife: between, to avoid between the wires on the chip, please refer to the second, third, fifth, and sixth No. 323 has more beauty than the present invention: Patent No. 5 ,. 12, The number of wires of the conductor element is reduced, and the same solder joint is reduced. The number of times of the half of the invention is reduced, and the invention further improves the reliability of the half-point hit by the steel nozzle. _ The wire quality of the piece and although the present invention has been disclosed in a preferred embodiment, without the invention, anyone familiar with this skill * will not depart from: hair; used to limit the book, when various changes and modifications can be made, therefore this book The spirit and scope shall be determined by the scope of the attached patent application. β protection range when

C:\Program Files\patent\PK6965.ptd 第12頁C: \ Program Files \ patent \ PK6965.ptd Page 12

Claims (1)

r 14326 5 1 一·"1案號88〗17fi：^_年月日 修正__ 六、申請專利範圍 1、 一種導線連續打線構造，該導線構造包含： —第一焊點，該導線一端打線連接於該第一焊點； 一第二焊點，該導線打線連接於該第二焊點，使該導 線在該第一焊點及第二焊點之間形成一第一線段；及 一第三焊點，該導線打線連接於該第三焊點，使該導 線在該第二焊點及第三焊點之間形成一第二線段； 因而該導線從該第一焊點經第一線段，第二焊點及第 二線段電性連接至該第三焊點形成通路。 2、 依申請專利範圍第1項所述之導線連續打線構造，其 中該第二焊點設有一第二凸球。 3、 依申請專利範圍第2項所述之導線連續打線構造，其 中該凸球設有一平頂，該平頂設有一距離供該導線從 第一線段沿該平頂之距離延伸至第二線段，該平頂之 距離使該凸球之平頂延伸於該第一焊點與第三焊點之 間。 4、 依申請專利範圍第1項所述之導線連續打線構造’其 中該第一焊點及第三焊點分別設有一第一凸球及一第 三凸球。 5、 依申請專利範圍第1項所述之導線連續打線構造’其 中該第一線段及第二線段具有適當弧度以避免在該第 二焊點附近該第一線段末端及第二線段起端過於接 近，因而導致該第一線段末端及第二線段起端產生不 必要的相互碰觸。 6、 依申請專利範圍第1項所述之導線連續打線構造’其r 14326 5 1 1 " 1 case number 88〗 17fi: ^ _ year month day amendment __ six, patent application scope 1, a wire continuous wire structure, the wire structure includes:-the first solder joint, one end of the wire A wire is connected to the first solder joint; a second wire is connected to the second solder joint, so that the wire forms a first line segment between the first solder joint and the second solder joint; and A third solder joint, the wire is connected to the third solder joint, so that the wire forms a second line segment between the second solder joint and the third solder joint; therefore, the wire passes from the first solder joint through the first solder joint A line segment, a second solder joint and a second line segment are electrically connected to the third solder joint to form a via. 2. The wire is continuously wired in accordance with item 1 of the scope of the patent application, wherein the second solder joint is provided with a second convex ball. 3. The wire is continuously wired according to item 2 of the scope of the patent application, wherein the convex ball is provided with a flat top, and the flat top is provided with a distance for the wire to extend from the first line segment along the flat top to the second The distance between the flat tops of the line segment makes the flat top of the convex ball extend between the first solder joint and the third solder joint. 4. According to the wire continuous wiring structure described in item 1 of the scope of the patent application, wherein the first solder joint and the third solder joint are respectively provided with a first convex ball and a third convex ball. 5. According to the wire continuous wiring structure described in item 1 of the scope of the patent application, wherein the first line segment and the second line segment have appropriate radians to avoid the end of the first line segment and the second line segment near the second solder joint. The ends are too close, resulting in unnecessary contact between the end of the first line segment and the beginning of the second line segment. 6. According to the continuous wire structure described in item 1 of the scope of patent application ' 第13頁 r1432651Page 13 r1432651 修正 中該第一焊點位於一第一 腳及該第三焊點位於一第 依申請專利範圍第1項所 中該第一焊點位於一第一 二晶片及該第三焊點位於 依申請專利範圍第7項所 中該第一晶片及第二晶片 接於該第一晶片及第二晶 第二晶片及接腳，因而該 一線段、第二焊點及第二 三焊點。 晶片、該第二焊點位於一接-一晶片。 述之導線連續打線構造，其 日日片、該第二焊點位於一第 —接腳。 述之導線連續打線構造，其 形成堆疊體，該第一線段連 片’而該第二線段連接於該 第一晶片之第一焊點經該第 線段電性連接至該接腳之第 一種導線連續打線方法，該連續打線方法包含： —導線打線連接於一第一焊點後往一第二焊點移動進 行打線，使該導線在該第一焊點及第二焊點形成一第 一線段；及 該導線打線連接於第二焊點後往一第三焊點移動進 打線，使該導線在該第二焊點及第三焊點形成一第二 線段； 因而該第一線段經由該第二焊點第二線段連接形成該 導線。 1 0、依申請專利範圍第9項所述之導線連續打線方法’其 中該第二焊點設有一第二凸球。 11、依申請專利範圍第1 〇項所述之導線連續打線方法，其 中該凸球設有一平頂，该平頂設有一距離供該導線從In the amendment, the first solder joint is located on a first leg and the third solder joint is located on a first base in the first patent application scope. The first solder joint is located on a first two wafers and the third solder joint is located on an application. The first wafer and the second wafer in the patent scope item 7 are connected to the first wafer and the second crystal and the second wafer and the pins, so the one line segment, the second solder joint and the second third solder joint. The wafer and the second solder joint are located in a one-to-one wafer. The wire structure described above is continuous, and the sun-chip and the second solder joint are located at a first pin. The continuous wiring structure described above forms a stacked body, and the first line segment is connected to a piece, and the first solder joint of the second line segment connected to the first chip is electrically connected to the first of the pins via the second line segment. A continuous wire bonding method, the continuous wire bonding method includes:-connecting a wire to a first solder joint and moving the wire to a second solder joint to form a wire at the first solder joint and the second solder joint; A wire segment; and the wire is connected to the second solder joint and moved to a third solder joint to make the wire form a second wire segment at the second solder joint and the third solder joint; thus the first wire The segments are connected via the second solder joint and the second line segment to form the wire. 10. According to the continuous wire bonding method described in item 9 of the scope of the patent application, wherein the second solder joint is provided with a second convex ball. 11. The method for continuous wire routing according to item 10 of the scope of the patent application, wherein the convex ball is provided with a flat top, and the flat top is provided with a distance for the wire to follow. 笫14頁 Γ·4々65ί ---- -f 月 _曰 修真___ 六、申請專利範圍 第一線段沿該平頂之距離延伸至第二線段，該平頂之-距離使該凸球之平頂延伸於該第一焊點與第三焊點之 間。 1 2、依申請專利範圍第9項所述之導線連線打線方法，其 中該第一焊點及第三焊點分別設有一第一凸球及一第 三凸球。 1 3、依申請專利範圍第9項所述之導線連續打線方法，其 中該第一線段及第二線段具有適當弧度以避免在該第 二焊點附近該第一線段末端及第二線段起端過於接 近，因而導致該第一線段末端及第二線段起端之間產 生不必要的相互碰觸。 1 4、依申請專利範圍第9項所述之導線連續打線方法，其 中該第一焊點位於一第一晶片、該第二焊點位於一接 腳及該第三焊點位於一第二晶片。 1 5、依申請專利範圍第9項所述之導線連續打線方法，其和 中該第一焊點位於一第一晶片、該第二焊點位於一第ί?：! 二晶片及該第三焊點位於一接腳。 1 6、依申請專利範圍第1 5項所述之導線連續打線方法，其 中該第一晶片及第二晶片形成堆疊體，該第一線段連、 接於該第一晶片及第二晶片，而該第二線段連接於該 第二晶片及接腳，因而該第一晶片之第一焊點經該第 一線段、第二焊點及第二線段電性連接至該接腳之第 三焊點。笫 Page 14 Γ · 4々65ί ---- -f month _ Yue Xiu ___ 6. The first line segment of the scope of patent application extends along the distance from the flat top to the second line segment, and the-distance of the flat top makes the convex The flat top of the ball extends between the first solder joint and the third solder joint. 1 2. According to the method of wire connection and wiring described in item 9 of the scope of the patent application, wherein the first solder joint and the third solder joint are respectively provided with a first convex ball and a third convex ball. 1 3. The method of continuous wire routing according to item 9 of the scope of the patent application, wherein the first line segment and the second line segment have a proper arc to avoid the end of the first line segment and the second line segment near the second solder joint. The starting ends are too close, resulting in unnecessary contact between the end of the first line segment and the beginning of the second line segment. 14. The continuous wire bonding method according to item 9 of the scope of the patent application, wherein the first solder joint is located on a first wafer, the second solder joint is located on a pin, and the third solder joint is located on a second wafer. . 1 5. According to the continuous wire bonding method described in item 9 of the scope of the patent application, in which the first solder joint is located on a first wafer, the second solder joint is located on a first ?: two wafers and the third The solder joint is located on a pin. 16. The method for continuous wire routing according to item 15 of the scope of the patent application, wherein the first chip and the second chip form a stack, and the first line segment is connected to the first chip and the second chip. The second line segment is connected to the second chip and the pin, so the first solder joint of the first chip is electrically connected to the third pin of the pin via the first line segment, the second solder joint, and the second line segment. Solder joint.
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