1362097 九、發明說明： 【發明所屬之技術領域】 4寺別係有關於一種打 本發明係有關於半導體裝置， 線在多曲折接指之半導體封裝構造。 【先前技術】 在已知的半導體封裝構造中’晶片係黏設於一晶片 載體，例如導線架或線路基板。並f見地藉由打線形成 之複數個銲線電性連接晶斑日Η # m 丈丧日日片與日曰片载體。其中，晶片載 體上會設有複數個接指，以供媒綠夕 供知線之一端連接。然而隨 著高密度積體電路、微間距端子斑私賠 碼于興封裝體積微小化的發 展，接指之排列間隙蛊赏唐抱也 、見度越來越小，使得銲線容易誤 觸鄰近接指而產生電氣短路。此卜 此外’接指可供截斷銲線 之距離越來越小，導致打線作業 F呆囝難貫施。因此，現行 的作法是針對具有不同尺寸戋 丁3不冋銲墊配置之晶片，設 計出專屬的晶片載體’其係具有 ’對應日日片銲塾的接指排 列順序與排列位置，故共用性甚差。 請參閱第1及2圖所示，習知主造 為知+導體封裝構造100 係包含一導線架之複數個第一 Μ 弓丨腳110與第二引腳 150、-晶片120以及複數個第—銲線131與第二銲線 132。每一第一引腳U0之内端係具有一接指m，每一 第二引腳15〇之内端係具有一接# 151，以供打線接 合。該些第一引聊110與該些第二弓1腳15〇係具有延伸 在該半導體封裝構造100兩相對側之外引腳（或外露 墊）。請參閱第2圖所示，該些第一引腳11〇之接指^ 5 1362097 與該些第二引腳150之接指151係為「相隔的平行排 列」，即如第2圖所示，該些第一引腳110之接指U1 與該些第二引腳1 50之接指1 5 1之間係相隔有一間隙 S 1，並且以其内端朝向該間隙S1之方式分別排列在該 間隙S1之兩側。其中該些第一引腳11 0係較長於該些 第二引腳150，以供設置該晶片120。該些第一銲線13 i 係電性連接該晶片120之複數個銲墊122至該些第一引 鲁 腳110之接指111，而該些第二銲線132係電性連接該 晶片120之該些銲墊122至該些第二引腳150之接指 151。一封膠體170係密封該晶片120、該些第一銲線 • 丨31、該些第二銲線132以及該些第一引腳110之内端 • 與該些第二引腳150之内端，但可顯露該些第一引腳 110之外引腳與該些第二引腳150之外引腳。請再參閱 第2圖所示，基於以上所述的該些第一引腳ι10之接指 111與該些第二引腳丨50之接指1 5 1的排列位置，該晶 φ 片1 20之該些銲墊丨22亦須對應排列，以確保該些銲線 131與132之打線方向係與該些第一引腳11〇之接指m 以及該些第二引腳15〇之接指151的延伸方向大致對 齊，故習知的半導體封裝構造1〇〇只能封裝—種銲塾排 列固定與尺寸固定之晶片1 20。若選用其它類型的晶片 時，晶片之銲墊排列位置或/及晶片尺寸將有所不相 同’導致銲線之打線方向會與導線架之接指延伸方向產 生傾斜角度或是銲線交錯的問題’在打線與模封過程中 會誤觸鄰近接指導致電氟短路。 6 1362097 【發明内容】 本發明之主要目的係在於提供一種打線在多 指之半導體封裝構造，藉由銲線可選擇性連接在 接指之多個接指部，使該封裝構造具有共用性，、 具有不同尺寸或不同銲墊配置之晶片，在較佳的 線角度下能避免誤觸鄰近接指。 本發明之次一目的係在於提供一種打線在多 指之半導體封裝構造，能使第一銲線與第二銲線 較為平均，以避免在封膠製程中因銲線長度不同 鄰之銲線相互接觸導致訊號短路之問題。 本發明的目的及解決其技術問題是採用以下 案來實現的。依據本發明一種打線在多曲折接指 體封裝構造，主要包含一導線架之複數個第一引 晶片以及複數個銲線。每一第一引腳係具有一多 指’其係包含曲折連接之一第一接指部與一第 部。該晶片係具有複數個銲墊，該些銲線之一端 該些銲墊並且另一端選擇性連接於該些第一接 該些第二接指部之其中一群組，其中該些銲線之 向與包含該些第一或第二接指部之連接群組之 向之間係形成一第一夾角，該些銲線之打線方向 該些第一或第一接指部之未連接群組之延伸方 係形成一第二夾角，該第一夾角係不大於該第二 在不同實施例的應用上’該導線架係可為一具有 多曲折接指之晶片載體，每一多曲折接指係包含 曲折接 多曲折 J 能封裝 接指打 曲折接 的4度 造成相 技術方 之半導 腳' — 曲折接 -一接指 係連接 指部與 打線方 延伸方 與包含 向之間 夾角。 複數個 曲折連 7 1362097 接之一第一接指部與一第二接指部，一半導體封裝構造 係利用該晶片載體承載該晶片，再藉由該些銲線電性連 接該晶片至該第一接指部或該第二接指部之其中一群 組。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述的半導體封裝構造中，該第一夹角係可趨近 Φ 於零，以使該些銲線之打線方向與包含該些第一或第二 接指部之連接群組之延伸方向大致平行。 在前述的半導體封裝構造中，該些第一接指部係可 相對於該些第二接指部更鄰近於該晶片。 在前述的半導體封裝構造十，該些第二接指部係可 包含該些第一引腳之内端。 在前述的半導體封裝構造中，該些多曲折接指係可 為z字形。 # 在前述的半導體封裝構造中，可另包含有一電鍍 層’其係形成於該些多曲折接指之表面。 在前述的半導體封裝構造中，可另包含有該導線架 之複數個第二引腳，每一第二引腳係具有一第二接指 部’該些第三接指部係與該些第一接指部相鄰地錯位平 行排列。 在前述的半導體封裝構造中，至少一之該些第二引 腳之内端亦可為多曲折狀並具有一第四接指部’該第四 接指部係與該些第一接指部相鄰地錯位平行排列。 8 1362097 在前述的半導體封裝構造中，該些第一弓丨腳係可較 長於該些第二引腳並往該些第二弓丨腳延伸，以供該晶片 之設置。 在前述的半導體封裝構造中，町另包含有該導線架 之複數個晶片承座’其係位於該些第一引腳之兩侧。 在前述的半導體封裝構造中，可另包含有一封膠 體’以密封該晶片、該些銲線與該些第一引腳之内端與 該些第二引腳之内端，而該些第〆引腳之外端與該些第 二引腳之外端係分別延伸外露在该封膠體之兩相對側 邊。 在前述的半導體封裝構造中，該些銲塾係可位於該 晶片之其中一側邊，並且該晶片之該側邊之中央係留有 一無銲墊留白區》 【實施方式】 第3至5圖係有關於本發明之第一具體實施例’揭 示一種打線在多曲折接指之半導赠封裝構造。第3圖係 為該半導體封裝構造剖切第一引腳之截面示意圖。第4 圖係為該半導體封裝構造剖切第二引腳之截面示意 圖。第5圖則為該半導體封裝構造所使用導線架之平面 示意圖。 請參閱第3及4圖所示，一種半導體封裝構造200 係主要包含一導線架2 0(如第5圖所示）之複數個第一引 腳210、一晶片22 0以及複數個第一銲線231。如第5 及6圖所示，每一第一引腳210係具有一多曲折接指 9 13620971362097 IX. Description of the Invention: [Technical Field to Be Invented by the Invention] 4 The present invention relates to a semiconductor package in which a semiconductor device is wired in a multi-folded finger. [Prior Art] In the known semiconductor package construction, the wafer is attached to a wafer carrier such as a lead frame or a wiring substrate. And f see the ground by the plurality of bonding wires formed by the wire to electrically connect the spotted sundial # m 丧 日 日 日 日 日 日 日 日 日 日Wherein, a plurality of fingers are arranged on the wafer carrier for connecting one end of the medium green communication line. However, with the development of the high-density integrated circuit and the micro-pitch terminal patchy code, the size of the package is small, and the arrangement gap of the fingers is more and less, and the visibility is getting smaller and smaller, making the wire easy to touch the adjacent area. An electrical short circuit occurs when the finger is connected. In addition, the distance between the fingers to cut off the welding wire is getting smaller and smaller, which makes the wire-laying operation F difficult. Therefore, the current practice is to design a wafer carrier with a different size of the solder pad configuration, which has a corresponding wafer carrier order and arrangement position corresponding to the day-to-day chip solder joint, so the commonality Very bad. Referring to FIGS. 1 and 2, the conventional master-conductor package structure 100 includes a plurality of first bow legs 110 and a second pin 150, a wafer 120, and a plurality of - a bonding wire 131 and a second bonding wire 132. The inner end of each first pin U0 has a finger m, and the inner end of each second pin 15 has an interface #151 for wire bonding. The first chats 110 and the second bows 1 have 15 pins (or exposed pads) extending on opposite sides of the semiconductor package 100. Referring to FIG. 2, the first pin 11's finger ^ 5 1362097 and the second pin 150's finger 151 are "parallel arrangement", as shown in FIG. The fingers U1 of the first pins 110 and the fingers 1 51 of the second pins 150 are separated by a gap S1 and are respectively arranged with their inner ends facing the gap S1. Both sides of the gap S1. The first pins 110 are longer than the second pins 150 for the wafer 120 to be disposed. The first bonding wires 13 i are electrically connected to the plurality of pads 122 of the wafer 120 to the fingers 111 of the first routing pins 110 , and the second bonding wires 132 are electrically connected to the wafer 120 . The pads 122 are connected to the fingers 151 of the second pins 150. A glue body 170 seals the wafer 120, the first bonding wires 丨31, the second bonding wires 132, and the inner ends of the first pins 110 and the inner ends of the second pins 150 However, the pins other than the first pin 110 and the pins other than the second pin 150 may be exposed. Referring to FIG. 2 again, based on the arrangement positions of the fingers 111 of the first pin ι10 and the fingers 151 of the second pins 以上 50, the crystal φ piece 1 20 The soldering pads 22 are also arranged to ensure that the bonding directions of the bonding wires 131 and 132 are connected to the first pin 11 and the second pin 15 The extending direction of 151 is substantially aligned, so that the conventional semiconductor package structure 1 can only package a wafer 1 20 in which the solder fillet is fixed and fixed in size. If other types of wafers are used, the position of the pads of the wafers and/or the size of the wafers will be different, resulting in a problem that the direction of the bonding wires will be inclined to the direction in which the leads of the lead frames extend or the wires are staggered. 'In the process of wire bonding and molding, the proximity contact will be touched and the fluorine short circuit will be called. 6 1362097 SUMMARY OF THE INVENTION The main object of the present invention is to provide a semiconductor package structure in which a wire is wired in a multi-finger, which can be selectively connected to a plurality of fingers of a finger by a bonding wire to make the package structure shareable. A wafer having different size or different pad configurations can avoid accidental contact with adjacent fingers at a preferred line angle. A second object of the present invention is to provide a semiconductor package structure in which a wire is applied in a multi-finger, which can make the first bonding wire and the second bonding wire relatively average, so as to prevent the bonding wires from being adjacent to each other due to different wire bonding lengths in the sealing process. Contact causes a problem with the signal being shorted. The object of the present invention and solving the technical problems thereof are achieved by the following cases. According to the present invention, a wire bonding in a multi-folded finger package structure mainly includes a plurality of first lead wires and a plurality of bonding wires of a lead frame. Each of the first pins has a plurality of fingers' which includes a first finger portion and a first portion of the meandering connection. The chip has a plurality of pads, one of the pads is connected to the pads, and the other end is selectively connected to one of the first contacts of the second fingers, wherein the wires are Forming a first angle between the direction of the connection group including the first or second finger portions, and the unbonded groups of the first or first finger portions of the bonding wires The extension means forms a second angle, the first angle is not greater than the second. In the application of the different embodiments, the lead frame can be a wafer carrier having a plurality of meandering fingers, each of the plurality of meandering fingers The system includes a zigzag multi-folded J-encapsulated finger, and the 4th degree of the twist-and-loop method is used to make the semi-guided leg of the phase-technical method's - the zigzag-joint finger-joining finger and the angle between the extension of the wire-line and the inclusion direction. a plurality of zigzag connections 7 1362097 are connected to a first finger portion and a second finger portion, a semiconductor package structure is used to carry the wafer by the wafer carrier, and the wafer is electrically connected to the wafer by the bonding wires One of the fingers or one of the second fingers. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the foregoing semiconductor package structure, the first angle can be close to Φ to zero, so that the wire bonding direction of the bonding wires is substantially the same as the extending direction of the connection group including the first or second fingers. parallel. In the foregoing semiconductor package construction, the first fingers may be closer to the wafer relative to the second fingers. In the foregoing semiconductor package construction ten, the second finger portions may include inner ends of the first pins. In the foregoing semiconductor package construction, the plurality of zigzag fingers may be zigzag. # In the foregoing semiconductor package structure, an electroplated layer may be further included, which is formed on the surface of the plurality of zigzag fingers. In the foregoing semiconductor package structure, a plurality of second pins of the lead frame may be further included, and each of the second pins has a second finger portion, and the third finger portions are associated with the first One finger is adjacently arranged in parallel and arranged in parallel. In the foregoing semiconductor package structure, at least one of the inner ends of the second pins may be multi-folded and have a fourth finger portion, and the fourth finger portion and the first finger portion The adjacent misalignments are arranged in parallel. 8 1362097 In the foregoing semiconductor package construction, the first bow legs can be longer than the second pins and extend toward the second legs for the placement of the wafer. In the foregoing semiconductor package structure, the plurality of wafer holders of the lead frame are further disposed on both sides of the first pins. In the foregoing semiconductor package structure, a gel may be further included to seal the wafer, the bonding wires and the inner ends of the first pins and the inner ends of the second pins, and the third ends The outer ends of the pins and the outer ends of the second pins are respectively extended to expose opposite sides of the sealant. In the foregoing semiconductor package structure, the solder pads may be located on one side of the wafer, and a center of the side of the wafer is left with a solderless blank area. [Embodiment] FIGS. 3 to 5 In connection with the first embodiment of the present invention, a semi-conducting package structure in which a wire is bent in a multi-folded finger is disclosed. Figure 3 is a cross-sectional view showing the first pin of the semiconductor package structure. Fig. 4 is a schematic cross-sectional view showing the second lead of the semiconductor package structure. Figure 5 is a plan view of the leadframe used in the semiconductor package construction. Referring to FIGS. 3 and 4, a semiconductor package structure 200 is mainly composed of a plurality of first leads 210, a wafer 22 0 and a plurality of first solders of a lead frame 20 (as shown in FIG. 5). Line 231. As shown in Figures 5 and 6, each of the first pins 210 has a multi-folded finger 9 1362097
千連接之一第一接指部212與一第二 ，在此所指「曲折速接」係指該第一 二接指部213連接之部位係形成有一 概呈V形之曲折角度，該曲折角度約為20度至90度。 在本實靶例中，該些多曲折接指211係可為z字形，具 有至少一曲折。 請參閱第3及6圖所系’該些第一接指 部2 1 2係可相對於該些第二接指部2 1 3更鄰近於該晶片 220。該些第二接指部213係可包含該些第-引腳210 之内端。 請參閱第4及5圖所示，該半導體封裝構造200係 可另包含有該導線架20之複數個第二引腳250。如第3 圖所示，該些第二引腳250之外端與該些第一引腳210 之之外端分別排列在該半導體封裝構造2〇〇之兩對稱 侧邊。在本實施例中，該些第二引腳2 5 〇之外端與該些 第一引腳2 1 0之外端係為由一封膠體270之兩對稱側邊 外露延伸的外引腳，並可彎折成海鷗腳（gull lead)，或 可彎折成其它形狀。每一第二引腳250係具有一第三接 指部252,該些第三接指部252係與該些第一接指部212 相鄰地錯位平行排列。在此所稱之「相鄰地錯位平行排 列」，係如第5圖之左側所示，該些第一引腳2 1 0之内 端係朝向該些第二引腳延伸且超越該些第三接指部 252,並使該些第一接指部212係與該些第三接指部252 對齊。至少一之該些第二引腳250係具有一多曲折接指 251，即為該第二引腳250之内端亦可為多曲折狀並具 10 1362097 有一第四接指部253’其係與該第三接指部252曲折連 接’其中該第四接指部253係可與該些第二接指部213 相鄰地錯位平行排列》再如第3及5圖所示，該些第一 引腳210係可較長於該些第二引腳25〇並往該些第二引 腳250延伸，以供該晶片22〇之設置。具體而言，如第 3圖所示，該半導體封裝構造2〇0係可另包含有一電鍍 層240，其係形成於該些第一引腳21〇之該些多曲折接 鲁 指211之表面，其覆蓋面積包含了該些第一接指部212 與該些第二接指部213，用以增加對該些銲線231的結 合力。如第4圖所示’該電鍍層240更可形成於該些第 二引腳250之該些多曲折接指251之表面，並覆蓋該些 第二接心部252與該些第四接指部253。該電鍵層240 之材質係可選用於銀、鎳金、錫、鎳把金、錫錯、錫祕 之其中之一。 該晶片220係具有一主動面221，該主動面22!上 φ 係設有複數個銲墊222 ’以作為該晶片220之對外電 極。在本實施例中’該些銲墊222係可位於該晶片220 之其中一侧邊，並且該些銲墊222的配置位置與間隙都 有相當大的彈性。例如’如第6圖所示，該晶片220之 該侧邊之中央係可留有一無銲墊留白區，其係大於該些 銲塾222之平均間隙’而將該些銲墊222區分成前半部 群組銲塾與後半部群組銲墊。該晶片220係可為快閃記 憶體晶片220»如第3及6圖所示，可利用一黏晶層280 黏接該晶片220至該些第一引腳210之表面，並使該晶 11 1362097 片220係以該主動面221 設置於該些第-引腳210上。請參閱第5及6圖所干 該半導體封裝構造200係可另包含有該導線架2〇之複 數個晶片承座260，其係位於該些第一引腳2ι〇之兩 側’以供增進晶片設置之補強功效。One of the first connecting fingers 212 and the second one of the thousands of links, the term "tortuous speeding" as used herein means that the portion connecting the first two fingers 213 is formed with a generally V-shaped meander angle, the meandering The angle is approximately 20 to 90 degrees. In the actual target example, the plurality of polygonal fingers 211 may be zigzag with at least one meander. Referring to Figures 3 and 6, the first finger portions 2 1 2 are further adjacent to the wafer 220 with respect to the second finger portions 2 1 3 . The second fingers 213 may include inner ends of the first pins 210. Referring to Figures 4 and 5, the semiconductor package structure 200 can further include a plurality of second pins 250 of the leadframe 20. As shown in FIG. 3, the outer ends of the second pins 250 and the outer ends of the first pins 210 are respectively arranged on two symmetric sides of the semiconductor package structure 2'. In this embodiment, the outer ends of the second pins 2 5 〇 and the outer ends of the first pins 2 1 0 are external pins extended by two symmetric sides of a colloid 270. It can be bent into a gull lead or can be bent into other shapes. Each of the second pins 250 has a third finger portion 252, and the third finger portions 252 are arranged in parallel with the first finger portions 212 in a staggered manner. As shown in the left side of FIG. 5, the inner ends of the first pins 210 are extended toward the second pins and beyond the first portions. The fingers 252 are connected to the third finger 252 and the third fingers 252 are aligned with each other. At least one of the second pins 250 has a plurality of bent fingers 251, that is, the inner ends of the second pins 250 may be multi-folded and have a 10 1362097 and a fourth finger 253' The third finger portion 252 is bent and connected to the third finger portion 252, wherein the fourth finger portion 253 can be arranged in parallel with the second finger portions 213 in a staggered manner. As shown in FIGS. 3 and 5, the first A pin 210 can be longer than the second pins 25 and extend toward the second pins 250 for the wafer 22 to be disposed. Specifically, as shown in FIG. 3, the semiconductor package structure 〇0 can further include a plating layer 240 formed on the surface of the plurality of bent fingers 211 of the first pins 21 The cover area includes the first finger portion 212 and the second finger portions 213 for increasing the bonding force of the wire bonds 231. As shown in FIG. 4, the plating layer 240 may be formed on the surface of the plurality of bent fingers 251 of the second pins 250, and covers the second core portions 252 and the fourth fingers. Part 253. The material of the key layer 240 can be selected from one of silver, nickel gold, tin, nickel, gold, tin, and tin. The wafer 220 has an active surface 221 on which a plurality of pads 222' are provided as the external electrodes of the wafer 220. In the present embodiment, the pads 222 can be located on one side of the wafer 220, and the pads 222 are disposed at a considerable degree of elasticity with respect to the gap. For example, as shown in FIG. 6, the center of the side of the wafer 220 may have a solderless pad blank area that is larger than the average gap of the solder pads 222 and separate the pads 222 into The first half of the group of soldering and the latter half of the group of pads. The wafer 220 can be a flash memory chip 220», as shown in FIGS. 3 and 6, the die 220 can be bonded to the surface of the first pins 210 by using a die bonding layer 280, and the crystal 11 is The 1362097 piece 220 is disposed on the first pin 210 by the active surface 221 . Referring to FIGS. 5 and 6 , the semiconductor package structure 200 can further include a plurality of wafer holders 260 of the lead frame 2 , on the two sides of the first pins 2 〇 for improvement The reinforcing effect of the wafer setup.
請參閱第6、7及8圖所示，該些第一銲線23ι之第 一端231Α係連接該些銲墊222並且第二端23ιβ選擇 性連接於該些第一接指部212與該些第二接指部213之 其中一群組。在本實施例中，每一第一銲線231之該第 一端23 1 Α係可為起始端，而該第二端23 1Β則為終止 端’即為由晶片至接指部（導線架）的正向打線。但不受 限制地，該些第一銲線23 1亦可為由接指部（導線架）至 晶片的逆向打線。然在本發明中’以正向打線為較佳。 其中該些第一銲線231之打線方向與包含該些第—接 指部212或該些第二接指部213之連接群組之延伸方向 之間係形成一第一夾角01，該些第一銲線231之打線 方向與包含該些第二接指部213或第一接指部212之未 連接群組之延伸方向之間係形成一第二夾角02，該第 一夾角01係不大於該第二夾角02。其中，在此所指 打線方向」係指該些第一銲線231之該第一端231Α 至該第二端231Β在該導線架20上之水平方向（如第7 及8圖所示）。請參閱第7圖所示，當該些第一銲線23 1 之第一端231Α係連接至該些銲墊222，該些銲線之第 二端231Β則選擇性連接該些第一引腳210之第一接指 12 1362097 部212，此時該些第一銲線23 1之打線方向與該些第一 接指部212(被連接接指部）之延伸方向之間所形成之該 第一失角Θ1係小於該些第一銲線231之打線方向與該 二第一接指部213(未連接接指部）之延伸方向之間所形 成之該第二夾角02。請參閱第8圖所示，該些第一銲 線231之第一端231A係連接該些銲塾222，該些錄線 之第二端23 1B係選擇性連接至該些第—引腳21〇之第Referring to FIGS. 6 , 7 and 8 , the first ends 231 of the first bonding wires 23 Α are connected to the pads 222 and the second ends 23 πβ are selectively connected to the first fingers 212 and One of the second fingers 213. In this embodiment, the first end 23 1 of each of the first bonding wires 231 can be the starting end, and the second end 23 1 Β is the terminating end, that is, from the wafer to the connecting portion (the lead frame) ) The positive line. However, without limitation, the first bonding wires 23 1 may also be reversely wired from the fingers (lead frame) to the wafer. However, in the present invention, it is preferable to use a positive line. Forming a first angle 01 between the wire bonding direction of the first bonding wires 231 and the extending direction of the connection group including the first finger portions 212 or the second finger portions 213, the first A second angle 02 is formed between a wire bonding direction of the bonding wire 231 and an extending direction of the unconnected group including the second finger portion 213 or the first finger portion 212, and the first angle 01 is not greater than The second angle 02. The term "wire direction" as used herein refers to the horizontal direction of the first end 231 至 to the second end 231 of the first bonding wires 231 on the lead frame 20 (as shown in FIGS. 7 and 8). Referring to FIG. 7 , when the first ends 231 of the first bonding wires 23 1 are connected to the pads 222 , the second ends 231 of the bonding wires are selectively connected to the first pins. The first finger of 210 is the portion of the first finger wire 23 1 and the direction in which the first finger portion 212 (the connected finger portion) extends. The second angle θ1 is smaller than the second angle 02 formed between the direction of the wire bonding of the first bonding wires 231 and the extending direction of the two first finger portions 213 (the unconnected fingers). Referring to FIG. 8 , the first ends 231A of the first bonding wires 231 are connected to the soldering pads 222 , and the second ends 23 1B of the recording wires are selectively connected to the first pins 21 . 〇之第
二接指部213’此時該些第一銲線231之打線方向與該 些第二接指部213(被連接接指部）之延伸方向之間所形 成之該第一夾角0 1係小於該些第一銲線23丨之打線方 向與該些第一接指部212(未連接接指部）之延伸方向之 間所形成之該第二夾角02。因此，該些第一接指部212 與該些第二接指部213可提供打線靈活度，以提供該些 銲線231較佳的接指打線角度，以避免誤觸鄰近之 多曲折接指211。再如第7及8圖所示，在本實施例中， 該第一夾角01係可趨近於零，以使該些第一銲線231 之打線方向與包含該些第一接指部212或該些第二接 指部2 1 3之連接群組之延伸方向大致平行，達到完全的 對齊。 該半導體封裝構造200可以封裝具有不同銲墊配置 位置或/與不同尺寸之晶片。如第9圖所示，另一晶片 220’可設置於該導線架上。該晶片22〇，之複數個Z墊 222’係可位於該晶片220’之主動面221，之單一側邊，且 在該些銲墊222’之間可以不設有無銲墊留白區。該些第 13 1362097 一麵線231係電性連接該晶片.220’之該些鲜塾222,並 選擇性連接至該些第一引腳210之該些第一接指部212 或該些第二接指部213，以提供該晶片220,較佳的打線 角度，故利用該些多曲折接指211之該些第一接指部212 與該些第二接指部213可提供銲線231之選擇性接合 以適用具有不同銲墊配置之晶片，達到在較佳的接指打 線角度以避免誤觸鄰近接指。The first angle θ1 formed by the second finger 213' between the wire bonding direction of the first bonding wires 231 and the extending direction of the second finger portions 213 (connected fingers) is smaller than The second angle 02 formed between the wire bonding direction of the first bonding wires 23 and the extending direction of the first finger portions 212 (the unconnected fingers). Therefore, the first finger portions 212 and the second finger portions 213 can provide wire bonding flexibility to provide better wire angles of the wire wires 231 to avoid accidental contact with the adjacent plurality of meandering fingers. 211. As shown in the seventh and eighth embodiments, in the embodiment, the first angle 01 can be close to zero, so that the first bonding wires 231 are wired and the first fingers 212 are included. Or the connection groups of the second finger portions 2 1 3 extend substantially in parallel to achieve complete alignment. The semiconductor package construction 200 can package wafers having different pad configuration locations or/and different sizes. As shown in Fig. 9, another wafer 220' may be disposed on the lead frame. The plurality of Z pads 222' of the wafer 22 may be located on a single side of the active surface 221 of the wafer 220', and no solder pad blank area may be provided between the pads 222'. The first line 231 is electrically connected to the dice 222 of the chip 220. and is selectively connected to the first fingers 212 of the first pins 210 or the The second finger portion 213 is provided to provide the wafer 220, and the wire bonding angle is provided. Therefore, the first finger portions 212 and the second finger portions 213 of the plurality of bent fingers 211 can be used to provide the bonding wires 231. The selective bonding is suitable for wafers having different pad configurations to achieve a preferred fingering angle to avoid accidental contact with adjacent fingers.
請參閱第4及6圖所示’複數個第二銲線232係電 性連接該晶片220之該些銲墊222至該些第二引腳25〇 之該些第三接指部252或該些第四接指部253。由於該 些第二引腳250之其一之内端亦可為多曲折狀並具有 該第四接指部253，故該第二引腳25〇之該第三接指部 252與該第四接指部253，可提供該些第二銲線232較 佳的打線位置。通常該些第二銲線232係選擇較鄰近該 晶片220之該些第三接指部252,以縮短打線距離。請 再參閱第5及6圖所示，雖然該些第一引腳21〇與該些 第二引腳250分別排列在該導線架2〇之不同侧邊，但 該些第一引腳21〇之多曲折接指211與該些第二引腳 250之多曲折接指仍可為相鄰地錯位平行排列，並且該 些第一引腳210之内端係朝向該些第二引腳延伸且 超過該些第二引腳250之内端，使得分別地該些第一接 指部2 1 2之配置區與該妆第：桩护邱，< Λ —乐一接知部252之配置區並 排，該些第二接指部2 13 t @ ρ 4 & t配置區與該些第四接指部 253之配置區並排，故在打錄 打線時可使該些第一銲線23 1 1362097 與該些第二銲線232之長度較為平均。 具體而言’該半導體封裝構造2〇〇係可另包含有一 封膠體270，以密封該晶片22〇、該些第一銲線、 該些第二銲線232、該些第一引腳21〇之内端與該些第 二引腳250之内端，而該些第一引腳21〇之外端與該些 第二引腳250之外端係分別延伸外露在該封膠體27〇之 兩相對侧邊’以供對外表面接合。 φ 因此，藉由每一第一引腳21〇具有不同彎折角度之 接扣P 212與第一接指部213，能提供較佳的接指 打線角度，以避免該些第一銲線231誤觸鄰近之多曲折 接指211’亦可提供不同尺寸或不同銲墊配置之晶片之 較佳的接指打線角度，使該半導體封裝構造2〇〇具有共 用性’能封裝具有不同銲墊配置或/與不同尺寸之晶 片。此外，由於該些第一引腳21〇之多曲折接指211至 該些銲墊222之距離概為相等於該些第二引腳25〇之多 鲁 曲折接#a 251至該些銲塾222之距離’故在打線時，該 些第一銲線231與該些第二銲線232的長度可較為平 均’亦可控制銲線之長度。如此一來，即使在封膠製程 中該些第一銲線231與該些第二銲線232受模流影響產 生位移，也較不會因銲線長度不同造成相鄰之銲線相互 碰觸，而導致訊號短路失效的問題。Referring to FIGS. 4 and 6 , a plurality of second bonding wires 232 are electrically connected to the pads 222 of the die 220 to the third fingers 252 of the second pins 25 或 or the Some fourth fingers 253. Since the inner ends of the second pins 250 may be multi-folded and have the fourth fingers 253, the third pins 25 and 252 of the second pins 25 The finger 253 can provide a better wire bonding position of the second bonding wires 232. Typically, the second bonding wires 232 select the third fingers 252 that are closer to the wafer 220 to shorten the wire bonding distance. Please refer to FIGS. 5 and 6 again. Although the first pin 21 〇 and the second pins 250 are respectively arranged on different sides of the lead frame 2 , the first pins 21 〇 The plurality of zigzag fingers 211 and the plurality of zigzag fingers of the second pins 250 may be arranged in parallel adjacent to each other, and the inner ends of the first pins 210 extend toward the second pins. Exceeding the inner ends of the second pins 250, respectively, so that the arrangement areas of the first finger portions 2 1 2 and the configuration area of the makeup part: < Λ 乐 乐 知 知 252 Side by side, the second finger portions 2 13 t @ ρ 4 & t arrangement area and the arrangement areas of the fourth finger portions 253 are arranged side by side, so that the first bonding wires 23 1 can be made when recording the wire bonding The length of 1362097 and the second bonding wires 232 are relatively average. Specifically, the semiconductor package structure 2 may further include a glue 270 for sealing the wafer 22, the first bonding wires, the second bonding wires 232, and the first pins 21〇. The inner end of the first pin 21 and the outer end of the second pin 250 and the outer ends of the second pin 250 are respectively extended to expose the two sides of the sealing body 27 The opposite side 'for the outer surface joint. Therefore, by the first pin 21 接 having different bending angles of the buckle P 212 and the first finger portion 213, a better finger wire angle can be provided to avoid the first wire 231. Mis-touching the adjacent multi-folding fingers 211' can also provide a preferred finger-bonding angle of the wafers of different sizes or different pad configurations, so that the semiconductor package structure 2 has a common 'encapsulation with different pad configurations Or / with different size wafers. In addition, since the distance between the plurality of bent fingers 211 of the first pins 21 211 and the pads 222 is substantially equal to the multiple turns of the second pins 25 # to the solder pads The distance 222 is such that the lengths of the first bonding wires 231 and the second bonding wires 232 can be relatively average when the wire is being wired, and the length of the bonding wires can also be controlled. In this way, even if the first bonding wires 231 and the second bonding wires 232 are displaced by the mold flow during the sealing process, the adjacent bonding wires are not touched by the different lengths of the bonding wires. , causing the problem of signal short-circuit failure.
在本發明之第二具體實施例中，揭示另一種打線在 多曲折接指之半導體封裝構造《請參閱第10圖所示， 該半導體封裝構造300係包含一晶片載體31〇、_ a H 15 1362097 320以及複數個銲線330。在本實施例中， 310係可為一線路基板。請參閱第I〗及丄^ 晶片載體310係具有複數個多曲折接指311 折接指311係包含曲折連接之一第一接指部 二接指部313。該些多曲折接指311之表面 電锻層340’其係覆蓋該些第一接指部312 接才曰部313。該晶片320係具有複數個銲墊 該晶片載體3 1 0上。請參閱第1 0及1 Γ圖所 鲁線之第一端331係連接該些銲墊322 3 3 2係選擇性連接於該些第一接指部3丨2與 指部313之其中一群組’其中該些銲線33〇 與包含該些第一接指部312或該些第二接指 接群組之延伸方向之間係形成一第一夾角 330之打線方向與包含該些第二接指部313 部3 1 2之未連接群組之延伸方向之間係形 φ 角’該第一夾角係不大於該第二夾角。當該 該第二夾角大致為相同時，該些銲線33 〇係 些第一接指部312 ’以縮短該些銲線33 〇之 因此，該半導體封裝構造3 00能封裝具 配置之晶片，並可提供較佳的打線角度以免 指。如第12圖所示，另一晶片32〇,係可設 載體310上，並藉由該些銲線330電性連接 之複數個銲墊3 22’至該晶片載體31〇之該 指311。其中，該些銲線33〇係連接該些銲 該晶片載體 圖所示，該 .，每一多曲 312與一第 係形成有一 與該些第二 322並設於 示，該些銲 並且第二端 該些第二接 之打線方向 部3 1 3之連 ，該些銲線 或第一接指 成一第二夹 第一夾角與 可連接於該 長度。 有不同銲墊 誤觸鄰近接 置於該晶片 該晶片320’ 些多曲折接 鱼322’與該 16 1362097 些第二接指部313。具體而言，該半導體封裝構造3 00 係可另包含有一封膠體370，其係形成於該晶片載體 310之上表面，以密封該晶片320以及該些銲線330。 因此’該半導體封裝構造300具有能封裝多種晶片之共 用性並符合接指微間距排列之要求。 以上所述’僅是本發明的較佳實施例而已，並非對 本發明作任何形式上的限制，本發明技術方案範圍當依 I 所附申請專利範圍為準。任何熟悉本專業的技術人員可 利用上述揭示的技術内容作出些許更動或修飾為等同 變化的等效實施例，但凡是未脫離本發明技術方案的内 容，依據本發明的技術實質對以上實施例所作的任何簡 單修改、等同變化與修飾，均仍屬於本發明技術方案的 範圍内。 【圖式簡單說明】 第1圖：習知半導體封裝構造之截面示意圖。 φ 第2圖：繪示習知半導體封裝構造在封膠前打線在晶片 主動面與導線架之間之平面示意圖。 第3圖：依據本發明之第一具體實施例’ 一種打線在多 曲折接指之半導體封裝構造剖切第一引腳之截面 示意圖。 第4圖.依據本發明之第一具體實施例，該半導體封裝 構造剖切第二引腳之截面示意圖。 第5圖：依據本發明之第一具體實施例，該半導體封裝 構造所使用導線架之平面示意圖。 17 1362097 第6圖 第7圖 第8圖 第9圖 第10 第11 第12 :依據本發明之第一具體實施例，繪示該半導體 封裝構造在封膠前打線在晶片主動面與導線 架之間之平面示意圖。 :依據本發明之第一具體實施例，繪示該半導體 封裝構造中銲線可連接晶片銲墊並選擇性連 接至多曲折接指之第一接指部之平面示意圖。 :依據本發明之第一具體實施例，繪示該半導體 封裝構造中銲線可連接晶片銲墊並選擇性連 接至多曲折接指之第二接指部之平面示意圖。 :依據本發明之第一具體實施例，繪示該半導體 封裝構造在封膠前打線在具有不同銲墊配置 變化晶片之主動面與導線架之間之平面示意 圖。 B :依據本發明之第二具體實施例，另一種打線 在多曲折接指之半導體封裝構造之截面示意 圖。 ]:依據本發明之第二具體實施例，繪示該半導 體封裝構造在封膠前打線在具有第一銲墊配 置晶片之主動面與晶片載體之間之局部立體 示意圖。 3 :依據本發明之第二具體實施例，繪示該半導 體封裝構造在封膠前打線在具有第二銲墊配 置晶片之主動面與晶片載體之間之局部立體 示意圖。 18 1362097 【主要元件符號說明】 20 導線架 100半導體封裝構造In a second embodiment of the present invention, another semiconductor package structure in which a plurality of wires are folded is shown. Referring to FIG. 10, the semiconductor package structure 300 includes a wafer carrier 31, _ a H 15 1362097 320 and a plurality of bonding wires 330. In this embodiment, the 310 series can be a circuit substrate. Please refer to page I and 丄^ The wafer carrier 310 has a plurality of multi-folded fingers 311. The folded fingers 311 comprise one of the first fingers and two fingers 313 of the meandering connection. The surface of the plurality of folded fingers 311 is electrically forged 340' to cover the first fingers 312. The wafer 320 has a plurality of pads on the wafer carrier 310. Please refer to the first end 331 of the 10th and 1st drawings, and connect the solder pads 322 3 3 2 to be selectively connected to one of the first finger portions 3丨2 and the fingers 313. a grouping direction in which the bonding wires 33A and the extending directions of the first finger portions 312 or the second finger-joining groups form a first angle 330 and includes the second portions The extending direction of the unconnected group of the finger portion 313 portion 3 1 2 is a line shape φ angle 'the first angle is not greater than the second angle. When the second angles are substantially the same, the bonding wires 33 are tied to the first fingers 312' to shorten the bonding wires 33. Therefore, the semiconductor package structure 300 can package the wafers with the configuration. A better wire angle can be provided to avoid fingering. As shown in Fig. 12, another wafer 32 is provided on the carrier 310, and the plurality of pads 3 22' electrically connected by the bonding wires 330 to the fingers 311 of the wafer carrier 31. Wherein, the bonding wires 33 are connected to the soldering wafer carrier, and each of the plurality of curves 312 and a first system is formed with the second portions 322, and the soldering and the first The second end of the second wire bonding direction portion 3 1 3 is connected to the second wire, and the first wire is connected to the length. There are different pads that are mis-touched adjacent to the wafer. The wafer 320' has a plurality of zigzag fish 322' and the second finger 313 of the 16 1362097. Specifically, the semiconductor package structure 300 may further include a glue 370 formed on an upper surface of the wafer carrier 310 to seal the wafer 320 and the bonding wires 330. Therefore, the semiconductor package structure 300 has the requirement of being able to package a plurality of types of wafers and conforming to the arrangement of the pitches of the fingers. The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the scope of the appended claims. Any person skilled in the art can make some modifications or modifications to the equivalent embodiments by using the technical content disclosed above, but the content of the technical solution of the present invention is made according to the technical essence of the present invention without departing from the technical solution of the present invention. Any simple modifications, equivalent changes and modifications are still within the scope of the technical solutions of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional semiconductor package structure. φ Fig. 2 is a schematic plan view showing the conventional semiconductor package structure between the active surface of the wafer and the lead frame before the sealing. Fig. 3 is a cross-sectional view showing a first lead of a semiconductor package structure of a multi-folded finger according to a first embodiment of the present invention. Figure 4 is a cross-sectional view showing the second lead of the semiconductor package in accordance with a first embodiment of the present invention. Figure 5 is a plan view of a leadframe used in the semiconductor package construction in accordance with a first embodiment of the present invention. 17 1362097 Fig. 6 Fig. 7 Fig. 8 Fig. 9 Fig. 10th 11th 12th: According to the first embodiment of the present invention, the semiconductor package structure is wired before the encapsulation on the active surface of the wafer and the lead frame A schematic diagram of the plane between. According to a first embodiment of the present invention, a plan view of a wire bond pad in a semiconductor package structure in which a die pad is attached and selectively connected to a first finger portion of a multi-fold finger is shown. According to a first embodiment of the present invention, a schematic plan view of a semiconductor package in which a bonding wire can be connected to a die pad and selectively connected to a second finger of the multi-folded finger is shown. According to a first embodiment of the present invention, a plan view of the semiconductor package structure between the active surface of the wafer having different pad configuration variations and the lead frame is shown before the sealing of the semiconductor package. B: A cross-sectional view of another semiconductor package in a multi-folded finger according to a second embodiment of the present invention. According to a second embodiment of the present invention, a partial perspective view of the semiconductor package structure between the active surface having the first pad configuration wafer and the wafer carrier is illustrated before the sealing of the semiconductor package structure. 3: According to a second embodiment of the present invention, a partial perspective view of the semiconductor package structure before the seal is applied between the active surface of the wafer having the second pad and the wafer carrier is illustrated. 18 1362097 [Description of main component symbols] 20 lead frame 100 semiconductor package construction
110 第一引腳 111 接指 120 晶片 122 銲墊 131 第一銲線 132 第二銲線 150 第二引腳 151 接指 170封膠體 S1 間隙 200 半導體封裝構造 210 第一引腳 211 多曲折接指 212 第一接指部 213 第二接指部 220 晶片 221 主動面 222銲墊 220, 晶片 221， 主動面 222’銲墊 231 第一銲線 231A第一端 231B第二端 232 第二銲線 240 電鏡層 250 第二引腳 251 多曲折接指 252 第三接指部 253 第四接指部 260 晶片承座 270 封膠體 280黏晶層 300 半導體封裝構造 310 晶片載體 311 多曲折接指 312第一接指部 313 第二接指部 320 晶片 322 銲墊 320, 晶片 322, 銲墊 330 銲線 331 第一端 332第二端 19 1362097 340 電鍍層 370 Θ1 第一夹角 Θ2 封膠體 第二夾角110 first pin 111 finger 120 wafer 122 pad 131 first wire 132 second wire 150 second pin 151 finger 170 sealant S1 gap 200 semiconductor package structure 210 first pin 211 multi-fold finger 212 first finger portion 213 second finger portion 220 wafer 221 active surface 222 pad 220, wafer 221, active surface 222' pad 231 first bonding wire 231A first end 231B second end 232 second bonding wire 240 Electron mirror layer 250 second pin 251 multi-folded finger 252 third finger portion 253 fourth finger portion 260 wafer holder 270 sealant 280 adhesive layer 300 semiconductor package structure 310 wafer carrier 311 multi-folded finger 312 first Contact portion 313 second finger portion 320 wafer 322 pad 320, wafer 322, pad 330 bond wire 331 first end 332 second end 19 1362097 340 plating layer 370 第一 1 first angle Θ 2 sealing body second angle
2020