TW432599B - Removal of silicon hydroxide layer on polysilicon gate in integrated circuit processing - Google Patents
Removal of silicon hydroxide layer on polysilicon gate in integrated circuit processing Download PDFInfo
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p43259 9 五' 發明說明" ---- 5 -1發明領域: 本發明係有關於一種在積 極的氮氧矽的方法,特別是利 時性的蝕刻幕罩,以便進行餘 構。 體電路製程中移去多晶矽閘 用光阻幕罩,藉以形成一臨 刻’產生良好電容輪廓之結 5-2發明背景: 在隨機記憶體的製程中, 程中’隨著製程技術的進步, 寸會愈來愈趨向於極小化的原、 尤其在動態隨機記後體的製 可以預見的’未來的元件尺 子尺寸。 目前生產線上的線寬已達次微米的寬度,如〇.丨8微米 。而製造成品之目標亦往半導體之高積集度邁進。回顧近 十數年,自有電腦的產生以來,因隨機記憶體(Ram)廣泛 的使用於各相關範圍,使得需求量快速增加β特別是應用 於電腦硬體之資訊產業。同時更不只使用於資訊產業,一 般亦應用於大型積體電路(LSI)與極大型積體電路(VLSI) 及超大型積體電路(ULSI)方面。無疑地,即使下—個世紀 來臨’隨機記憶體(RAM)之製程技術仍然佔有資訊產業中 相當重要的地位。p43259 9 Five 'Description of the invention " ---- 5 -1 Field of the invention: The present invention relates to a method for actively purifying silicon oxynitride, in particular, to etch a curtain in a timely manner, so as to make the structure. In the bulk circuit manufacturing process, the photoresist mask for the polysilicon gate is removed to form a knot that produces a good capacitance profile. 5-2 Background of the Invention: In the process of random memory, during the process, with the progress of process technology, Inch will increasingly tend to minimize the original, especially in the dynamic random postscript system foreseeable 'future element ruler size. At present, the line width of the production line has reached the width of the sub-micron, such as 0.1 micron. The goal of manufacturing finished products is also moving towards the high accumulation of semiconductors. Looking back on the past ten years or so, since the birth of the computer, because of the extensive use of random memory (Ram) in various related areas, the demand has increased rapidly, especially in the information industry of computer hardware. At the same time, it is not only used in the information industry, it is also commonly used in large integrated circuit (LSI), very large integrated circuit (VLSI), and ultra large integrated circuit (ULSI). Undoubtedly, even in the next century, the process technology of random memory (RAM) will still occupy a very important position in the information industry.
"F4 32 59 9 五 '發明說明(2) 在製程中,化學上的蝕刻技術(Chemicaj[ 其中不可或,步驟之-。-般傳統上對於所謂的硬光ί 層Uard Mask)去除時,如氮氧化矽化合物,多以加 800 C的熱構酸(H3P〇4)作為製程令的#刻液以進行去除…。 若以氮氧化矽(以卯)作為硬光罩時, 氧化石夕層較易在除去時,因為職(Gveretching^之=氣 如第一A圊至第—B圈’已摻雜多晶石夕閉極! 2會同時被去陝 變形’產生不良輪廓。其他圖中標號分別& :工〇是半導‘ 底材,1〗是閘氧化層且1 4是氮氧化矽層。 / ’隹ί 土所述’儘管氮氧化矽化合物對整體製程較好;但 除E氧化石夕化合物的過程時,若無法有效控制钱 d製程的過蝕現象’以致多晶矽閘極 進而影響多晶矽間極的功能。 又以€办會 SRAM ί t :上所述’有鑑於改善與提高隨機靜態記憶體( 程技術的需* ’因此,亟待-新製程方法及其 1改善上述之問題’並改善元件品質及其製 5-3發明目的及概述: r4 3259 9 五、發明說明(3) 鑒於上述之發明背景中’傳統因不當蝕刻的諸多缺點 ,本發明提供一方法,利用光阻幕罩,藉以形成一臨時性 的蝕刻幕罩,以便進行蝕刻,產生良好多晶矽閘極輪廓之 結構。 本發明的另一目的在改善與提高隨機靜態記憶體( SRAM )之製程技術的需求,尤其是面對下一世代的深次微 米時代。 本發明的再一目的,係用以在晶圓代工廠中,半導體 積體電路製程之尚要求與高良率,更可有效減低製造成本 根據以上所述之目的,本 製程中移去多晶矽閘極的氮氧 驟。首先,提供一半導體底材 /、 未推雜多晶碎閘極形成於 抗反射層(Anti-Reflection) 接著’塗佈一光阻層於底材 用反向光罩(Reverse Mask)除 光阻。跟著,回蝕刻一部份的 側壁與表面。繼而,乾蝕刻氮 化砂層時,其中已摻雜多晶矽 殘留的光阻層保護。再次,移 發明提供了一種在積體電路 化矽的方法,包含了下列步 ’至少有一摻雜多晶矽閘極 其上,及一氮氧化矽層用為 I成於多晶石夕閘極的表面上 與氮氧化石夕層上。再次,使 去大區域多晶矽閘極表面之 ,阻層以露出氮氧化矽層的 氧化矽層,且當移去該氮氣 閘極與未摻雜多晶矽閘極以 去殘留的光阻層直到露出底" F4 32 59 9 Five 'invention description (2) In the process, when the chemical etching technology (Chemicaj [which is not possible, the step of-.-generally traditionally for the so-called hard light layer Uard Mask) is removed, Such as silicon oxynitride compounds, 800 C of thermostructural acid (H3P04) is added as the #etching solution of the process order for removal ... If silicon oxynitride (thallium) is used as the hard mask, it is easier to remove the oxidized stone layer, because the post (Gveretching ^ = Ga such as the first A 圊 to the -B circle 'has been doped with polycrystalline stones Xi closed pole! 2 will be deformed at the same time in Shaanxi to produce bad contours. The symbols in the other figures are &: 工 〇 is a semiconducting substrate, 1 is a gate oxide layer and 14 is a silicon oxynitride layer. / '隹 ί As stated in the soil, 'Although silicon oxynitride compounds are better for the overall process; but in the process of removing E oxide oxide compounds, if the over-etching phenomenon of the QD process cannot be effectively controlled', the polycrystalline silicon gates will affect the polycrystalline silicon interelectrodes. Function. Also in the meeting SRAM ί t: The above mentioned 'in view of the need to improve and improve the random static memory (process technology *'), so urgently-new process methods and 1 to improve the above problems' and improve component quality The purpose and summary of its invention 5-3 invention: r4 3259 9 V. Description of the invention (3) In view of the above-mentioned many disadvantages of traditional etching due to improper etching, the present invention provides a method for using a photoresist curtain to form A temporary etch curtain in order to Etching is performed to produce a structure with a good polysilicon gate profile. Another object of the present invention is to improve and increase the demand for process technology of random static memory (SRAM), especially in the deep submicron era of the next generation. The present invention Another purpose is to reduce the manufacturing cost of semiconductor integrated circuits in wafer foundries and high yields, which can effectively reduce manufacturing costs. According to the purposes described above, the nitrogen of the polycrystalline silicon gate is removed in this process. Oxygen step. First, a semiconductor substrate is provided. An un-doped polycrystalline gate is formed on the anti-reflection layer, and then a photoresist layer is coated on the substrate with a reverse mask. Remove the photoresist. Then, etch back a part of the sidewall and surface. Then, when dry-etching the nitrided sand layer, the photoresist layer that has been doped with polycrystalline silicon remains to be protected. Third, the invention provides a kind of silicon in integrated circuit The method includes the following steps: at least one doped polycrystalline silicon gate electrode, and a silicon oxynitride layer is formed on the surface of the polycrystalline silicon gate electrode and the oxynitride layer. Again, Remove the silicon oxide layer on the surface of the polysilicon gate in a large area to expose the silicon oxide layer of the silicon oxynitride layer, and when the nitrogen gate and the undoped polysilicon gate are removed, remove the remaining photoresist layer until the bottom is exposed.
_ 五、發明說明(4) 材的表面為止。最後,清洗已摻雜多晶石夕閘極與未摻雜多 晶矽閘極及底材的表面。 為讓本發明之上述說明與其他目的,特徵和優點更能 明顯易懂,下文特列出較佳實施例並配合所附圖式,作詳 細說明。 明 說 單 簡 式 圖 第第 至至 圖圖 A A 一二 第第 及。 ; 圖 圖面 面剖 剖續 的連 藝的 技明 知發 習本 為為 圖圖 本發明圖中主要部份之代表符號: 10 半 導 體 底 材 11 閘 氧 化 層 12 已 換 雜 多 晶 矽 閘 極 13 未 摻 雜 多 晶 矽 閘 極 14 氮 氧 化 矽 20 半 導 體 底 材 21 閘 氧 化 層 22 - 已 摻 雜 多 晶 矽 閘 極 23 未 摻 雜 多 晶 矽 閘 極 23-A 大 區 域 多 晶 矽 閘_ 5. Description of the invention (4) Up to the surface of the material. Finally, the surfaces of the doped polysilicon gate and the undoped polysilicon gate and the substrate are cleaned. In order to make the above description and other objects, features and advantages of the present invention more comprehensible, the preferred embodiments are listed below and described in detail with the accompanying drawings. Explain that the list is simple and the figures from the first to the first figure A A 12 and the second. The drawings of the Lian Yi technical know-how published by the drawings are the representative symbols of the main parts in the drawings of the present invention: 10 semiconductor substrate 11 gate oxide layer 12 polysilicon gates doped 13 doped Heteropolycrystalline silicon gate 14 Silicon oxynitride 20 Semiconductor substrate 21 Gate oxide 22-Doped polycrystalline silicon gate 23 Undoped polycrystalline silicon gate 23-A Large area polycrystalline silicon gate
w 酽4 3259 9 五、發明說明(5) 26 氮氧化矽 27 殘留的光阻層 5-5發明詳細說明: 以下疋本發明的描述。本發明的描述會先配合以一示 範結構做參考^ —些變動和本發明的優點會在之後描述, 且製造的較佳方法會於隨後討論。 再者’雖然本發明以數個 不會限制本發明的範圍或應用 薄介電層’應該明瞭的是主要 代。因此,本發明的半導體元 些元件包括證明本發明和呈現 用性。且即使本發明係藉由舉 實施例來描述,但是本發明並 此外’凡其它未脫離本發明所 改變或修飾,均包含在本發明 廣之疋義來解釋本發明之範圍 類似結捐:。 實施例來教導,但這些描述 。而且,雖然這些例子使用 的部份可能以相關的部份取 件不會限制結構的說明。這 的較佳實施例之實用性和應 例的方式以及舉出一個較佳 不限定於所舉出之實施例。 揭示之精神下所完成之等效 之申請專利範圍内。應以最 ’藉以包含所有這些修飾與w 酽 4 3259 9 V. Description of the invention (5) 26 Silicon oxynitride 27 Residual photoresist layer 5-5 Detailed description of the invention: The following is a description of the present invention. The description of the present invention will first be made with reference to an exemplary structure. Some changes and advantages of the present invention will be described later, and the preferred method of manufacturing will be discussed later. Furthermore, although the present invention is not limited to the scope or application of the present invention, it should be understood that the thin dielectric layer is the main generation. Therefore, the semiconductor element of the present invention includes proof of the present invention and its applicability. And even though the present invention is described by way of examples, the present invention and in addition, 'any other changes or modifications without departing from the present invention are included in the broad meaning of the present invention to explain the scope of the present invention. Examples to teach, but these are described. Also, although the parts used in these examples may be taken as related parts, the explanation of the structure is not limited. The practicality of this preferred embodiment and the manner in which it should be applied, as well as listing a preferred one, are not limited to the examples given. Within the scope of equivalent patent application completed under the spirit of disclosure. Should be used to include all of these modifications and
在本發明的較佳實施例中 f多晶砂閘極的氮氧化矽的方 °兒明並配合如第二Λ圖至第二F ,此種在積體電路製程中移 法,至少包含了下列步驟’ 圖所示,為本發明的連續剖In the preferred embodiment of the present invention, the formula of the silicon oxynitride of the f polycrystalline sand gate is shown in the second figure to the second F. This method of shifting the integrated circuit manufacturing process includes at least The following steps are shown in the figure.
Γ432Β9 9 五、發明說明(6) 面圖。 首先,在本發明的較佳實施例中,如第二A圖所示, 提供一半導體底材20,至少有一已摻雜多晶矽閘極22與一 未摻雜多晶石夕問極23形成於其上’及一氮氧化石夕層26用為 抗反射(Anti-Reflection)層’且形成於已摻雜多晶砂閘 極22與未摻雜多晶矽閘極23的表面上。而標號21為閘氧化 層。 接著,如第二B圖所示,以傳統的光阻塗佈法,鍍— 光阻層27於底材20與氮氧化矽層26上。 再次’如第二C圖所示,以傳統的氧電漿蝕刻法,移 去在大區域多晶石夕閘極表面23-A上之光阻層。 跟著,如第二D圖所示’回蝕刻一部份的光阻層2 7以 露出It氧化石夕層2 6的側壁與表面。 ’如圖所示,以敗化碳化合物乾钮刻氮氧 化夕層26,且虽移去該氮氧化矽層26時,其中已 矽閘極22與未摻雜多晶矽閘極23以 ;件曰曰 氣化二碳(W,其⑽心整數。且其=^能或量、Γ432Β9 9 V. Description of the invention (6) Plan view. First, in the preferred embodiment of the present invention, as shown in FIG. 2A, a semiconductor substrate 20 is provided. At least one doped polycrystalline silicon gate electrode 22 and an undoped polycrystalline silicon gate electrode 23 are formed at The 'and oxynitride layer 26 is used as an Anti-Reflection layer' and is formed on the surfaces of the doped polycrystalline silicon gate 22 and the undoped polycrystalline silicon gate 23. Reference numeral 21 is a gate oxide layer. Next, as shown in FIG. 2B, a conventional photoresist coating method is used to plate a photoresist layer 27 on the substrate 20 and the silicon oxynitride layer 26. Again 'as shown in Figure 2C, the photoresist layer on the surface 23-A of the polycrystalline silicon gate is removed by a conventional oxygen plasma etching method. Then, as shown in FIG. 2D, a portion of the photoresist layer 27 is etched back to expose the sidewall and surface of the It oxide layer 26. 'As shown in the figure, the oxynitride layer 26 is etched with a dried carbon compound dry button, and although the silicon oxynitride layer 26 is removed, the silicon gate electrode 22 and the undoped polycrystalline silicon gate electrode 23 are included; Said gasification of two carbons (W, which is a whole heart number. And its = ^ energy or amount,
第9頁 五、發明說明(7) 為可調整。 再次,如第二F圖所示,以於 殘留的光阻層27直到露出底材^ 除法(Dry strip)移去 的表面為止。 最後,再如第二F1圖所示, 已摻雜多晶矽閘極22與未摻# , a Uean方法清洗 20的表面。 禾4雜夕晶石夕閘極23,23-A及底材 II於在前述之發明背哥中, 點’本發明提供了 —較佳方法,利用光:::刻:諸多缺 -臨時性的蝕刻幕[以便進行蝕刻。其ί:是藉以形成 1 ·可有效保護多晶砂閘極不受損害。 2.可有效避免多晶矽閘極的剝離問題。 且正如本發明的另一目的,在於改善 古 工 記憶體(SRAM)之製程技術的需求,尤其是面阿,機靜態 深次微米時代。且本發明的再一目的,係用以J:世代的 廠中,半導體積體電路製程之高要求與高良^在晶圓代 故本發明中’此種在積體電路製程中移去 的氮氧化矽的方法,至少包含了下列步驟。首ea矽閘極 半導體底材’至少有一摻雜$異劢關炻與—夫 提供一 、衣6雜多晶矽 32 5 9 9 五、發明說明(8) 閘極形成於其上, An t i-Ref lection) 一光阻層於底材與 Reverse Mask )除 ,回蝕刻一部份的 。繼而,乾蝕刻氮 其中已摻雜多晶矽 層保護。再次,移 止。最後,清洗已 底材的表面。 以上所述僅為 定本發明之申請專 精神下所完成之等 專利範圍内。 及氮氧化矽層用為抗反射層( 形成於多晶矽閘極的表面上。接 氮氧化矽層上。再次,伯田e & 敏 耳工 丹-人,使用反向光罩 去大區域多晶矽閘極表面之光阻。跟 光阻層以露出氮氧化矽層的側壁與表面 氧化矽層,且當移去該氮氧化矽層時, 開極與未摻雜多晶矽閘極以殘留的光阻 去殘留的光阻層直到露出底材的表面為 擦雜多晶矽閘極與未摻雜多晶矽閘極及 本發明之較佳實施例而已,並非用以限 利範圍;凡其它未脫離本發明所揭示之 致改變戒修飾’均應包含在下述之申請Page 9 5. Description of the invention (7) is adjustable. Again, as shown in FIG. 2F, the remaining photoresist layer 27 is exposed until the surface removed by the substrate strip (Dry strip) is exposed. Finally, as shown in the second F1 diagram, the surface of the doped polysilicon gate 22 and the undoped # 20 are cleaned by a Uean method. He 4 miscellaneous spar spar gate 23, 23-A and substrate II In the aforementioned invention, point 'the present invention provides-a better method, using light ::: engraving: many defects-temporary The etching curtain [for etching. Its ί: is used to form 1 · It can effectively protect the polycrystalline sand gate from damage. 2. It can effectively avoid the problem of polysilicon gate stripping. And just like another object of the present invention, it is to improve the needs of the process technology of ancient memory (SRAM), especially the surface, deep static submicron era. And another object of the present invention is to use J: the high requirements and high quality of semiconductor integrated circuit manufacturing process in the generation of the factory ^ In the wafer generation, the present invention 'this nitrogen removed in the integrated circuit manufacturing process The method of silicon oxide includes at least the following steps. The first ea silicon gate semiconductor substrate has at least one doped polyisocyanate, and the couple provides one, six heteropoly silicon 32 5 9 9 V. Description of the invention (8) The gate is formed on it, An t i- Ref lection) A photoresist layer is removed from the substrate and Reverse Mask, and a part of it is etched back. Then, dry-etched nitrogen was protected by doped polycrystalline silicon layers. Again, stop. Finally, clean the surface of the substrate. The above are only within the scope of the patents completed under the spirit of the application of the present invention. And the silicon oxynitride layer is used as an anti-reflection layer (formed on the surface of the polycrystalline silicon gate. It is connected to the silicon oxynitride layer. Again, Boda e & Miner Gongdan-ren, uses a reverse mask to remove large area polycrystalline silicon Photoresist on the gate surface. Follow the photoresist layer to expose the sidewall and surface silicon oxide layer of the silicon oxynitride layer, and when the silicon oxynitride layer is removed, the open electrode and the undoped polycrystalline silicon gate with residual photoresist The remaining photoresist layer is removed until the surface of the exposed substrate is doped polycrystalline silicon gate and undoped polycrystalline silicon gate and the preferred embodiment of the present invention, which is not intended to limit the scope of profit; all others do not depart from the disclosure of the present invention All changes or modifications shall be included in the following application
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