A7 B7 432.523 5 8 5 9 twf _ doc / Ο Ο 6 五、發明說明（/ ) 本發明是有關於一種半導體元件結構的製造’且特別 适有關於一種可以增加化學機械硏磨製程窗口的方法’同 時可以簡化微影製程。 在製造積體電路的元件時，在製造過程的一個或多個 階段中，常常需要自元件的表面上移除一些材料’並且在 進行後續步驟之前對各個材料層進行平坦化。以化學機械 硏磨作爲移除及平坦化材料的方法，已經越來越頻繁。此 方法是在硏磨表面固定被硏磨的晶圓，在硏漿（slun_y) 的存在下以一控制好的壓力進行所謂的化學機械硏磨法。 硏漿通常具有一化學活性成分（例如酸或鹼）和一機械活 性及硏磨顆粒成分（例如細緻的二氧化矽顆粒）。雖然正 確的反應機構尙不完全淸楚，但是化學反應和機械硏磨則 促成了其硏磨及平坦化過程，使其可以應用在金屬層和介 電層的平坦化。 舉例來說，在一基底的內部和上面形成場效應電晶體、 二極體或電晶體，接著在積體電路元件的表面上，沉積第 一絕緣材料平面。接觸窗開口（ contact holes )或介層 窗ί vias )的圖案是指穿越該第一絕緣材料，再以蝕刻微 影製程形成介層窗。 因爲某些作爲配線的金屬（例如鋁），當其塡入介層 窗之內時，無法提供合適的塡充性，所以通常是以化學氣 相沉積法（chemical vapor deposition)將鎢沉積並塡 充於介層窗之內。以化學氣相沉積法使鎢沉積於介層窗之 內時，將在絕緣材料的表面和穿越該絕緣材料的介層窗之 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公f ) {諳先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -I n ^ I I f IiT'J1]111111 ί 1 — — — — — — ί — — — — — — — [ — — — l· — — . 432523 5859twf . d.〇c/〇〇6 五、發明說明（之） 內形成一層鎢。在介層窗塡滿後，移除溢出介層窗的鎢層， 並且在介電層和介層窗的表面上沉積鋁作爲配線。該層鎢 nJ以使用回触刻（e t ch back )的步驟將其移除，例如反 應性離子融刻法（reactive ion etching)。此反應性離 子蝕刻法會對鎢造成過度蝕刻並且自介層窗之內移除鎢。 這將會造成介層窗之內凹的鎢金屬與隨後沉積而作爲配線 層的鋁金屬之間的接觸不良。此外，在回蝕刻時產生之微 塵沉積在晶片表面，將導致元件良率之降低。進行回蝕刻 步驟之外的另一種選擇，則是以化學機械硏磨法來移除過 多的鶴。 傳統式鎢化學機械硏磨法包括兩個步驟。第一個步驟， 晶圓在第一硏磨階段是以一種含低pH値氧化劑的硏漿， 自絕緣層的表面移除過多的鎢層。在下面的絕緣層可作爲 第一化學機械硏磨法的触刻終止層（e t ch s t op )。第二 個步驟，將晶圓移至第二硏磨階段，此階段係採用一種高 pH値的硏漿進行硏磨，並且使該絕緣層平坦化。 傳統的方法相信此二步驟均是必須的，因爲第一硏磨 階段在絕緣層中會留下刮痕，此刮痕容易使污染物陷入其 中並在隨後造成導電結構間的短路。第二硏磨步驟則是用 來減緩絕緣層外的刮痕。在理想狀態下，第二硏磨步驟是 爲了使第二硏磨步驟中移除之厚度，至少與第一金屬移除 步驟中所造成最大刮痕的深度相等。 本發明提供一種增加化學機械硏磨製程窗口的方法’ 可以只用一道化學機械硏磨步驟進行鎢的硏磨，而且可以 4 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 7^ · i I I 1 I I I^口，· I I I I ϋ III I I I —— — —-I 1· — — — — — f— — — — — n I I I · A7 B7 4 3 2 6 2 3d〇c/〇〇6 五、發明說明（>) 避免在介電層表面形成刮痕。 本發明提供的增加化學機械硏磨製程窗口的方法，係 在基底表面覆蓋一層平坦化的介電材料，此基底上包括一 些半導體元件結構，比如場效應電晶體、二極體或電晶體 等，再在介電層上覆蓋一層硬度較介電層大的頂蓋層，進 行微影與蝕刻製程，在介電層中形成介層洞開口或接觸窗 開口暴露出部分基底。在頂蓋層上與開口中形成一層鎢， 塡滿開口以後，進行化學機械硏磨製程去除溢出開口的 鎢，直到暴露出頂蓋層爲止。 頂蓋層可以在鎢的化學機械硏磨製成中提供硏磨終止 層的作用，可以增加化學機械硏磨的窗口；且因爲頂蓋層 的硬度高於介電層，鎢的化學機械硏磨並不易在頂蓋層表 面形成刮痕，因此可以省略進行第二道去除介電層上刮痕 的硏磨步驟。 此外，頂蓋層具有低的反射率，在後續沈積並定義內 連線金屬材料於鎢插塞上時，頂蓋層可以作爲定義內連線 金屬材料的抗反射層，因此無須在完成鎢插塞以後，欲沈 積內連線材料之前，再進行一道抗反射層的沈積步驟，因 此可以簡化定義內連線金屬材料的微影製程。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 圖式之簡單說明‘· 第1A圖至第1E圖繪示爲依照本發明一較佳實施例的 本紙張足度適用中國國家標準（CNS)A4規格（210x 297公釐） -----I---一----f--------訂 ---------線 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 43 25 23 5859twf.doc/006 A7 ___B7_____ 五、發明說明（4) 一種增加化學機械硏磨製程窗口的方法流程剖面圖。 圖示標記說明： 100 基底 102 閘極 104 間隙壁 106 BPSG 層 108 介電層 110, ll〇a 頂蓋層 112 接觸窗開口 114, 114a 黏著層/阻障層 116 鎢金屬層 116a 鎮插塞 實施例 第1A圖至第1E圖繪示爲依照本發明一較佳實施例的 一種增加化學機械硏磨製程窗口的方法流程剖面圖。 請參照第U圖，在半導體基底1〇〇上已形成有部分半 導體元件結構，比如電晶體、二極體或場效應電晶體，在 本實施例中以電晶體爲例，圖中在半導體基底100上的結 構包括電晶體的閘極102與位於閘極102兩側的間隙壁 104 ° 以旋塗的方法在半導體基底100上覆蓋一層介電層 106，其材質包括硼磷矽玻璃（BPSG)，形成的介電層1〇6 係塡充在電晶體之間，且具有平坦化的表面，此介電層106 的厚度只要足夠塡滿電晶體之間的空隙即可。 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I-------------> -------訂--------· -- (請先閱讀背面之没意事項再填寫本頁) 32523 ?859twf.do< doc / 0 0 6 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（Γ) fe：者，請參照弟IB圖，形成一層介電層108覆蓋在介 電層106與閘極102上，此介電層108之材質爲四乙基正 砂酸鹽〔TE0S)形成的二氧化矽。形成介電層1〇8以後，再 於其上覆蓋一層頂蓋層U0,厚度約爲500- 1000A，材質 包括氯化矽或氮氧化矽。 請參照第1C圖，進行微影與蝕刻製程，去除部分的頂 蓋層110、介電層〖08與介電層106,藉以在電晶體之間 形成開口 112暴露出半導體基底1〇〇,剩餘的頂蓋層標示 爲丨10 a ° 請參照第1D圖，在上述的結構上形成一層共形的黏著 罾114(或稱爲阻障層），接著形成一層金屬層116於該黏 著層114上，完全塡滿開口 112,金屬層116的材料爲鎢。 其中黏著層114係用以增加金屬層116與介電層108、106 的附著力，也可以防止金屬層116中的材料擴散進入介電 罾108與106，或進入基底100。 請參照第1E圖，進行化學機械硏磨製程，去除溢出開 口 112以外的金屬層116以及阻障層114，直到暴露出頂 蓋層110a爲止，只剩下塡充於開口 112中的鎢插塞116a 與阻障層1 1 4 a。 由於頂蓋層所用的材質硬度大於介電層的二氧化矽， 因此在進行化學機械硏磨時，頂蓋層不僅可以作爲硏磨阻 擋層，增加鎢的化學機械硏磨製程的窗口，也可以保護二 氧化矽的介電層，避免介電層在硏磨過程中產生刮痕。 此外，由於在介電層最上方覆蓋有頂蓋層，因此介電 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------^-------* 裝-------—訂-----I ---線 (請先閱讀背面之注意事項再填寫本頁) 432523 五、發明說明（6) 層不一定要包括硼磷矽玻璃與TEOS的二氧化矽兩種材料， 只要可以提供平坦化的上表面即可，因此在頂蓋層下方也 可以Η形成ν層較厚的硼磷矽玻璃，完全覆蓋基底上的元 件並提供平坦的上表面，而不一定要進行TEOS二氧化政 的沈積步驟。 再者，由於頂蓋層具有低的反射率，當後續製程在鶴 插塞h:方形成金屬內連線時，必須進行金屬的定義，此時 頂蓋層可以作爲抗反射層，因此無須在完成鎢插塞以後， 欲沈積內連線材料之前，再進行一道抗反射層的沈積步 驟，如此一來可以簡化金屬微影製程的步驟。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內t當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) n f— .^1 經濟部智慧財產局員工消費合作社印製 8 本纸張尺度適用中國國家標準（CNS)A4規格（210x297公爱） 線！·----— I —-----：——^——：-----A7 B7 432.523 5 8 5 9 twf _ doc / Ο Ο 6 6. Description of the invention (/) The present invention relates to the manufacture of a semiconductor element structure 'and is particularly applicable to a method that can increase the chemical mechanical honing process window' At the same time, the lithography process can be simplified. When manufacturing a component of an integrated circuit, it is often necessary to remove some materials' from the surface of the component during one or more stages of the manufacturing process and to planarize the individual material layers before proceeding to the subsequent steps. Chemical mechanical honing has been used more and more frequently as a method of removing and planarizing materials. In this method, the honing wafer is fixed on the honing surface, and a so-called chemical mechanical honing method is performed under a controlled pressure in the presence of slun_y. Mortars usually have a chemically active ingredient (such as an acid or base) and a mechanically active and honing particulate component (such as fine silica particles). Although the correct reaction mechanism is not completely clear, chemical reactions and mechanical honing have contributed to its honing and planarization processes, making it applicable to the planarization of metal and dielectric layers. For example, a field-effect transistor, a diode, or a transistor is formed inside and on a substrate, and then a first insulating material plane is deposited on the surface of the integrated circuit element. The pattern of contact hole openings (vias) refers to passing through the first insulating material and forming an interlayer window by an etching lithography process. Because some metals (such as aluminum) used as wiring do not provide proper filling properties when they are inserted into the interlayer window, tungsten is usually deposited by chemical vapor deposition. Fill in the interlayer window. When chemical vapor deposition is used to deposit tungsten in the interlayer window, the paper size of the insulating material on the surface of the insulating material and the interlayer window passing through the insulating material shall be in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm f) {Read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -I n ^ II f IiT'J1] 111111 ί 1 — — — — — — ί — — — — — — — [— — — L · — —. 432523 5859twf. D.〇c / 〇〇6 5. Description of the invention (a) A layer of tungsten is formed. After the dielectric window is full, the tungsten layer overflowing the dielectric window is removed, and aluminum is deposited on the surface of the dielectric layer and the dielectric window as wiring. This layer of tungsten nJ is removed in a step using e t ch back, such as reactive ion etching. This reactive ion etch process causes excessive etching of tungsten and removes tungsten from the interlayer window. This will cause poor contact between the recessed tungsten metal in the via and the aluminum metal which is subsequently deposited as the wiring layer. In addition, the dust generated during the etch-back is deposited on the wafer surface, which will lead to a reduction in the yield of the device. An alternative to the etch-back step is to remove too many cranes by chemical mechanical honing. Traditional tungsten chemical mechanical honing involves two steps. In the first step, in the first honing stage of the wafer, a tungsten slurry containing a low pH oxidant is used to remove an excessive tungsten layer from the surface of the insulating layer. The underlying insulating layer can be used as an etching stop layer (e t ch s t op) of the first chemical mechanical honing method. In the second step, the wafer is moved to a second honing stage. This stage is honing with a high-pH honing slurry, and the insulating layer is planarized. The traditional method believes that both steps are necessary because the first honing stage will leave scratches in the insulating layer, and this scratch will easily cause contaminants to become trapped therein and then cause short circuits between conductive structures. The second honing step is used to reduce scratches outside the insulation layer. Ideally, the second honing step is to make the thickness removed in the second honing step at least equal to the depth of the largest scratch caused by the first metal removing step. The present invention provides a method for increasing the window of the chemical mechanical honing process. The tungsten honing can be performed with only one chemical mechanical honing step, and the paper size can be adapted to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). (%) (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 7 ^ · i II 1 III ^, · IIII ϋ III III —— — —-I 1 · — — — — — F — — — — — n III · A7 B7 4 3 2 6 2 3doc / 〇〇6 5. Description of the invention (&); Avoid scratches on the surface of the dielectric layer. The method for adding a chemical mechanical honing process window provided by the present invention is to cover a surface of a substrate with a layer of planarized dielectric material, and the substrate includes some semiconductor element structures, such as field effect transistors, diodes, or transistors, etc. Then, the dielectric layer is covered with a capping layer having a greater hardness than the dielectric layer, and a lithography and etching process is performed to form a dielectric hole opening or a contact window opening in the dielectric layer to expose a part of the substrate. A layer of tungsten is formed on the capping layer and the opening. After the opening is filled, a chemical mechanical honing process is performed to remove tungsten that overflows the opening until the capping layer is exposed. The capping layer can provide the function of a honing stop layer in the chemical mechanical honing of tungsten, and can increase the window of chemical mechanical honing; and because the hardness of the capping layer is higher than that of the dielectric layer, the chemical mechanical honing of tungsten It is not easy to form scratches on the surface of the capping layer, so a second honing step to remove scratches on the dielectric layer can be omitted. In addition, the capping layer has a low reflectance. When subsequently depositing and defining the metal interconnect material on the tungsten plug, the capping layer can be used as an anti-reflection layer defining the metal interconnect material, so there is no need to complete the tungsten plug. After plugging, before the interconnection material is to be deposited, an anti-reflection layer deposition step is performed, so the lithography process of defining the interconnection metal material can be simplified. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description as follows: Brief description of the drawings' · Figure 1A to Figure 1E shows that the paper is fully compliant with the Chinese National Standard (CNS) A4 (210x 297 mm) according to a preferred embodiment of the present invention ----- I --- 一 ---- f- ------- Order --------- Line (Please read the notes on the back before filling out this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Manufacturing 43 25 23 5859twf.doc / 006 A7 ___B7_____ V. Description of the invention (4) A cross-sectional view of a method for adding a chemical mechanical honing process window. Description of icons: 100 substrate 102 gate 104 spacer 106 BPSG layer 108 dielectric layer 110, 110a cap layer 112 contact window opening 114, 114a adhesion layer / barrier layer 116 tungsten metal layer 116a ball plug implementation Examples FIGS. 1A to 1E are cross-sectional views of a method for adding a chemical mechanical honing process window according to a preferred embodiment of the present invention. Please refer to FIG. U. Some semiconductor element structures, such as transistors, diodes, or field effect transistors, have been formed on the semiconductor substrate 100. In this embodiment, the transistor is used as an example. The structure on 100 includes a gate 102 of a transistor and a spacer 104 on both sides of the gate 102. A semiconductor layer 100 is covered with a dielectric layer 106 by a spin coating method, and the material includes borophosphosilicate glass (BPSG). The formed dielectric layer 106 is filled between the transistors and has a flat surface. The thickness of the dielectric layer 106 can be sufficient to fill the gap between the transistors. 6 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) I ------------- > ------- Order ------ -·-(Please read the unintentional matter on the back before filling out this page) 32523? 859twf.do < doc / 0 0 6 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy : Please refer to the IB diagram to form a dielectric layer 108 covering the dielectric layer 106 and the gate electrode 102. The material of this dielectric layer 108 is silicon dioxide formed by tetraethyl orthosaltate (TE0S). . After the dielectric layer 108 is formed, it is covered with a capping layer U0 with a thickness of about 500-1000A, and the material includes silicon chloride or silicon oxynitride. Referring to FIG. 1C, the lithography and etching process is performed, and a part of the cap layer 110, the dielectric layer 08 and the dielectric layer 106 are removed, so that an opening 112 is formed between the transistors 112 to expose the semiconductor substrate 100, and the remaining The capping layer is labeled 丨 10 a ° Please refer to Figure 1D. On the above structure, a conformal adhesive layer 114 (or a barrier layer) is formed, and then a metal layer 116 is formed on the adhesive layer 114. , The opening 112 is completely filled, and the material of the metal layer 116 is tungsten. The adhesive layer 114 is used to increase the adhesion between the metal layer 116 and the dielectric layers 108 and 106. It can also prevent the material in the metal layer 116 from diffusing into the dielectric ions 108 and 106 or into the substrate 100. Referring to FIG. 1E, a chemical mechanical honing process is performed to remove the metal layer 116 and the barrier layer 114 other than the overflow opening 112 until the cap layer 110a is exposed, leaving only tungsten plugs filled with the opening 112. 116a and barrier layer 1 1 4 a. Because the material used in the cap layer is harder than the silicon dioxide of the dielectric layer, when performing chemical mechanical honing, the cap layer can not only serve as a honing barrier layer, but also increase the window of the chemical mechanical honing process of tungsten. Protect the silicon dioxide dielectric layer from scratches during the honing process. In addition, the top layer of the dielectric layer is covered with a capping layer, so the paper size of the dielectric paper applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ------ ^ ----- -* Install --------- Order ----- I --- line (please read the notes on the back before filling this page) 432523 V. Description of the invention (6) The layer does not necessarily include boron Phosphosilicate glass and TEOS silicon dioxide materials, as long as they can provide a flat upper surface, so under the top cap layer can also be formed ν thicker borophosphosilicate glass, completely covering the components on the substrate A flat upper surface is provided without having to perform a TEOS dioxide deposition step. Furthermore, because the cap layer has a low reflectivity, when the subsequent process forms a metal interconnect at the crane plug h: side, the definition of the metal must be made. At this time, the cap layer can be used as an anti-reflection layer, so there is no need to After the tungsten plug is completed, an anti-reflection layer deposition step is performed before the interconnection material is to be deposited, so that the steps of the metal lithography process can be simplified. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling this page) n f—. ^ 1 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 8 This paper size applies to China National Standard (CNS) A4 (210x297 public love) line! · ----— I —-----: —— ^ ——: -----