TW431069B - High-speed data buffer - Google Patents

High-speed data buffer

Info

Publication number
TW431069B
TW431069B TW089106389A TW89106389A TW431069B TW 431069 B TW431069 B TW 431069B TW 089106389 A TW089106389 A TW 089106389A TW 89106389 A TW89106389 A TW 89106389A TW 431069 B TW431069 B TW 431069B
Authority
TW
Taiwan
Prior art keywords
edge
correct
data
buffer
assured
Prior art date
Application number
TW089106389A
Other languages
English (en)
Inventor
Shr-Ping Gau
Original Assignee
Via Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Via Tech Inc filed Critical Via Tech Inc
Priority to TW089106389A priority Critical patent/TW431069B/zh
Priority to US09/827,136 priority patent/US6882192B2/en
Application granted granted Critical
Publication of TW431069B publication Critical patent/TW431069B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
TW089106389A 2000-04-07 2000-04-07 High-speed data buffer TW431069B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW089106389A TW431069B (en) 2000-04-07 2000-04-07 High-speed data buffer
US09/827,136 US6882192B2 (en) 2000-04-07 2001-04-05 High-speed data buffer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW089106389A TW431069B (en) 2000-04-07 2000-04-07 High-speed data buffer

Publications (1)

Publication Number Publication Date
TW431069B true TW431069B (en) 2001-04-21

Family

ID=21659311

Family Applications (1)

Application Number Title Priority Date Filing Date
TW089106389A TW431069B (en) 2000-04-07 2000-04-07 High-speed data buffer

Country Status (2)

Country Link
US (1) US6882192B2 (zh)
TW (1) TW431069B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7602871B2 (en) 2005-03-14 2009-10-13 Ntt Docomo, Inc. Mobile communication terminal

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006067852A1 (ja) * 2004-12-24 2006-06-29 Spansion Llc 同期型記憶装置、およびその制御方法
US7068195B1 (en) * 2005-04-29 2006-06-27 National Semiconductor Corporation Accurate sampling technique for ADC
TWI292096B (en) * 2005-10-06 2008-01-01 Via Tech Inc A data buffer system and an access method of a data buffer device
KR102456587B1 (ko) * 2015-11-09 2022-10-20 에스케이하이닉스 주식회사 래치 회로, 그 래치 기반의 이중 데이터 레이트 링 카운터, 하이브리드 카운팅 장치, 아날로그-디지털 변환 장치, 및 씨모스 이미지 센서

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4157587A (en) 1977-12-22 1979-06-05 Honeywell Information Systems Inc. High speed buffer memory system with word prefetch
US4823259A (en) 1984-06-29 1989-04-18 International Business Machines Corporation High speed buffer store arrangement for quick wide transfer of data
US5043921A (en) 1989-10-23 1991-08-27 International Business Machines Corporation High speed Z-buffer control
US5250858A (en) * 1992-02-19 1993-10-05 Vlsi Technology, Inc. Double-edge triggered memory device and system
US5799048A (en) * 1996-04-17 1998-08-25 Sun Microsystems, Inc. Phase detector for clock synchronization and recovery
US5789953A (en) * 1996-05-29 1998-08-04 Integrated Device Technology, Inc. Clock signal generator providing non-integer frequency multiplication
KR100254858B1 (ko) * 1997-06-30 2000-05-01 김영환 액정표시소자의 샘플링펄스 발생회로
US6535045B1 (en) * 1998-07-09 2003-03-18 Intel Corporation Integrated circuit interconnect routing using double pumped circuitry
US6269414B1 (en) * 1998-07-14 2001-07-31 Rockwell Technologies, Llc Data rate doubler for electrical backplane
US6647506B1 (en) * 1999-11-30 2003-11-11 Integrated Memory Logic, Inc. Universal synchronization clock signal derived using single forward and reverse direction clock signals even when phase delay between both signals is greater than one cycle

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7602871B2 (en) 2005-03-14 2009-10-13 Ntt Docomo, Inc. Mobile communication terminal

Also Published As

Publication number Publication date
US6882192B2 (en) 2005-04-19
US20010032322A1 (en) 2001-10-18

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Legal Events

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MK4A Expiration of patent term of an invention patent