TW430900B - Method for producing structures having a high aspect ratio - Google Patents

Method for producing structures having a high aspect ratio

Info

Publication number
TW430900B
TW430900B TW087110890A TW87110890A TW430900B TW 430900 B TW430900 B TW 430900B TW 087110890 A TW087110890 A TW 087110890A TW 87110890 A TW87110890 A TW 87110890A TW 430900 B TW430900 B TW 430900B
Authority
TW
Taiwan
Prior art keywords
mask
produced
aspect ratio
layer
structures
Prior art date
Application number
TW087110890A
Other languages
English (en)
Inventor
Manfred Engelhardt
Volker Weinrich
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Application granted granted Critical
Publication of TW430900B publication Critical patent/TW430900B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0335—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F4/00—Processes for removing metallic material from surfaces, not provided for in group C23F1/00 or C23F3/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Semiconductor Memories (AREA)
  • Drying Of Semiconductors (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Manufacturing Of Electric Cables (AREA)
TW087110890A 1997-09-08 1998-07-06 Method for producing structures having a high aspect ratio TW430900B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19739224 1997-09-08

Publications (1)

Publication Number Publication Date
TW430900B true TW430900B (en) 2001-04-21

Family

ID=7841545

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087110890A TW430900B (en) 1997-09-08 1998-07-06 Method for producing structures having a high aspect ratio

Country Status (6)

Country Link
US (1) US6210595B1 (zh)
EP (1) EP0902461A3 (zh)
JP (1) JPH11154668A (zh)
KR (1) KR19990029609A (zh)
CN (1) CN1211067A (zh)
TW (1) TW430900B (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW430900B (en) * 1997-09-08 2001-04-21 Siemens Ag Method for producing structures having a high aspect ratio
SG79292A1 (en) * 1998-12-11 2001-03-20 Hitachi Ltd Semiconductor integrated circuit and its manufacturing method
US6782610B1 (en) * 1999-05-21 2004-08-31 North Corporation Method for fabricating a wiring substrate by electroplating a wiring film on a metal base
DE10147929C1 (de) * 2001-09-28 2003-04-17 Infineon Technologies Ag Verfahren zum Herstellen einer Halbleiterstruktur und Verwendung des Verfahrens
KR100645041B1 (ko) * 2004-07-12 2006-11-10 삼성전자주식회사 엠아이엠 캐패시터를 갖는 반도체 소자 및 그 형성 방법
DE102005039667A1 (de) * 2005-08-22 2007-03-01 Infineon Technologies Ag Verfahren zum Herstellen einer Struktur mit geringem Aspektverhältnis
US9871044B2 (en) * 2015-11-06 2018-01-16 Micron Technology, Inc. Enhanced charge storage materials, related semiconductor memory cells and semiconductor devices, and related systems and methods
US10562763B2 (en) * 2017-08-28 2020-02-18 Taiwan Semiconductor Manufacturing Co., Ltd. Fence structure to prevent stiction in a MEMS motion sensor
CN111095450A (zh) 2018-08-21 2020-05-01 深圳市为通博科技有限责任公司 电容器及其加工方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4400257A (en) 1982-12-21 1983-08-23 Rca Corporation Method of forming metal lines
US4533430A (en) * 1984-01-04 1985-08-06 Advanced Micro Devices, Inc. Process for forming slots having near vertical sidewalls at their upper extremities
US4702795A (en) 1985-05-03 1987-10-27 Texas Instruments Incorporated Trench etch process
JPS63211740A (ja) * 1987-02-27 1988-09-02 Oki Electric Ind Co Ltd 半導体素子の配線パタ−ン形成方法
JPH0622218B2 (ja) * 1988-08-06 1994-03-23 富士通株式会社 エッチング方法
CA2061119C (en) * 1991-04-19 1998-02-03 Pei-Ing P. Lee Method of depositing conductors in high aspect ratio apertures
JPH0613357A (ja) * 1992-06-25 1994-01-21 Seiko Epson Corp 半導体装置のエッチング方法
US5468340A (en) * 1992-10-09 1995-11-21 Gupta; Subhash Highly selective high aspect ratio oxide etch method and products made by the process
US5258093A (en) * 1992-12-21 1993-11-02 Motorola, Inc. Procss for fabricating a ferroelectric capacitor in a semiconductor device
US5409563A (en) * 1993-02-26 1995-04-25 Micron Technology, Inc. Method for etching high aspect ratio features
JPH07130702A (ja) * 1993-11-08 1995-05-19 Fujitsu Ltd 白金又はパラジウムよりなる金属膜のパターニング方法
JP3101685B2 (ja) * 1995-02-28 2000-10-23 マイクロン・テクノロジー・インコーポレイテッド 再蒸着を用いた構造体の形成方法
KR970054009A (ko) * 1995-12-16 1997-07-31 김주용 반도체 소자의 캐패시터 제조 방법
US5728619A (en) * 1996-03-20 1998-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Selective reactive Ion etch (RIE) method for forming a narrow line-width high aspect ratio via through an integrated circuit layer
US5825609A (en) * 1996-04-23 1998-10-20 International Business Machines Corporation Compound electrode stack capacitor
TW430900B (en) * 1997-09-08 2001-04-21 Siemens Ag Method for producing structures having a high aspect ratio

Also Published As

Publication number Publication date
EP0902461A3 (de) 2000-10-11
EP0902461A2 (de) 1999-03-17
JPH11154668A (ja) 1999-06-08
US6210595B1 (en) 2001-04-03
CN1211067A (zh) 1999-03-17
KR19990029609A (ko) 1999-04-26

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Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees