TW429619B - Method of forming memory cell - Google Patents

Method of forming memory cell

Info

Publication number
TW429619B
TW429619B TW88122930A TW88122930A TW429619B TW 429619 B TW429619 B TW 429619B TW 88122930 A TW88122930 A TW 88122930A TW 88122930 A TW88122930 A TW 88122930A TW 429619 B TW429619 B TW 429619B
Authority
TW
Taiwan
Prior art keywords
layer
substrate
bit line
memory cell
stop layer
Prior art date
Application number
TW88122930A
Other languages
Chinese (zh)
Inventor
Shiang-Lan Lung
Original Assignee
Macronix Int Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Macronix Int Co Ltd filed Critical Macronix Int Co Ltd
Priority to TW88122930A priority Critical patent/TW429619B/en
Application granted granted Critical
Publication of TW429619B publication Critical patent/TW429619B/en

Links

Abstract

This invention provides the method for forming memory cell and at least includes the followings. At first, a substrate is provided and a layer of dielectric structure is formed on substrate. A conduction layer and a polish stop layer are sequentially formed on the dielectric structure layer. Pattern of bit line is defined on substrate and bit line is formed. After that, spacer is formed on sidewalls of conduction layer and polish stop layer, and is followed by performing the salicide process. On the bit line, an oxide layer is filled in. Chemical mechanical polishing process or etching process is then performed onto this oxide layer till reaching the etch stop layer. Finally, the polish stop layer is removed and a word line is formed by depositing a layer of polysilicon.
TW88122930A 1999-12-24 1999-12-24 Method of forming memory cell TW429619B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW88122930A TW429619B (en) 1999-12-24 1999-12-24 Method of forming memory cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW88122930A TW429619B (en) 1999-12-24 1999-12-24 Method of forming memory cell

Publications (1)

Publication Number Publication Date
TW429619B true TW429619B (en) 2001-04-11

Family

ID=21643557

Family Applications (1)

Application Number Title Priority Date Filing Date
TW88122930A TW429619B (en) 1999-12-24 1999-12-24 Method of forming memory cell

Country Status (1)

Country Link
TW (1) TW429619B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100367517C (en) * 2002-02-21 2008-02-06 松下电器产业株式会社 Semiconductor storage device and its manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100367517C (en) * 2002-02-21 2008-02-06 松下电器产业株式会社 Semiconductor storage device and its manufacturing method

Similar Documents

Publication Publication Date Title
WO2013180757A1 (en) Method of fabricating a gate-all-around word line for a vertical channel dram
CN109148258B (en) Method for forming oxide layer
CN100517655C (en) SONOS flash memory and production method thereof
US6686668B2 (en) Structure and method of forming bitline contacts for a vertical DRAM array using a line bitline contact mask
US6316331B1 (en) Method of making dishing-free insulator in trench isolation
CN105304608B (en) Self-aligned contacts part and method
US6391756B1 (en) Semiconductor processing methods of forming contact openings
JP2001044433A (en) Manufacture of semiconductor element
US6960523B2 (en) Method of reducing erosion of a nitride gate cap layer during reactive ion etch of nitride liner layer for bit line contact of DRAM device
US6800525B2 (en) Method of manufacturing split gate flash memory device
TW429619B (en) Method of forming memory cell
US6613648B1 (en) Shallow trench isolation using TEOS cap and polysilicon pullback
KR20000043558A (en) Metallization process of semiconductor device
KR100853477B1 (en) Method for fabricating semiconductor device
KR100575890B1 (en) Method for forming landing plug
KR100846367B1 (en) Method for fabricating Ferroelectric Random Access Memory
CN105405848B (en) Semiconductor device and the method for improving character line resistance and reducing silicide bridge joint
KR100532936B1 (en) Method of manufacture semiconductor device
KR100546059B1 (en) Method for manufacturing semiconductor
KR20040057635A (en) method for fabricating storage node electrodes of capacitor
KR20060071479A (en) Method for manufacturing semiconductor device
KR20010045700A (en) Method for forming gate of semiconductor memory
KR20020096473A (en) Method for fabricating semiconductor device
TW428218B (en) Method for preventing residues of rugged polysilicon
TW329547B (en) The manufacturing method for cylindrical capacitor in memory cell of DRAM

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MK4A Expiration of patent term of an invention patent