TW429532B - Method for preventing short circuit between polysilicon in the self-aligned contact etching process - Google Patents

Method for preventing short circuit between polysilicon in the self-aligned contact etching process

Info

Publication number
TW429532B
TW429532B TW88117477A TW88117477A TW429532B TW 429532 B TW429532 B TW 429532B TW 88117477 A TW88117477 A TW 88117477A TW 88117477 A TW88117477 A TW 88117477A TW 429532 B TW429532 B TW 429532B
Authority
TW
Taiwan
Prior art keywords
semiconductor substrate
polysilicon
layered structure
dielectric
self
Prior art date
Application number
TW88117477A
Other languages
Chinese (zh)
Inventor
Yu-Tsai Lin
Kuen-Lin Wu
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to TW88117477A priority Critical patent/TW429532B/en
Application granted granted Critical
Publication of TW429532B publication Critical patent/TW429532B/en

Links

Abstract

The present invention discloses a method for preventing the short circuit between polysilicon in the self-aligned contact etching process. The method includes the following steps: (1) providing a semiconductor substrate; (2) forming a thin oxide on the semiconductor substrate; (3) form a plurality of layered structure on the thin oxide; (4) employing the plurality of layered structure as a mask for ion implantation in the semiconductor substrate to form a lightly doped drain area; (5) depositing an uniformly covered silicon hydroxide on the plurality of layered structure and the exposed surface of the thin oxide; (6) depositing an insulation layer on the uniformly covered silicon hydroxide; (7) anisotropically etching the insulation layer to form a spacer on the sidewall of each layered structure; (8) employing the plurality of layered structure and spacer as a mask for ion implantation in the semiconductor substrate to form a heavily doped drain area; (9) forming a overlapped polysilicon inter-dielectric on the exposed surface of the entire formed structure; (10) etching the polysilicon inter-dielectric to form a contact between the layered structures to expose a part of the surface of the semiconductor substrate; finally, forming a conductive layer on the polysilicon inter-dielectric and the sidewall of the contact.
TW88117477A 1999-10-11 1999-10-11 Method for preventing short circuit between polysilicon in the self-aligned contact etching process TW429532B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW88117477A TW429532B (en) 1999-10-11 1999-10-11 Method for preventing short circuit between polysilicon in the self-aligned contact etching process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW88117477A TW429532B (en) 1999-10-11 1999-10-11 Method for preventing short circuit between polysilicon in the self-aligned contact etching process

Publications (1)

Publication Number Publication Date
TW429532B true TW429532B (en) 2001-04-11

Family

ID=21642573

Family Applications (1)

Application Number Title Priority Date Filing Date
TW88117477A TW429532B (en) 1999-10-11 1999-10-11 Method for preventing short circuit between polysilicon in the self-aligned contact etching process

Country Status (1)

Country Link
TW (1) TW429532B (en)

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Legal Events

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GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees