TW347560B - Process for producing stacked gate of an integrated circuit and structure thereof - Google Patents

Process for producing stacked gate of an integrated circuit and structure thereof

Info

Publication number
TW347560B
TW347560B TW086105983A TW86105983A TW347560B TW 347560 B TW347560 B TW 347560B TW 086105983 A TW086105983 A TW 086105983A TW 86105983 A TW86105983 A TW 86105983A TW 347560 B TW347560 B TW 347560B
Authority
TW
Taiwan
Prior art keywords
integrated circuit
gate
oxide layer
forming
layer
Prior art date
Application number
TW086105983A
Other languages
Chinese (zh)
Inventor
Jaw-Jye Tsay
Shii-Jonq Suen
Jia-Shyong Tsay
Show-Gwo Wuu
Original Assignee
Taiwan Semiconductor Mfg Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg Co Ltd filed Critical Taiwan Semiconductor Mfg Co Ltd
Priority to TW086105983A priority Critical patent/TW347560B/en
Application granted granted Critical
Publication of TW347560B publication Critical patent/TW347560B/en

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A process for producing stacked gate of an integrated circuit and structure thereof, which comprises the following steps: (a) a substrate, including a semiconductor substrate, a field oxide layer and a gate oxide layer, the field oxide layer being formed on the semiconductor substrate for being used as insulation for components, and the gate oxide layer being located on the semiconductor substrate; (b) cover the gate oxide layer with a polysilicon layer as the gate of the integrated circuit; (c) covering the polysilicon layer with an amorphous silicon layer capable of filling up the cavities on the surface of the polysilicon layer, thereby forming a planar surface; (d) defining a gate region of the integrated circuit by using lithography and etching techniques; (e) forming a side wall on both sides of the gate as a barrier between the gate and the integrated circuit; (f) performing ion implantation thereby forming an active region of the integrated circuit; and (g) performing a self-aligning silicide metal reaction on the surface of the active region of the integrated circuit thereby forming a silicide metal layer as the metal contact of the integrated circuit.
TW086105983A 1997-05-06 1997-05-06 Process for producing stacked gate of an integrated circuit and structure thereof TW347560B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW086105983A TW347560B (en) 1997-05-06 1997-05-06 Process for producing stacked gate of an integrated circuit and structure thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW086105983A TW347560B (en) 1997-05-06 1997-05-06 Process for producing stacked gate of an integrated circuit and structure thereof

Publications (1)

Publication Number Publication Date
TW347560B true TW347560B (en) 1998-12-11

Family

ID=58263983

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086105983A TW347560B (en) 1997-05-06 1997-05-06 Process for producing stacked gate of an integrated circuit and structure thereof

Country Status (1)

Country Link
TW (1) TW347560B (en)

Similar Documents

Publication Publication Date Title
JP4173629B2 (en) Self-aligned power field effect transistor on silicon carbide.
EP1403914A3 (en) Method of making a semiconductor device having trenches
US20060261416A1 (en) Semiconductor device and method of manufacturing the same
JP2005197704A (en) Semiconductor device and manufacturing method therefor
US5460998A (en) Integrated P+ implant sequence in DPDM process for suppression of GIDL
US5994743A (en) Semiconductor device having different sidewall widths and different source/drain depths for NMOS & PMOS structures
EP1100128A4 (en) Semiconductor device and method of manufacture thereof
EP1246258A4 (en) Semiconductor device, method of manufacture thereof, and information processing device
TW356601B (en) Method for making memory cell of self-aligning field plate and structure of the same
TW449836B (en) Manufacturing method and device for forming anti-punch-through region by large-angle-tilt implantation
US5726081A (en) Method of fabricating metal contact of ultra-large-scale integration metal-oxide semiconductor field effect transistor with silicon-on-insulator structure
US7872316B2 (en) Semiconductor device and method of manufacturing semiconductor device
US7285449B2 (en) Semiconductor device manufacture method including process of implanting impurity into gate electrode independently from source /drain and semiconductor device manufactured by the method
US6200846B1 (en) Semiconductor device with capacitor formed on substrate and its manufacture method
TW347560B (en) Process for producing stacked gate of an integrated circuit and structure thereof
US6235566B1 (en) Two-step silicidation process for fabricating a semiconductor device
US20240290617A1 (en) Field-effect transistors with a gate dielectric layer formed on a surface treated by atomic layer etching
EP4421878A1 (en) Field-effect transistors with deposited gate dielectric layers
JPH10242264A (en) Manufacture of semiconductor device
KR980012599A (en) Methods of forming transistors using salicide process technology
TW429532B (en) Method for preventing short circuit between polysilicon in the self-aligned contact etching process
KR100281346B1 (en) Method for manufacturing via holes in doped regions
TW336342B (en) Process for producing mixed model capacitor having a metal silicide layer
KR19980025543A (en) Silicide Formation Method of Semiconductor Device
KR100273685B1 (en) Method for forming semiconductor device

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees