TW288198B - Process of fabricating CMOSFET with short channel - Google Patents

Abstract

A process of fabricating inverted self-aligned field effect transistor comprises the steps of: (1) preparing one semiconductor substrate and doping with first conductive impurity; (2) forming field oxide on the semiconductor substrate, surrounding active area and making each other separate electrically; (3) depositing first conductive layer on the active area and field oxide; (4) depositing first polysilicon on the first conductive layer, and doping with second conductive impurity; (5) depositing first insulator on the first polysilicon layer; (6) in the first insulator and first polysilicon etching opening with vertical side wall until to the first conductive layer surface, in which the opening at least must be located on active area in order to form the gate of field effect transistor on active area; (7) in vertical uni-directioni etching first conductive layer in the opening until substrate surface; (8) in the opening on first insulator depositing one layer of second insulator; (9) wholly etching back the second insulator until the first insulator forms side wall space on vertical side wall of the opening so as to shrink opening size; (10) in the opening implanting first conductive channel ion impurity; (11) on substrate surface of the opening forming gate oxide by thermal oxidization; (12) heating the substrate, making second conductive impurity diffuse outside from first polysilicon through first conductive layer, and forming source/drain doped area in transistor active area; (13) in the second insulator and the opening depositing one second polysilicon, and doping with second conductive impurity; (14) patterning the second polysilicon, leaving portion above the opening, and forming the transistor stack gate; (15) on the stack gate and first insulator depositing third insulator; (16) in the third and first insulator forming contact hole to first polysilicon as contact to source/drain; (17) on the third insulator and in contact opening depositing second conductive layer; (18) patterning the second conductive layer, leaving portion on the contact opening, finishing inverted self-aligned transistor with second conductive layer as source/drain contact.