TW428287B - Manufacturing method for flash memory and the operation method for its erasure - Google Patents

Manufacturing method for flash memory and the operation method for its erasure

Info

Publication number
TW428287B
TW428287B TW087121316A TW87121316A TW428287B TW 428287 B TW428287 B TW 428287B TW 087121316 A TW087121316 A TW 087121316A TW 87121316 A TW87121316 A TW 87121316A TW 428287 B TW428287 B TW 428287B
Authority
TW
Taiwan
Prior art keywords
voltage
erasure
well
manufacturing
flash memory
Prior art date
Application number
TW087121316A
Other languages
English (en)
Inventor
Hau-Ming Li
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to TW087121316A priority Critical patent/TW428287B/zh
Priority to US09/467,372 priority patent/US6329246B1/en
Application granted granted Critical
Publication of TW428287B publication Critical patent/TW428287B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/788Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881Programmable transistors with only two possible levels of programmation
    • H01L29/7883Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/972Stored charge erasure

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
TW087121316A 1998-12-21 1998-12-21 Manufacturing method for flash memory and the operation method for its erasure TW428287B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW087121316A TW428287B (en) 1998-12-21 1998-12-21 Manufacturing method for flash memory and the operation method for its erasure
US09/467,372 US6329246B1 (en) 1998-12-21 1999-12-20 Method for fabricating flash memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW087121316A TW428287B (en) 1998-12-21 1998-12-21 Manufacturing method for flash memory and the operation method for its erasure

Publications (1)

Publication Number Publication Date
TW428287B true TW428287B (en) 2001-04-01

Family

ID=21632397

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087121316A TW428287B (en) 1998-12-21 1998-12-21 Manufacturing method for flash memory and the operation method for its erasure

Country Status (2)

Country Link
US (1) US6329246B1 (zh)
TW (1) TW428287B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10304654A1 (de) * 2003-02-05 2004-08-19 Infineon Technologies Ag Speicherzelle, Speicherzellen-Anordnung und Verfahren zum Herstellen einer Speicherzelle
US7119393B1 (en) * 2003-07-28 2006-10-10 Actel Corporation Transistor having fully-depleted junctions to reduce capacitance and increase radiation immunity in an integrated circuit
US9117832B2 (en) * 2012-06-05 2015-08-25 Phison Electronics Corp. Semiconductor device with physical manipulation detector and corrector
JP6298240B2 (ja) * 2013-03-22 2018-03-20 サイプレス セミコンダクター コーポレーション 半導体装置及びその消去方法
KR102567072B1 (ko) * 2016-03-21 2023-08-17 에스케이하이닉스 주식회사 수평형 바이폴라 접합 트랜지스터를 갖는 안티퓨즈 불휘발성 메모리 소자
US10318071B2 (en) * 2017-03-23 2019-06-11 Intel Corporation Method and apparatus for a blob angle orientation recognition in a touch device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5411908A (en) * 1992-05-28 1995-05-02 Texas Instruments Incorporated Flash EEPROM array with P-tank insulated from substrate by deep N-tank
US5379253A (en) * 1992-06-01 1995-01-03 National Semiconductor Corporation High density EEPROM cell array with novel programming scheme and method of manufacture
KR960012303B1 (ko) * 1992-08-18 1996-09-18 삼성전자 주식회사 불휘발성 반도체메모리장치 및 그 제조방법
US6043123A (en) * 1996-05-30 2000-03-28 Hyundai Electronics America, Inc. Triple well flash memory fabrication process
US6071778A (en) * 1998-02-20 2000-06-06 Stmicroelectronics S.R.L. Memory device with a memory cell array in triple well, and related manufacturing process
US6091101A (en) * 1998-03-30 2000-07-18 Worldwide Semiconductor Manufacturing Corporation Multi-level flash memory using triple well

Also Published As

Publication number Publication date
US6329246B1 (en) 2001-12-11

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Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MK4A Expiration of patent term of an invention patent