TW425579B - Integral thin-film metal resistor with improved tolerance and simplified processing - Google Patents

Integral thin-film metal resistor with improved tolerance and simplified processing Download PDF

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Publication number
TW425579B
TW425579B TW088111519A TW88111519A TW425579B TW 425579 B TW425579 B TW 425579B TW 088111519 A TW088111519 A TW 088111519A TW 88111519 A TW88111519 A TW 88111519A TW 425579 B TW425579 B TW 425579B
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Taiwan
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dielectric layer
film
layer
resistive
resistive film
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TW088111519A
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English (en)
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Gregory J Dunn
Jovica Savic
Allyson Beuhler
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Motorola Inc
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/16Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/167Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed resistors
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01CRESISTORS
    • H01C17/00Apparatus or processes specially adapted for manufacturing resistors
    • H01C17/06Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base
    • H01C17/07Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base by resistor foil bonding, e.g. cladding
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0302Properties and characteristics in general
    • H05K2201/0317Thin film conductor layer; Thin film passive component
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09818Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09881Coating only between conductors, i.e. flush with the conductors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01Tools for processing; Objects used during processing
    • H05K2203/0147Carriers and holders
    • H05K2203/0152Temporary metallic carrier, e.g. for transferring material
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14Related to the order of processing steps
    • H05K2203/1461Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • H05K3/0023Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/022Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
    • H05K3/025Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates by transfer of thin metal foil formed on a temporary carrier, e.g. peel-apart copper
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/04Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
    • H05K3/046Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer
    • H05K3/048Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer using a lift-off resist pattern or a release layer pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/38Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/386Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Conductive Materials (AREA)

Description

A7 425579 B7_____ 五、發明說明(」) 本發明遵照與DARPA簽訂合約第F33615-96-2-1838號受政 府贊助。政府對本發明擁有某種權利。 發明背景 1、 發明頜域 概略而言本發明係關於電路及其製造。特別本發明係關 於相對不複雜的形成具有改良維度容差之薄膜金屬電阻器 之方法。 2、 先前技術之説明 薄膜金屬電阻器通常係藉眞空沉積於小基板而用於混成 電子電路。常用基於鎳之組合物例如鎳-鉻以及其它材料例 如矽化絡及氮化钽。鎳-磷薄膜電阻器也曾經由層合大片 Ni-P-鍍敷銅箔於印刷電路板組成體形成,接著爲扣除蚀刻 步驟來界定電阻器。此等扣除蝕刻方法由於各向同性濕式 蚀刻之凹割效果具有維度控制不良的缺點。爲了確保電阻 器縱橫比(L/W)與電阻間的線性關係,單一電阻器寬度常 用於電路之全部縱橫比,其對電路布局或設計造成非期望 的限制。扣除蝕刻法之第二缺點爲電阻器金屬之化學蝕刻 劑與典型用於電路板製造之蝕刻劑不同。 如此希望有一種方法其可減少金屬積體電阻器之製程複 雜度同時促進電阻容差之準確控制。 ".發明概述 根據本發明,提供一種製造具有預定製程的維度特性之 電阻器及特別金屬電阻膜之微_電子總成之方法。該方法通 常包括施加光敏性電介質之基板形成介電層。介電層經光 \紙張尺國家標準(CNS)A4規格(210 X 297公釐) •in--— -裝.5 — <請先閱讀背面之注意事項再.fi本頁) 訂5*丨? 經濟部智慧財產局員工消費合作社印製 425579 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(2) 成像而使於基板第一區之介電層之第—部分爲可溶,而於 基板第二區之介電層之第二部分爲不可溶。然後電阻膜施 用於介電層,介電層經顯像同時去除第—部分及覆於第一 部分上之電阻膜部分,故部分電阻膜殘留於第二部分上形 成電阻器。另-種製程順序係於介電層曝光於照射前施加 電阻膜’然後經由電阻膜曝光介電層。此種技術要求電阻 膜厚度及電磁性質許可電磁穿透電阻膜而允許光敏性電介 質之光敏特性激發。 根據本發明,電阻膜較佳爲多層膜其包括一電阻膜如Nip ,NiCr或其它含鎳合金及襯層如銅層。—旦層合至介電層 ,銅層可使用習知蝕刻劑選擇性去除而留下電阻層於介電 層表面上。另外,電阻膜可藉無電鍍敷或藉蒸鍵或激散: 介電層上形成。本發明方法也較佳包括於顯像第一介電層 後施加第二介電層於第一介電層上,於第二介電層形成開 口而曝光部分剩餘電阻膜,然後鍍敷電阻膜之曝光部分形 成電連接至膜之端子。 根據則X,#父佳本發明之方法僅包含使用習知蚀刻劑進 行單一金屬蝕刻俾便選擇性去除層合膜襯層。因此本發明 不會如同先前技術之形成金屬積體電阻器之方法般,由於 使用非標準軸刻劑之蚀刻步驟變得複雜化。要緊地’ 本部分與介電層可溶部分之過程期 間可定。由於此項技術結果,可準 確控制電阻器寬度而參赛凹割。最後,本發明方法使 用光界定達成對電阻器ϊ確安置端子,因而準確決定電阻 -5- ---------1Ί 裝---- (請先閱讀背面之注意事項再,,本頁 訂: -線 卜紙張尺度適用中國國家標準(C_NS)A4規格— X 297公釐) 425579 經濟部智慧財產局員工消費合作杜印製 Α7 Β7 五、發明說明(3) 器之電長度。結果藉由本發明方法製造的金屬積體電阻器 之維度及電阻容差比較使用先前技術方法可能達成之容差 更爲緊密。 其π本發明之目的及優點由後文詳細説明將更爲明瞭。 圖式之簡犟説明 則述及其它本發明之優點由後文説明連同附圖考慮將顯 然自明,附圖中: 圖1至3爲透視圖及圖4爲剖面圖顯示根據本發明之第一 具體例形成金屬積體電阻器之製程步驟; 圖5至8爲透視圖顯示根據本發明之第二具體例形成金屬 積體電阻器之製程步驟;及 圖9爲藉由圖1至4或圖5至8之製程步驟製成的環狀電阻 器之透梘圖。 較佳具體例之詳細説明 根據本發明處理之電路板〗〇具有金屬積體電阻器〗2部分 表示於圖1至4。如圖4所示,電阻器12包含電阻膜14及一 對終端16其決定電阻器12之電長度。容後參照圖】至4詳細 説明,電阻器1 2之準確物理維度可使用本發明達成,故電 阻器12具有準確控制的電阻容差^雖然特定電阻器終端配 置顯示於圖4,但業界人士暸解可做無數變化及修改,包括 圖8及9之修改,此等變化及修改係屬本發明之範圍。 參照圖1 ’電路板10顯示爲有一基板18,於其上形成一 介電層20。基板18可爲任何適當材料包括印刷布線板、撓 性電路'陶瓷或矽基板或其它多層電路之介電層,但其它 -6- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -------------Γ-裝.--- (請先閲讀背面之注意事項再:„}^本頁) 訂- 線 425579 π _B7__ 五、發明說明(4) 適當基板及材料也可使用。介電層20係由正或負可光成像 厚膜聚合物製成,因此已知之光成像及顯像技術可用於圖 樣化介電層20 ^適當厚膜聚合物組合物典型包括樹脂、光 敏劑及硬化劑。樹脂成份可爲任何適當液體樹脂或固體樹 脂,故樹脂混合物方便以液體形式沉積於基板1 8表面上或 呈層合物形成介電層20。有用的樹脂包括熱塑性樹脂、熱 固性樹脂、彈性體及其混合物,其當攙混光敏性材料時形 成可光成像组合物。厚膜聚合物之預定性質包括於介電層 2 0沉積及光成像過程保持穩定的物理性質。根據本發明, 介電層20作爲電路結構於基板18之永久介電層,故薄膜聚 合物之介電性質於整個沉積及光成像過程也較佳保持穩定 。由於前述理由故,環氧樹脂特別適合作爲介電層2 〇,較 佳基於環氧樹脂之組合物爲市面上得自汽巴嘉基公司之 LMB 7081 及LMB 7082。 經濟部智慧財產局員工消費合作社印 由於存在有光敏劑,介電層2 0曝光於適當電磁輻射可透 過一光罩(圖中未顯示)進行而精確地以光化學方式圖樣化 介電層20。随後介電層20經顯像去除於光成像過程中未被 聚合的介電層20之可溶部分,同時介電層20之已聚合(不 可洛)部分保留黏者於基板18表面。圖1中,介電層2〇之第 —部分22已經聚合,而介電層2〇之環繞部分22之其餘部分 2 4保持未聚合。如由後文討論顯然易知,聚合部分2 2建立 電阻層14之寬度及長度如圖4所示。 圖2中,層合物箔26係於介電層20顯像前施加於介電層 20表面。箔26包括一電阻層28及一保護性襯層3〇,其輔 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公g ) 經濟部智慧財產局員工消費合作社印製 425579 A7 _________B7__ 五、發明說明(5) 助薄電阻層2 8之層合至介電層2 〇。較佳具體例中,電阻層 28爲以鎳爲主的合金,較佳爲鎳-磷或鎳_鉻合金,而襯層 3 0爲銅箔。較佳電阻層2 8係由鎳-磷合金製成,其含有最 间5 〇重量_,差額爲鎳及附帶的雜質。電阻層2 8之較佳 厚度爲約0.01至約0.5微米俾許可於介電層2 〇顯像過程中顯 像劑滲透通過電阻層28 ^銅襯層3〇之較佳厚度爲約4至約 50微米。一旦層合物搭26層合至介電層2〇,則襯層被 去除而留下電阻層28黏著於介電層2〇表面。若襯層係由銅 製成,則襯層3 0易藉已知方法去除,例如使用習知鹼性含 氨蝕刻劑去除。 如圖3所示,然後介電層20被顯像,如此顯像時’電阻 層28之覆於介電層20,未聚合部分24上方部分也随同溶解的 介電材料去除。電阻層28之殘留部分爲電阻器12之電阻膜14,如圖4所示。随後第二可光界定介電層32較佳施用於 電路板ίο,亦即施用基板18及其餘電阻膜14上β此介電層 3 2經過光成像及顯像形成開口,經由該開口例如藉已知錄 敷技術形成終端16。結果終端16之邊緣經過光界定,而可 準確決定電阻器12之電長度。圖5至8所示替代具體例中, 終端16係經由適當蝕刻銅襯層30形成,而非如圖完全 去除襯層30。替代辨法之缺點爲由於由銅襯層3〇形成=端 需要使用扣除㈣步驟,結果導致容差控制減低及終: 1 6凹割。 由前文説明,業界人士瞭解所得電阻器〗2之特徵爲藉由 光成像達成對應介電層20之聚合部分22寬度的精確寬^, 本紙張尺度適用中國國家標準(CNS)A4規格(2Ι〇χ 297公釐) 請先M讀背面之注意事項再本頁) 裝- •lt5J. -線. 425579 A7 B7 五、發明說明( 以及由光成像開口 34於第二介電層32決定的精確長度。前 述製程之修改爲可預見’同時保有藉光成像可進行的預定 準確度。例如使用夠薄的電阻層2 8或透光電阻層2 8例如銦 錫氧化物’介電層2 0可經由電阻層2 8光成像,而非如前述 ’於層合猪26至介電層20前先光成像介電層20。爲了如此 進行’電阻層2 8較佳具有電磁性質其許可具有預定頻率、 傳播方向及強度足夠激勵介電層2 〇之光敏特性的電磁輻射 作電磁穿透。此外,電阻層2 8可經由蒸鍍、濺散或無電鍍 敷電阻膜於介電層20上形成。 雖然已經就特定具體例説明本發明,但業界人士顯然可 採用其它形式。例如如圖9顯示的環形電阻器1 2,電阻器 1 2之配置於圖1至8所示配置有顯然變動。如此本發明之範 圍僅受如下申請專利範圍界定。 (請先間讀背面事項再} ^本頁) 裝/ 訂- 線 經濟部智慧財產局員工消費合作社印製 -9- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐〉

Claims (1)

  1. 425579 A8 B8 C8 D8 、申請專利範圍 1 · 經;ί部智慧財產局員工消費合作社印*'1衣 5. 製Γ微電子總成之方法,該總成具有-電阻器結 勺土板上,該基板具有-第-區及-第二區,該方 法包含下列步驟: :力二敏性電介質至基板,形成一第—介電層,及遮 態;m及系二區,光敏性電介質可爲可溶態及不可溶 =第-介電層於電絲射而產生第—介電層於第一 I邵分之可溶態以及第—介電層於第二區之第-郅分之不可溶態; 外加—電阻膜於第一介電層上;以及 覆介電層而同時去除其第一部分及電阻膜之 二部分上万邵分,使電阻膜之剩餘部分保留於第 利範圍第1項之方法,其中該外加電阻膜之步 膜:括一介電層與—多層膜作爲電阻膜,該多層 膜包括一電阻層及一單體層。 ^ 如申請專利範園第2項之方法,其進一步包 曝光電阻層後去除單體層之步驟。 。 圍第1項之方法’其中該外加電阻膜之步 驟包含層合第-介電層與—多層膜,該’ 層及-鎳-磷層;。… 帮腰含有-銅 如申凊專利範圍第1項之方法,其進—步包含&, 膜a二層膜(步骤’該多,膜包含—電限層及二單體 層係由電阻材料组成,該電阻材料係選自包括 請 先 閱 背 面 之 注 意 項彳ί 頁 訂 線 -10 本纸張尺度速用中國國家標準(C|s;S)A4規格(210 X 297公釐 425579 A8 R8 CS D8 六、申請專利範圍 經濟部智慧財產局員工消#合作社印製 鎳合金’鎳-磷及鎳-鉻。 如申請專利範圍第1項之方法,其進一步包含製造電阻 膜爲多層膜之步驟,該多層膜包含—電阻層及一單體層 ’該電阻層係由鎳-磷合金組成及具有厚度於約0.0〗微 米至約0.5微米之範圍。 如申請專利範圍第1項之方法,其中該外加電阻膜之步 驟包含無電沉積電阻膜。 如申請專利範園第1項之方法,其中該外加電阻膜之步 驟包含濺散電阻膜。 如申請專利範圍第1項之方法,其中該選擇性曝光第一 介電層之步驟係經由透過電阻膜選擇性曝光第一介電層 完成,該方法進一步包含形成電阻膜之步驟,該電阻膜 具有厚度及電磁性質許可具有預定頻率、預定傳播方向 、及預足強度足夠激發光敏性電介質之光敏特性的電磁 輻射經由電阻膜作電磁穿透,因而獲得該可溶區及不可 落區0 10.如申請專利範圍第1項之方法,其進一步包含下列步驟: 於顯像第一介電層後,外加—第二介電層於第—介電 層上;以及 形成至少二開口於第二介電層而暴露至少電阻膜剩餘 部分之一部分A .. '' 6 . 8 . 9. -11 匕纸張尺度遺用中國圃家標準(CNS)AJ規格(21ϋχ 297公沒 -------- I I I I I · t----— —訂 I I------ (請先閱讀背面之注意事項再 \本頁)
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JP2002520809A (ja) 2002-07-09
EP1053507A1 (en) 2000-11-22
DE69935780D1 (de) 2007-05-24
WO2000002088A1 (en) 2000-01-13
ATE359539T1 (de) 2007-05-15
EP1053507B1 (en) 2007-04-11
US6232042B1 (en) 2001-05-15
DE69935780T2 (de) 2007-12-27

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