TW425561B - Vertically stacked field programmable nonvolatile memory and method of fabrication - Google Patents

Abstract

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Description

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5. Description of the invention (1) 'Background of the invention 1. Field of the invention The present invention relates to low-cost, high-density semiconductor memory. Furthermore, ‘the present invention relates to semiconductors whose contents are non-volatile, and the data stored in the memory will not change when power is lost. / Day or change 2 * Background of the Invention The demand for higher density semiconductor memory continues unabated, and customers continue to buy these memories in larger quantities, even when the number of bits on each chip is every three years ( (Approximately) The same is true when quadrupling. Therefore, there is a constant need to provide more aggressive and affordable products at lower, cost & rates to meet the needs of the market. " * Semiconductor non-volatile memory can be divided into two types: (丨) data is permanently written in the manufacturing process and its content cannot be changed afterwards, which is called mask ROM and read ROM (mask ROM) Or factory-programmed ROM: (2) Memory that can be added after the completed memory device leaves the factory. The latter of the two is called "field programmable memories" because its contents can be written by the user when the semiconductor memory chip is configured in its final application environment-i.e., on-site. The field programmable memory can be further subdivided into "write once" memory and "write / erase / rewrite" memory. Those written once are called / Programmable Read Only Memory (PROM) or Programmable Read Only Memory (0TPR0M) β and those with write / erase / rewrite capabilities are called ultraviolet erasable programmable Read-only memory (UVEPR〇M) or electrical can be programmed

Page 6 '425561 V. Description of the Invention (2) ~-Read-Only Memory (EEPROM) or Fast and Flexible EEPROM (Flash EEPROM): Conversely, the contents of the ROM are masked. They are stored permanently during manufacture, so The ROM from the mask cannot be erased and is actually "factory-only" memory. The on-site programmable memory is more flexible than the mask R0J (because it allows the system product manufacturer to stock a single universal part for many purposes, and uses many different methods at the very end of the system manufacturing process. This part is specialized (programming the memory content). This flexibility makes it easier for system manufacturers to adapt to changes in demand between different system products and update or modify system products without generating pre-programmed existing The cost of disposing (discarding) the mask ROM stock. But this flexibility also has its cost: Programmable memory on the site, which has a lower progress than the mask ROM (the number of bits on each chip is less) and the cost High t has a higher price per bit). Customers will like to purchase products that provide the flexibility and convenience of on-site programmable memory and the cost and cost of mask ROM. Unfortunately, no such device is currently available. 'Mask ROM is denser and cheaper than on-site programmable memory due to-° First' because the mask ROM does not support the erase or rewrite function, its = side circuit does not need to include any dedicated circuits or input / output The terminal is used for input data guidance, writing timing, or writing control. Therefore, the peripheral circuit of the mask r0m can be smaller than the field programmable non-volatile memory. This can reduce the mold size of the mask ROM compared to the mold size of the field programmable non-volatile memory, thereby allowing more mask ROM chips to be stored on half the semiconductor wafer, which reduces costs. Secondly, because the mask ROM is only written in the factory, its memory is 4 4

V. Description of the invention (3): 2 The reading operation is designed and optimized, and in general, the single 70 already contains a single circuit element (for example, a single MOS circuit).俨 々 々 艚 艚 艚 — 发-send injustice to the Japanese body). However, the current circuit components—typically a second tunneling oxide floating-closed two-string series electric single crystal—are added to the single-MOS transistor required for reading. Ji Qingyu-: Zhan: The extra pieces inside occupy additional silicon crystal range, making. It has been hidden that the range of the early 7L is larger than the range of the mask ROM cell. Therefore, the density of the field programmable non-volatile memory is lower than the density of the mask ROM. The field programmable memory with write / erase / rewrite capability will cause further complexity. They allow product upgrades, on-site reconfiguration, and enable new applications such as digital photos, solid state disks, and more. Unfortunately, these devices generally suffer from lower density than write-once programmable memory. Turning now to the design of memory cells used in these memories. Most non-volatile memory cells have used semiconductor devices such as Mos field-effect transistors, junction transistors, or junction diodes constructed on a flat single crystal semiconductor substrate. This method can only tolerate very limited vertical integration into third-dimensional space (ie perpendicular to the plane of the base), because each memory cell contains some elements built into the base. Traditional non-volatile memory cells are manufactured using a number of sequential light epitaxial steps that define the characteristics of the cell. For example, the fabrication of the prior art mask ROM unit shown in Figure 1 requires at least five photoetching /

Page 8 425561 V. Description of the Invention (4) Technical masking steps. (A) nitride-LOCOS drawing; (b) polycrystalline silicon gate drawing; Cc) contact point drawing; (d) metal drawing; (6) stylized drawing with ion implantation. These steps are performed sequentially, and each subsequent layer must be carefully aligned with the previous layer that has been patterned on the memory circuit to ensure that the geometry of each layer is printed in its desired spatial position. For example, in cell 10 of FIG. 1, the 'ion implanted layer has traditionally been patterned before the polysilicon layer is patterned. Β Unfortunately, photolithography machines used in a large number of semiconductor manufacturing processes cannot perform such alignments perfectly. They have a "Layer Alignment Tolerance" specification, which indicates the degree of misalignment caused when a new layer is aligned with a previously existing layer on a memory circuit. This misalignment tolerance error forces the unit designer to use a larger body size. If the alignment error is negligible, it is not necessary to design such a larger size. -Designed at least and for another example, the increase in t on the LOCOS layer and the increase in the difference in polycrystalline t, this is the case. If the misalignment of the new memory unit can be found, more photo-etching techniques are allowed, such as' if a shape on the metal layer requires a complete shape, then the geometric overlap between the two shapes must be allowed by the misalignment between the touch layer and the metal layer. The error is as great. If a shape of the polycrystalline sluice layer needs to be avoided, do not touch one shape, then the geometrical separation between the two shapes is at least as large as the misalignment tolerance between the open layer and the LOCOS layer. Misalignment allows the mold size to be increased, the density reduced, and a new structure that requires fewer sequential photoetching steps to be performed. 'This unit will include less difference in its size' and the unit will be The size will be smaller than -425561

The size of the unit of step. And if a new memory cell structure ("self-aligned" cell) with no alignment requirements in the X or Y direction can be found, it will not need to include any alignment tolerances in its physical size. This new type of cell can be made smaller than similarly functioning non-self-aligned memory cells. Fig. 1 shows a very common circuit design used in a mask ROM. It is an example of a 'virtual ground type' elbow circuit as taught in U.S. Patent No. 4,281,397. Its memory cell, such as cell 10, includes a single MOS transistor built in a flat semiconductor substrate, and is connected to a polycrystalline line (such as ffL1, ffL2), a metal bit line (such as BL1, BL2), and a virtual ground line (eg, VG2). The unit is stylized by, for example, an ion implantation mask, which greatly increases the threshold voltage of the transistor. For example, if implanted, the unit presents a logical j ', and if not, the unit presents a logical 0. Figure 2 shows a field programmable non-volatile memory such as taught by U.S. Patent No. 4,203,58. Its memory unit 2 includes a block line, a stylized line, a floating gate, a bit line, and a ground line. By applying a suitable voltage to the bit line and the stylized line, the unit can support writing, erasing, and rewriting and reading operations. Figure 3 shows a programmable logic array (PLA) semiconductor structure such as taught by U.S. Patent No. 4,646,266. Its basic unit 14 includes a pair of back-to-back diodes, providing four possible states: none in both directions, both directions are in conduction, the first direction is in conduction and the second direction is not in conduction, and the second direction It is turned on and the first direction is turned off. This structure is not constructed on a flat semiconductor

f A? 5 ^ 61 5. Description of the invention (6) PLA on a bulk substrate, which does not stack many layers perpendicular to each other to form a three-dimensional structure. Another prior art mask ROM circuit is taught by U.S. Patent No. 5,441,907. Its memory unit includes an X conductor, a Y conductor, and possibly a diode. The unit is stylized by a mask that allows (or prevents) the formation of an "inserted" diode at the intersection of the X conductor and the Y conductor. For example, if the diode exists, the unit presents a logic 1; if the diode does not exist, the unit presents a logic 0. U.S. Patent No. 5,536,968 teaches a field programmable non-volatile memory unit using a fuse and a diode. If the fuse is not blown (conducted), the diode is connected between the X conductor and the Y conductor, and the unit presents a logic zero. If the fuse is blown open (not conducting), there is no diode-body connection between the X conductor and the Y conductor, and the unit presents a logic one. U.S. Patent No. 4,442,507 teaches a field programmable non-volatile memory unit using a Schottky diode and an antifuse. Its memory unit includes an X conductor made of polycrystalline semiconductor material, a Schottky diode, an inverse fuse formed of an intrinsic or slightly doped semiconductor, and a Y conductor made of metal. The intrinsic or lightly doped semiconductor inverse / dead wire has a very high resistance, and this corresponds to a logic 0 stored in a memory cell / cell. But if an appropriate high voltage is applied across the unit, the anti-fuse is switched to a very low resistance, which corresponds to a logic 1 stored in the unit »Summary of the invention

Page 11 ^ 425561 j V. Description of the invention (7) The present invention is connected to a memory unit. The memory unit includes a guiding element for enhancing current in one direction and a state changing element. The state changing element retains a programmed state and is in series with the guide element. An array using these cells is fabricated vertically into multilayer cells. The self-alignment method allows very high densities with minimal masking steps. The array can be fabricated on a silicon substrate, inside the decoder and wheel-in / out circuits, or in a thin-film transistor above the substrate. Brief Description of the Drawings Figure 1 is a circuit diagram of a prior art mask ROM. Figure 2 is a circuit diagram of a prior art field programmable memory. Figure 3 is a circuit diagram of a prior art PLA. Figure 4 (a) is a perspective view of a memory cell constructed in accordance with the present invention. A specific example of the early stage Fig. 4 (b) is a schematic diagram of an array using the cell of Fig. 4 (a). Fig. 5 is a front view of the cross-section of the array using the cell of Fig. 4 (a). Fig. 6U) Three cross-sectional views of different examples used to make the cell of Fig. 4 (a). Layer and Layer Stack Penetration Figure 6 (b) is a view used to make the unit of Figure 4 (a). Fig. 6 (c) shows the structure after drawing in Fig. 6 (b). Fig. 6 (d) shows the structure after forming an extra conductor layer and layer stacking in Fig. 6 (c). 6 (e) shows the structure after drawing in FIG. 6 (d). Fig. 6 (f) shows the junction of Fig. 6 (e) after forming an additional conductor layer and layer stack

42556 1

ο Figure 6 (Bg) shows the structure after another drawing step of Figure 6 (f) β Figure 7—The cross section of the array using the unit of Figure 4 (a) is vertical as early as 70 疋, Whose $ and universal cross each other. Figure 8 (a) is a perspective view of vertical stacking units Fig. 9 (a) Plane of a substrate This figure shows the electrical layout inside the substrate. Fig. 9 (b) is the plane of a substrate. This figure shows the layout of the substrate in the substrate. Another tower-free ~

Fig. 8 (b) is an example of the units in Fig. 8 (a). 9 (a) Τζ.— 基 麻 .SI

Fig. 9 (c) is a plan view of a substrate showing the layout of circuits used in this substrate. Fig. 9 (d) is a plan view of a specific circuit using a plurality of sub-arrays of the present invention. Figure 10 (a) 疋 A circuit diagram of the peripheral circuits connected to the array. Figure 10 (b) is another circuit diagram of the peripheral circuits connected to the array. Fig. 11 is a circuit diagram of a peripheral circuit connected to an array used in a preferred embodiment of the present invention. Figure 12 is a cross-sectional front view of an array showing the contact points between three layers of memory arrays. Fig. 13 (a) shows the contact points between the layers 3. FIG. 13 (b) shows the contact points of the connection layer 1, layer 2 and layer 4. Figure 13 (c) shows the contact points between layer 1, layer 3 and layer 5. Figure 13 (d) shows the contact points between layer 1 and layer 5.

Page 13 42556 1 V. Invention, Poverty (9) 'il 3 (e) shows the contact point between layer 1 and layer 3. Detailed Description of the Invention The present invention provides a field programmable non-volatile memory unit and a memory array. Many specific details are set forth in the following description in order to provide: a thorough understanding of the invention. But it is clear to those skilled in the art that the present invention can be carried out without these specific details. Meanwhile, well-known circuits and processing procedures will not be described in detail hereinafter, so as not to confuse the essence of the present invention. The present invention is stacked on the substrate to allow the layer to be stacked vertically above the body. Figure 4 (a) There are two external ends and a state piece 22, or a guide element, which is at the site of the purpose of 22 One layer instead of multiple layers is very simple. The descriptive configuration shows the change in the state between the terminals of the display. The change 22 is a direction to ensure that the programmable non-volatile memory is stored in the substrate. So this forms a three-dimensional array. Each and one layer below it-each other is single. A special organization in which the memory unit is newly invented above the base and in the periphery: a turn-in terminal 20 ′ The §memory unit includes element 23. The input terminal 20 and the variable element 23 are not constructed with a strong asymmetric electric conduction easier than another electrical unit that flows through the memory unit. It is constructed in a flat memory unit, which can be vertical to the memory unit. This makes these units of the layers constructed in a circuit with a specific output terminal 21 connected in series with an output, and the flat semiconductor current-to-voltage direction is still high. The stream is generally within the three-dimensional memory base. Instance. It has a terminal 21, a guide element 22, and a guide element inside the substrate. Sexual device guide element unidirectional

Page 14 5. Description of the invention (1G). This unidirectional behavior enables the memory decoder to establish a unique circuit path to each independent memory unit, so that each memory unit can be accessed independently (for reading and writing) and the state of all other units Nothing. The state changing element 23 is a device that can be placed in more than one state and its state does not disappear or be changed even after the power is removed. One of the many possible embodiments discussed below is one with {HIGH IMPEDANCE} and { Low-impedance} -dielectric-rupture ant if use. These two stored states enable encoding of a single memory. As shown in FIG. 4 (a), the guide element 22 and the state changing element 23 are vertically stacked in a "columnar body" shape structure having a rectangular cross section of approximately y. The columnar body is vertical, and the current direction is also vertical. Depending on the direction of the unidirectional guide element 22, the current may flow upward or toward I. In fact, in one embodiment, the 'current flows upward in some layers of a vertically stacked cell and downwards in other layers. The state changing element 23 is selected so that it can be electrically switched from its initial state to another state ', thereby making the memory field programmable. For example, a dielectric breakdown anti-fuse can change its state electrically by applying a very large voltage (relative to the voltage used in a reading operation) between the input terminal and the output terminal of the memory unit. The memory unit of the present invention can be completely self-aligned in both the X (east to west) direction and the Υ (north to south) direction. This means that the columnar body is defined by the intersection of an input conductor and an output conductor and is automatically formed by β, so the single 7G can be made very small, because its size need not include

Page 15 425561 V. Description of the invention (11) Relaxation for alignment tolerance. In addition, for the construction of Zhuo 4 (a), such as: Thai &, the number is small. Opposite to 4 (b); == leather step mask step:-a step to make the bottom; and dagger ^ The third step is to provide a pattern of material outside the array,. This patterning method results in the vertical / electrical connection becoming self-aligned to the upper and lower conductors. If in contact with, click. The top conductor of the lower unit is equal to:?. Generally speaking, if the array includes (n) layer units, there are (NH) conductor layers and (n + i) photo-etching technology masking steps in the fabrication process of the rugged array itself. There are also several additional photolithographic masking steps to form the contact points. These contact points are outside the array, forming a connection between the array conductor layer and peripheral circuits. The memory unit can also be manufactured using another specific example; the method of forming the self-aligned columnar body described above can be replaced by a method of forming a mask including photolithography using the formation of the columnar body. This will eliminate the self-alignment of the columnar body to the conductor, but the advantage of the manufacturing process is that it is possible to take advantage of the physical characteristics without the side walls. These procedures include solid state crystallization using amorphous silicon, laser crystallization of amorphous silicon or polycrystalline silicon, and other processing procedures apparent to those skilled in the art to form the guide element. In the above self-aligned manufacturing process and non-self-aligned manufacturing process, the contact point of the upper conductor

Page 16 ^ -42556 1 V. The description of the invention (12) is smoothed and exposed, without the need for a masking step. Those skilled in the art are well aware that this procedure can be replaced with a contact point photolithography mask step. It is assumed that the direction of the first conductor 25 in FIG. 5 is east to west. Then, the direction of the second conductor 26 is north to south (orthogonal direction) 'and the memory cell columnar body 27 is formed where the vertical projection of the first conductor intersects the second conductor. The direction of the third guide boat 29 is east to west 'and the memory unit columnar body 30 is prevented from being intersected by the third conductor 29 and the second guide boat 26. Similarly, the fourth, sixth, eighth, tenth, ... and other conductors are oriented in the north-south direction, while the fifth, seventh, and ninth-eleventh, ... conductors are oriented in the east-west direction. Odd numbered conductors are oriented in one direction 'Even numbered conductors are oriented in a vertical direction. In this way, the conductor numbered j forms a downward column (to be connected to the layer numbered j_1), and it forms an upward columnar (to be connected to the layer numbered J + 1). . Because the memory cell does not need to contact a single crystal semiconductor substrate, the substrate below the memory cell array can be used to define uses other than the memory cell. In a specific example of the present invention, this area can be advantageously used to arrange a large portion of the J decoder, line decoder, input / output multiplexer, and read / write circuit directly in the memory unit. Below the array. This helps to minimize the ratio of the surface area of the mold dedicated to the non-memory body unit, and also increases the so-called "array efficiency. The degree of benefits: P car train efficiency = (total area dedicated to memory unit) / [( Memory unit consists of dedicated total area) · κ non-memory unit dedicated total area)] ^ The formula * may decrease by 1 '(non-memory unit dedicated total area) each resulting in an increase in array efficiency.

Page 17 42556 1 V. Description of the invention (13) In the specific example of the memory of Zhao Unit, there are two outings (the input terminal m is also called the block line gang ⑽) and the input "implicit, or" grinding This eight straight "# In addition, the unit may also include the sub- and is also common to a large group of Cuiyuan. Implicit end parasitic electricity ☆ \ ㈣ basis, which forms one for each-memory unit: meaning these hidden The inclusion of terminals may affect the function and utility of the memory unit. Therefore, the seal of the present invention is difficult to retain — 矣 earlier called "two-terminal structure" == exposed local terminals may have additional implicit Instead of pieces = = = j τ In some specific examples, the guide opening = is connected to the input terminal (and the state change element is connected to the conduction bow, and in other specific examples, the H element can be connected in the opposite direction: shape ^ The element is connected to the input terminal and the guiding element is connected to the output terminal: Where is a possible implementation with a strong asymmetric current-to-voltage characteristic curve #Semiconductor element 'which is more specific in one direction than the other == The method is ⑴amorphous, microcrystalline, polycrystalline 丨 or Pieces of early crystalline + conductor (such as Sl, Ge, SiGe, GaAs, [: junction diode; ⑺ metal semiconductor Schottky diode; () τ connected to the source or to the metal-oxide semiconductor field Effect transistor; (5) Qi = 425561,

V. Description of the invention (i) (Zener) diode, burst diode, or tunneling diode; (6) four-layer diode (SCR); (7) amorphous, condensed, Polycrystalline, or single-crystalline semiconductor PIN diodes, and other devices that are well known to those skilled in the art. For the convenience of description in this article, the arrangement of "anode" and "cathode" is extremely easier than flowing from the cathode to the anode. This quasi-word is consistent: PN is connected to the body of the diode. Of course, the present invention is not limited to the use of PN C as discussed in the previous section); for reasons of convenience and familiarity, "more than the voltage on its cathode, the conduction When the voltage exceeds the anode voltage, it is broken. "These terms are also for convenience and body language. The guide element can be two different square wheels into the terminal while the cathode faces the output terminal and the anode faces the output terminal. With proper design in mind, each direction has Which direction is better. The guide element is to make the traditional electrical marking and the PN traditional current from the junction diode and the diode phase. The private current flows from the anode to the anode, and the anode forward bias element is borrowed from the anode. The anode flows to the cathode of the cathode body. Guiding element sub-standard 7F only voltage ". But" reverse bias standard dipole

The orientation is configured with the anode facing the child, (2) the cathode facing the input terminal and the memory decoder and the read / write circuit can operate correctly ', and there is no particular bias + the state change element is the data actually stored in the dagger is a The state placed in more than one state does not disappear or change when the power is removed. According to the present invention, a place in the meta-memory unit may be adopted as the state change. Device, and selected to be some models of the status pattern of 〇 pieces

425561

Examples are (1) (high-impedance state) and (low-impedance state); (2) (state with peak capacitance at voltage Vi) and (peak capacitance under voltage γ2), (3) (Hall (The state where the effect voltage is positive) and (the state where the Hall effect voltage is ^); (4) (the state where the pole vector is pointing upwards) and (the state where the pole vector is pointing upwards) and other state types. Some possible implementation methods of state change elements include-but are not limited to-(a) dielectric breakdown anti-fuse; (b) intrinsically or slightly doped polycrystalline semiconductor anti-fuse, (c) amorphous semiconductor anti-fuse ; Metal incandescent electronic mobile fuse, which can be reversible (U.S. Patent No. 3, 71 7, 852 ') or irreversible transformation; (e) Polycrystalline silicon resistance fuse, which can be reversible (U.S. 4' 420, 766 No. patent) or irreversible transformation; (f) a capacitor with a strong dielectric value, (g) a capacitor with hysteresis caused by notches; (} 1) a Coulomb blocking device; and other possible embodiments. -During the manufacture of integrated circuits, a state change element of a memory cell is manufactured and placed in one of its possible states. This is called the "initial state. For example, if the state change element has (Electrical quality) and (original dielectric) The two-state dielectric destroys the anti-fuse, then the initial state of this component after manufacturing and before stylization is (original). Other specific examples of state changing components will be different The set of states' and thus will have different initial states. Traditionally, this initial state-"logical state"-represents the initial value stored in the memory cell during semiconductor manufacturing. But of course, in other cases, it is also possible to require that the initial state is "logic 1" and that the choice is only a matter of preference or convenience rather than the necessity of technology. The memory unit allows the state changing element to return from its initial state. move to

Λ2556 ^ V. Description of the invention (16) Stylized in a new state. Many examples of state changing elements can be used to change the state by applying a suitable large voltage from the input terminal to the output terminal to both ends of the memory cell. For example, if the state-changing element is implemented as a dielectric-damaged anti-fuse, it is programmed by applying a large voltage to the terminals C of the unit terminal or forcing a large current through the unit), and its polarity is selected to guide the The element is forward biased. This will directly apply a large electric field to the two ends of the dielectric anti-fuse, destroying the dielectric, thereby changing the state and changing the element state. If the electrical direction of the positive terminal is memorized, a large electrical state will flow through to create a resistor. A possible method to program the dielectric breakdown state change element is to ground the output terminal of the body unit and input it at the same time. The terminal is boosted to a voltage (assuming that the direction of the guiding element is arranged such that its anode faces the wheel in and its cathode faces the output terminal, that is, the guiding element is biased positively when the voltage is higher than the output terminal voltage). If the guide element ^ end ^ in the other direction, an anode is facing the output terminal and the cathode is facing the turn-in, nothing else is just to invert the stylized voltage and make the guide element be at the input terminal ㈣ and at the same time boost the output. Those skilled in the art can easily understand that the pressure device can be used to forward bias the guide bow element and program the dielectric: change the element.八八 化 ； 丨 Other specific examples of the electrical damage state change element can be stored in the memory unit without adding-a large voltage to the electrical submersible ϋ can be connected by a current source to its input terminal: output Η㈣ (assuming This polarity will be positively biased = time 卞) and the process

On page 21, the wire-removing L-state changing element is implemented as a "425561 V. Description of Invention (17). If the amount of current is large enough, it changes the resistance of the polycrystalline silicon resistance fuse ', thereby changing the state of the state changing element and programming. This unit. During programming, there may be unselected memory cells that are reverse biased by the fully programmed voltage. If the reverse leakage current of the guiding element exceeds the programmed current required for the state change of the state changing element, then Unselected memory cells may be accidentally written ^ So the characteristics of the guiding element and the state changing element should match each other; a state changing element (such as an intrinsic polycrystalline fuse) that requires a large current can be quite high leakage A current-guiding element is used to program a state-changing element with a very low current (such as a dielectric breakdown anti-fuse). A low-leakage current-guiding element is required. The memory unit of the present invention can be changed according to the selected state of the element. Implemented as non-volatile memory that can be programmed only once or write / erase / rewrite non-volatile memory. In an example, if a thin high-resistance polycrystalline silicon thin film anti-fuse is used as the state changing element (such as taught by US Patent No. 4,146,902), the programming operation is irreversible and the unit is programmable once. After manufacturing and before stylization, all cells contain "Logic 0". Those cells with the required content of "Logic 1" are irreversibly stylized by forcing the state change element to a new state. ° Logic 0 can be (by stylization) changed to logic 1, but logic 1 cannot be changed to logic 0 (because the programming in this state changing component is irreversible) In the second example, if metal is used to pass through insulator silicon Metal-via-insulator-silicon niament fuses are used as state changing elements (as taught by US Patent No. 3, 7 1 7, 852), then

Page 22 4 2556 1 V. Description of the invention (18) The programming operation can be reversed and the unit can be written, erased, and rewritten. After manufacturing and before stylization, all cells contain "logic 0". Those units that require "Logic 1" are stylized. But for this state changing element, the stylization is reversible and the logic value can be changed from 0 to 1 or from 1 to 0 as needed. In the third example, a state changing element having a write / erase / rewrite capability can be used. Its programming operation depends on power but its erasure operation does not necessarily depend on power. The erasing operation can be selectively added to a single memory unit, or all the memory units can be erased in a batch, such as exposing all units to a strong ultraviolet light source like UVEPROM memory. Alternatively, the integrated circuit can be eliminated by heating the integrated circuit. The heating can be performed by a heat source external to the integrated circuit or by an amplifier directly on the integrated circuit. The component is placed in a strong; ^ field to complete. Although the above discussions assume that the state changing element-ν * ^ U 匁 hovering state is called: Ϊ can provide an anti-fuse with a predetermined range of resistance-the risk 4 is partially melted in the range of s 1 Three ^ gate MOS devices allow many possible more ~ 70. Cattle. The area of Yihe is well-known, as shown in Figure 4 (a). A vertical column with a top. The memory unit includes ’another conductor in its memory unit: _print, field programmable non-volatile, a conductor at the bottom of the column 425561 "

^ _ 丨 · I 5. Description of the invention (19) The bottom conductor is a fairly long wire or a wiring on the first conductor layer. This conductor is arranged in a certain direction (for example, east-west direction). The top conductor is a relatively long wire or wiring on a second conductor layer, which is located directly above the layer forming the bottom conductor. The top conductor is arranged in another direction (for example, north-south). The angle between the top conductor and the bottom conductor should be 90 degrees (that is, they should be orthogonal), but this non-mandatory condition β-memory cell columnar Zhao is located at the portion where the top conductor and the bottom conductor project staggered. In fact, the conductors on each layer are conductors that are separated in parallel to each other, for example, the interval between the conductors is equal to the width of the conductors. The first conductor layer (conductor 1) includes a plurality of parallel conductors arranged in the same direction (for example, east-west). The second conductor layer (conductor 2) includes a plurality of parallel conductors, which are preferably arranged in the same direction (for example, north-south direction) as that shown in FIG. 5 perpendicular to the conductor direction of the first conductor layer. As long as the conductors on conductor 2 cross (or stagger) the conductors on conductor 1, the field programmable non-volatile memory unit of the present invention will be manufactured. This is shown in Fig. 4 (b), when viewed vertically toward the top, the memory unit of the present invention includes a conductor and then another conductor: the conductors are cylindrically stacked at the bottom and conductor 2 is at the top. But then conductor 2 is vertical 1-columnar body 1-lead 52 square: the bottom of a layer of memory unit: conductor memory unit with-layer in-another / 2-conductor 3 ° The present invention memorizes many layers Body units are stacked in a way that:-has ⑻. ((_Layer ^ = (N) layer cylinders and (N + 1) layer conductor 1 conductors are required to complete the ⑻layer unit: the bottom of each layer of columnar bodies 425561. 5. Description of the invention (20) ---- conductor Two and then there is a conductor on top of the array). Figure 5 shows a part of a two-dimensional memory array according to the present invention, with N = 6 layers of pillars, and (N + Π = 7 layers of conductors. One (N ) The vertical stacking of the columnar bodies makes the surface area used to be 1 / N of the surface range of the (N) columnar body combinations that are not vertically stacked; the vertical stacking has an N-fold improvement in density. A memory column The bottom conductor of the column is the top conductor of the 1-sided memory columnar Zhao, and the top conductor of a memory column is the bottom conductor of the memory column above. This makes the stacking particularly simple and flexible. In a specific In the example, the two conductors at the ends of the memory cylinder are perpendicular. Since the conductors are shared among the layers of cylinders, the result of this specific example is that even-numbered conductors are arranged in one direction, and odd-numbered conductors are arranged in one direction. The conductors are arranged in the vertical direction. For example, i set the conductor 1 to the east-west direction. U. Conductor 2 is perpendicular to conductor 1 ', so conductor 2 is arranged north-south 1 conductor 3 is perpendicular to conductor 2' so conductor 3 is disposed east-west. Conductor 4 (vertical to conductor 3) is arranged south-north, And so on. So (in this example) the conductors 1 '3' 5 '... are arranged east-west, and the conductors 2, 4, r, ... are made of fine soil. In a specific example of the present invention, a conductor layer (such as The conductor layer number j) is arranged in the north-south direction, while the adjacent conductor layers (number J-1 and J + 1) are arranged in the east-west direction. Where the vertical projection of the (J) layer conductor crosses the (j- 丨) layer conductor A column of corpus callosum is produced. Similarly, a memory unit column is produced where the vertical projection of the (J + 1) layer conductor crosses the (J) layer conductor. The body is intersected (crossed) by the conductors

Page 25 Description of the invention (21) Figure J, so the columns are self-aligned with the conductors. The self-alignment method is described as follows: Let the light-cut technique of the memory unit cause a smaller unit area range, 'the result can be higher; this is: to explain the self-alignment system of these columns, imagine a Material: layer (layer stacking) manufacturing guide element and state change element, and the state change element includes a polycrystalline-oxide-polycrystalline = electrical destruction anti-fuse, and other specific examples. "In this specific example, a columnar body includes four layers of material in a layer stack, which are arranged in sequence as shown in a): (1) a layer of P + doped polycrystalline silicon 40 a layer of N doped polycrystalline silicon 41 (3) —Layered SiO 2 42; (4) is a polycrystalline silicon 43. The layer (40) and the layer (41) form a PN junction (bow 1 element) 'layer (41-43) forms a polycrystalline-oxide-polycrystalline dielectric' anti-fuse. In this specific example, a stack of four layers of material collectively produces a memory cell and is referred to as a "layer stack" 45. There are also conductor layers on and above the layer stack. The patterning will be described below. These two conductors are shown as conductors 4 6 and 48 in Figure 6 (a). Another stack shown in Figure 6 (a) It is a stack 450. Similarly, it includes the conductors 460 and 48 (3) at the end of the stack. These conductors can be made of any conductive material such as metal 5 polycrystalline stone. The guide element package in the stack 450

Page 26 4 2 5 5 6 1 V. Description of the invention (22). The first layer includes a P + doped semiconductor such as microcrystalline silicon and a first layer of 400 and an N doped semiconductor such as microcrystalline silicon. The second layer 41 {). The state changing element includes a layer 420. The layer 420 may be an amorphous silicon layer β for forming an anti-fuse. This layer has a rated high resistance value, but after a large current passes during the programming process, its resistance value is greatly reduced. Layer 43 is shown as an N + layer to provide good electrical contact to the conductor 48o placed above. Layer 4 3 0 can be amorphous, microcrystalline, or polycrystalline silicon, but the processing method must be low temperature to maintain the amorphous structure in layer 4 2 0. Figure 6 (a) also shows another stack 405. It includes an N-polycrystalline silicon layer 400, a stone oxide layer 402, and an N + polycrystalline silicon layer 403. Similarly, the layer 400 or the layer 403 may be a microcrystalline or amorphous semiconductor layer. The stack 405 is sandwiched between conductors 406 and 408. The guide element here is a Schottky diode formed by a conductive metal 406 and a layer 400. The state changing element is an inverse fuse formed by layer 402. For example, the layers 406 and 408 may be a thickness of 100 angstroms of titanium disilicide or aluminum. The thicknesses of the layers wo, 402 and 403 may be 500 angstroms, 80 angstroms, And 50 Angstroms. / Figures 6 (b) -6 (g) schematically illustrate the manufacturing sequence of the memory unit. After deposition and before making the round sample, the layer stack 45 (or stack 45 and 4 05) is one. As shown in Figure 6 (b), it extends across the entire integrated circuit (actually across the entire wafer). 1 Continuous thin plate. Conceptually, the self-alignment method is a procedure of two etching steps: In the first etching step, This layer stack (a continuous sheet) is patterned into (for example) long straight strips running in the east-west direction, and the same patterning steps are used to etch these dielectrics for deposition and grinding as the etching process of the east-west running conductors on the underlying conductor layer ... , Deposition—Second Conductor: Layer = Layer:

Page 27 425561 V. Description of the invention (23) The stacking pattern is made into a long straight bar with a north-south trend ^ The money engraving for making a straight pattern with a north-south trend continues until the first layer of the day has also been passed through the guide引 Elements. This will cause east-west columns. The resulting columns are well aligned with the lower and upper conductors because the columns and conductors are engraved at the same time. In other specific examples, the semiconductor layers in the layer stack (45 or 450 or 405) can be deposited as microcrystalline or polycrystalline, and then treated with laser to improve the crystalline state and increase the dopant activity. The cross-section of the columnar Zhao is rectangular. One side of the rectangle is equal to the width of the bottom conductor and the other side is equal to the width of the top conductor. If the widths of these conductors are equal, the cross-section is square. East-west and north-south patterning uses photoetching technology steps that are widely used in the semiconductor industry and are well known and can use wet or dry etching. Moreover, the deposition "of course" or a layer-stacking method leads to a special practice conductor layer. The conductor is self-engraved to iu- and the silicon used in the unit and when used as a conductor can be borrowed from the original such as ions. Doping methods such as implantation. Other pattern making techniques can also be used to replace the last name. For example, liftoff or Damascene can be used instead of subtracting the pattern making technique. But ideally, The pattern should be made in two separate steps, once defined by the mask and once again by the mask to define the upper conductor. This is true regardless of which manufacturing technique is used to fabricate the pattern of each layer. A very large number of vertical stacks are constructed above Memory unit, and each self aligns with the lower layer stack and the upper layer stack. So the etching step that aligns me with the bifurcated body must remove the material from three different layers. The upper layer stack, the conductor layer, And the layers below.

Page 28 V. Description of the invention (24) The processing procedure can start on a wafer that has been subjected to a pre-processing step. For example, a CMOS transistor can be manufactured in a single crystal substrate for peripheral circuits. An insulator ' is then deposited and should be smoothed (using chemical mechanical polishing CMP, resist back-grinding, or any number of other smoothing techniques). The first conductor layer is deposited as layer 46 in Fig. 6 (b), and then a first layer stack 45 is deposited. Figure 6 (b) shows the wafer at this stage. Next, a mask defining the shapes on the conductor 1 layer is added, and these shapes are etched into the columnar layer stack 45 and the conductor 1 layer 46 below it. An insulating layer is deposited on the wafer and smoothed using CMP or other smoothing techniques. Figure 6 (c) shows the wafer at this stage. Pay particular attention to the individual stacks of columnar layer stacks and bottom layers that have been sculpted into continuous strips (46a and 45a) and (46a and 45b), but without insulation. Please also note that the edge green of the columnar layer stacks 45a and 45b is aligned with the edges of the conductor layers 46a and 46b because both of them are simultaneously etched and masked. Please note that the conductors generally include coplanar conductors' layers, such as aluminum or other metals, silicides, or doped silicon conductors. Although not shown in Fig. 6 (c) or other drawings, the 'dielectric' fills the spaces between the bars (and the columns) and thus increases the support for the array. Please also note that the smoothing operation must reveal the upper surface of the strips so that the conductor layer read later is connected to the strips. The smoothed dielectric also forms a layer that allows the pathway of Figure 3 to pass through the pituitary. Fold & sub-stack body layer 5 (conductor 2), and deposit a second columnar body stack. Since M M d shows the wafer at this stage. Note that the flattened tea automatically provides a self-aligned contact point between the stack of columnar body layers (such as 45b) and the subsequent conductor layer Q (such as 50) above it.

425561 V. Description of the invention (25) Now add the conductor 2 mask, and its shape is etched down into three different layers: columnar stack 2 (51)., Conductor 2 layer 50, and columnar stack i (45a and 45b). (This engraving step stops below the guide elements in 45a and 45b 'to provide a unique circuit path through the memory unit.) ^ An insulating layer is deposited on the wafer and polished (peripheral CMP or other methods). Figure 6 (6) shows the wafer at this stage. Please note the definition of individual columns (45a 1 ’45a 2, 45b 1, and 45b 2) within the conductor 2 mask + etched completed layer stack}. Also note that these pillars in layer 1 are aligned with conductor 1 (463, 46b) and conductor 2 (50a'50b), thereby achieving a self-aligned target. A third conductor layer 52 (conductor 3) is deposited next, and a third columnar layer stack 53 (layer stack 3) is deposited. Figure 6 (f) shows the wafer at this stage. Now add the conductor 3 mask, and its shape is etched down into the stack 3, guide 3, and stack 2 layers. (This etching operation is stopped below the guide element of layer stack 2 'and the conductor 2 layer is not touched intentionally). An insulating layer is deposited on the wafer and polished (using CMP or other methods). Figure 6 (g) shows the wafer at this stage. The conductor 3 mask + etching has completed the definition of individual columns (such as 51a 1, 51a 2 ′ 51b 2) in the layer stack 2. Figure 6 (g) shows that (N + l) = 3 conductor layers and (N + l) = 3 masking steps are needed to make (n = 2) layered columnar layer stacks. (Not counting interlayer transition layers used in peripheral circuits but not used in memory cells). The wafer is now (with the manufacturer's intention) ready to accept more stacked layers and conductor layers. In a possible specific example of an array of memory cells of the present invention, the pillars are as shown in FIG. Vertically stacked vertically. Please note

Page 30 _ 425561 V. Description of the invention (26) The columns are neatly arranged in a vertically aligned stack. However, because of self-alignment, it is not necessary for such columns to be stacked vertically above each other. The columnar body of the memory unit is automatically formed where the conductors on the conductor layer (J + 1) intersect the conductors above the conductor layer (J). Under the vertical stacking of the columns, even if the conductor layers are not directly aligned with each other, the automatic formation of the memory cell columns as described herein is still effective. "In fact, it is better that the columns are not stacked vertically; That is, they are staggered from each other as shown in FIG. 7. Compare Figure 5 (the columns are stacked vertically) and Figure 7 (the columns are staggered from each other) to see the effect. Staggered or staggered columnar configurations such as those shown in Figure 7 have practical advantages. It can help provide a smoother wafer surface, and is more suitable for flattening and polishing. In the foregoing sequence of steps, the 'electrode or conductor material is engraved. Because most electroplated metals also have a double-etched actual material combination such as aluminum and poly, the control of the etching process can be performed by using a chemical (such as preferentially polycrystalline; ε Xidan (Stop at Ming). Etchant-state changing elements used to remove electrodes and device materials can also be used as etch stoppers. This is true for oxide-destructive devices. High-melting metals such as tumbling and balling are compatible with the temperatures used in silicon and can be used as conductors. Metal silicides are compatible with higher temperatures of the product. Even highly doped silicon conductors. The selection of the conductor material is based on resistivity and includes etch characteristics. Together with the device material, silicon is a kind of polycrystalline. Selective engraving is required or by using barrier materials that are not engraved. Especially when the traditional CVD deposition of the device to activate the doping in silicon itself can also be used as a synthetic consideration.

The smoothing operation after the first half of the above step is required to form a self-opposite that has been half-etched early (that is, a line running in the east and west directions in the previous example). The implementation of this smoothing operation can be accomplished through a variety of different methods known in the art. The well-known examples of Zhongsan # include chemical-mechanical polishing (CMP), etching back rotation on the dielectric layer, and etching back rotation. On the polymer. In order to allow extreme over-polishing or over-etching that may occur during the flattening process, a second flattening process may be performed after depositing an electrode layer to ensure a flat electrode surface for subsequent layering of device materials. The above processing program sequence utilizes self-alignment to reduce the required alignment between the columnar body and the conductor. This specific example can be replaced by a specific example that involves one or more additional photo-etching technology steps to clearly Defining the pillars themselves, rather than defining the pillars in a self-aligning process using the interleaving of two conductor photoetching steps. This has the advantage in many different processes that it can take advantage of the clearly defined side walls created by this process. For example, solid state crystallization of amorphous silicon can be used to form a guide element layer stack. The free energy of the side walls can be expected to help the formation of monoliths or particles within the guide element, which is advantageous in some system specific examples. 'Another treatment procedure that uses clearly defined sidewalls is laser induced crystallization. Similarly, the free energy of the side walls can be expected to help the formation of single crystals or particles in the guide element. In a well-defined processing procedure involving a columnar body, a photoetching technique step is used to define a bottom conductor. "This photolithography technique is touched." then

Page 425561

‘Formation of cancer-like change elements and guidance. A photo-etching technique to be etched. After etching, an insulating material is flattened, exposing the top of the columnar body to deposit the top conductor’ and the process has layers. The required layer stack for 7G pieces is deposited. Another step is used to define the cylindrical body β which is generally deposited and ground in this self-aligning unit to form a self-aligning contact point. Then, the order of the masking steps in the subsequent state of the unit that needs to be repeated can also be reversed. For example, the 'pillar' is formed before the bottom conductor pattern is made. In this processing procedure, the entire layer stack of the plutonium, the body guiding element, and the state changing element can be deposited. Then, the columnar body can be delineated with a printing plate and etched down through the guiding element ... The rear boundary is scribed and the bottom conductor is engraved. This structure is purified using the above-ground polished insulator contact architecture. The self-aligned contact points in all three processing procedures can also be replaced by a day and month photo masking step formed with & contact points. Various device manufacturing steps may cause residual chemical or viscous fouling &gt; dyeing and damage device characteristics. To be clear, device leakage may be caused by such chemical residues or viscous pollution (such as Photoresist not completely removed). A low temperature (e.g., <40 0C) plasma oxidation exposure method can be used to grow a scavenging oxide on the edges of the columnar device, thereby dulling the edge traps. The growth of oxides is self-limiting because radon species only slowly diffuse through previously grown oxides, resulting in an extremely uniform oxide thickness and thereby improving its manufacturability. (Plasma oxidation can also be used to form the anti-fuse layer.) Oxide deposition can also be used to passivate the surface, for example, alone or in combination with a grown oxide.

Because in the above-mentioned example with the Ar ia ^, the device material I: such as polycrystalline silicon) Γ jade; later deposited, it is best to bury the device material where possible ^ ^ ^ ^ ^ to widen the appropriate Polycrystalline silicon doped at the original location of the metal can be reduced in pressure from Bogan #f 11 longitudinally enhanced chemical vapor deposition (PECVD) ί1] 1ινΓνηΛ., ^ Ultra-South Vacuum Chemical Vapor Deposition (UHVCVD) Deposit at low temperatures. — Hanwa ’s alternatives are to deposit un-doped silane, and then dope and activate using a low temperature process. “Traditional activation steps, such as long-heat annealing, expose the wafer to two temperatures that may not be acceptable. .) In some cases it may also be necessary to replace polycrystalline silicon with vermiculite or amorphous stone or crystallized amorphous silicon to enable low-temperature manufacturing. Another consideration is the expansion of electrode materials (such as metals) during processing. It is possible to enter the device layer. 4 The temperature treatment procedure can help reduce the severity of this problem, but it may not be enough to completely solve this problem. To prevent this problem, many barrier materials can be used. Examples of barrier materials are nitrogen Titanium (TiN), giant (Ta) or nitride button (TaN), and many other materials in this technical field. In a specific example of the unit, a thin dielectric layer is used as the anti-fuse 7C component In this unit, the good uniformity of the dielectric thickness and the low film defect density (such as the pinhole density in the dielectric) are very desirable characteristics. The quality of the dielectric can be measured in many ways L, for example between deposition of (continuously or periodically) the rotation of the substrate and / or source; an electric low-temperature growth or chemical wing is formed by a dielectric heating method; or using a dielectric liquid

Page 34 42556 V. Description of the invention (30) It is best to have a method to reduce the number of Fanlong involved. Reduced mask step alignment allows interconnected pathways for wide mask steps. The vias can be used to ease the relaxation of several electrode layers for scratching. For example, 奂 (machibe valley lines are connected to each other, X-edge path ruler 7Λχ: the gold distance in several layers arranged is loose, resulting in rectangular passages, compared with the γ-square: in-line discussion. The path will refer to Fig. 12 and Fig. 13. The contact fly of the contact, in which, each layer requires about one masking step to form a single sheet of 憔 τ. However, additional masks are needed to form contact points, Connection ^: the path of the conductors inside the array and the vertical conductors (sometimes collectively referred to as connecting to). Please remember that each array conductor only needs one contact point. So 2 contact points are at the end of the array conductor. Spaced on a layer = contact points can be on the opposite side of the array. This is important because it provides multiple ranges for contact points. In addition, the conductors on the same layer need not have the same screen length, that is, the conductors can gradually Shorter, or longer, or longer in some layers and shorter in other layers to provide a range around the array-these points of contact can be extended down to lower layers, such as each Lower separated layers without disturbing the middle The contact point must be outside the array to connect the inner conductor of the array to the driving circuit. The transistor built in the substrate generally provides driving. The driving transistor can also be constructed over the substrate with materials common to the array. The simplest method of applying contact points is to mask each path of the array ^ These contact points are connected to an upper layer and electrically connected to the base through all the layers below it.

Page 35 4 2 5 5 6 1 Canton V. Explanation of Invention (31). These contact points are either stacked directly on top of each other or are staggered. Both methods are common in the semiconductor industry. In general, the vias and contacts are used to provide a conduction path between the conductors in the array and the peripheral circuits. For example, contact points are formed around the array to contact decoders, row input / output circuits, and column address decoders as shown in Figures 9 (a), 9 (b), and 9 (c). In another specific example, it is desirable to fabricate an array on, for example, a broken substrate, and use a thin film electric reed body to form a peripheral circuit on a layer 'whose contact points provide a conduction path from the layer to the conductors in the array. In another specific example, the uppermost layer can be used as a power distribution. A direct method of making contact with each layer is to use a masking and etching step for each layer, which occurs before the formation of the layer that defines the conductor. This masking step forms an opening to the layer below it and provides contact points as needed. _ Figure 12 shows an example of this approach. Starting from the foundation of the structure, a contact point π was masked and etched through the substrate insulator 100 to the substrate contact point 101 before starting to manufacture the array. The conductor layer 10 6 is deposited before the memory stack 1 3 1. In this example, the lower layer 107 of the memory stack is a heavily doped semiconductor. This is important in this example because the heavily doped semiconductor will provide a connection in ohms' and thus need not be completely removed from the conductor layer. The region 120 and the range above the contact point 110 are formed during the formation of the stripe of the composition layer. In this case, 120 is electrically insulated from the other conductors on layer 1 by the layer 丄 's arrangement. The dielectric is then deposited and smoothed to expose the top surface of layer 1 and then a contact opening is formed.

2. Description of the invention (32) The layers of + are at least down to the heavily doped layer 107. Figure 5 shows that layer 2 conductor 122 and the memory stack are deposited and patterned in the same manner as layer 1 was made. Similarly, a mask is used to insulate the conductors in this area. The dielectric is likewise deposited and etched back to the top surface of the storm 2. As in layer 1, a contact mask is used to open α 11 2 through the memory cell element down to the heavily doped material. Finally, layer 3 conductors are deposited into the opening 2 to form a slave layer. 3 continuous electrical connection to the substrate. -From the description above, it is clear that contact points from any layer can be applied to an area within the substrate by an additional masking step for each layer. In another specific example ', a masking step of less than one per layer may be used to form a conductive path to the substrate. This is possible if more than one conductor is in contact with a single substrate area. Note the example in Figure 13 (c), where conductors 1, 3, and 5 are connected to the same substrate area. Figures ^ (8) -13 (6) show several possible structures of contact points. Figure 13 (£ 〇 shows a configuration, where the contact point is made between the layer 丨 (or layer N) and the conductor of layer 3 (or layer N + 2). Please note that in this configuration, the layer Nh The conductor is made shorter than the conductors in layer N and layer N + 2 to allow a wide space for contact points without affecting the conductors in layer N + 1. The contact point here is because it lies between adjacent layers Between them, so it stretches through the memory stack shown by the shaded part of the slant line. Figure 13 (b) _ shows a contact point from a conductor in layer 4 (or layer M + 3) to contact layer 1 and layer 2 (or Layer N and layer N + 1) conductors. Please note in this configuration

Page 37 ^ 12556 1________ 5. Description of the invention (33), the conductor in layer N + 2 is shorter than the conductor in layer N, so that the structure made from layer N + 3 can extend downward and contact the two lower conductors . It is only necessary to define a single opening within the insulator to form this contact point and the opening is configured to pass through an oxide or other insulator used in the smoothing step. Another contact point is shown in Fig. 13 (c), where the conductors from layers 1, 3 and 5 are connected to contact a substrate area. The conductors in layers 2 and 4 are staggered here so as not to affect the contact points. Again, this contact point is defined using only a single masking step. A contact structure is shown in FIG. 13 (d), wherein each of the layers 1, 2, 3, 4, and 5 has a conductor connected to a common base region. Finally, a contact point is shown in FIG. 13 (e) from layer 3 (or layer N + 2) to layer 1 (or layer N). The difference here from Fig. 13 (a) is a single-opening through the insulating material. ^. When forming structures 1 3 (a)-(e), the resistivity of vertical conductors is important. Metals, silicides, and silicon doped in situ can be used. Implanted dreams are not favored today because it is difficult to dope the silicon on the contact sidewalls. Note that when forming the contact point of FIG. 13 (d), an opening is first etched from an upper layer through several lower layers. "After the insulation is etched to expose the edges of the layers, the memory cell material is then isotropically aligned. Etched to expose more conductors. In this way, isotropic deposition of materials such as polycrystalline silicon * CVD w can be used to obtain a large surface area on the plutonium conductor to ensure low contact resistance. _ Although the contact point of Fig. 13 (c) uses the same principle ', because of that, only the insulating material must be made in the same direction to expose the layer i and layer 3 conductor 9

^ -42556 1

edge. Require = mask 0 steps and: two (C.): The technique shown is used to limit the number of processes in the process from reducing to ㈣ using any one of the two techniques can mask, unit: small size size 形ii: The person's self-alignment makes the pattern shape of the memory unit small _ The pattern layout does not need to be left out of alignment to allow for relaxation. This peptide is smaller == memory unit range is reduced, in fact it is less self-aligning = 4 m Ϊ unit range has a second benefit to further reduce the unit: the height of the geometry on each mask layer is repeated Sex pattern. In this case, the geometry of each layer of the memory cell array is very simple. It is just a lot of highly repetitive, very regular, closely spaced, straight long parallel conductor lines. The photolithography technology can be used for their simplicity and regularity. The smaller size and better resolution of the resulting shape are arbitrary, but it is impossible to achieve the shape. For example, 'If a (wafer stepper and illumination light source and lens and photoresist) system is generally rated at X micron resolution (such as 0. ^ 8 micron), the simple and highly regular shape of the present invention allows the line With spacing shipped less than X microns. The present invention can take advantage of the fact that there are no arbitrary geometries; only highly repeating very simple patterns are well known in the field of optics and are called "wrapping gratings" in textbooks. Proficient in the technical field The user can easily understand how to use the advantages of the raster pattern to achieve better resolution.

Page 39 Λ2556 ^ V. Description of the Invention (35) For the time being, suppose that there is a concrete example of a columnar body with six memory cells, and therefore a conductor with seven conductor layers. If the bottom conductor layer (conductor 1) is arranged in the east-west direction, the conductor 3, the conductor 5, and the conductor 7 are also arranged in the east-west direction. The conductor 2, the conductor 4, and the conductor 6 are arranged in a north-south direction. For the sake of simplicity, suppose there is a specific example in which the columns do not offset or intersect, but are stacked directly on top of each other. A single vertical stack of six such columns is shown in Figure 8 (a). The stack of six memory cell columns in Fig. 8 (a) is shown as a schematic circuit diagram in Fig. 8 (b). Note that the conductor layers 1, 3, 5, 7 are separated from each other in the illustration, but they are directly stacked on top of each other in the solid structure (Fig. 8 (; a)). Similarly, the conductor layers 2, 4, 6 are vertically stacked in Fig. 8 (a) but separated from each other in Fig. 8 (b). In Figure 8 U), there are six memory cell pillars: one is where the conductor 2 and conductor 1 intersect, one is where the conductor 3 and conductor 2 intersect, ..., and one conductor 7 and conductor 6 are staggered. $ 此 1, + Be prepared for the 5 column of the 5th memory body and the early columnar body in Figure 8 (b) (package: one V: right: the line is displayed at the lower left corner-between memory 1. (b) It also shows that in the body, the conductor and the conductor are staggered, and the other unit is located at the conductor two at the conductor 3 and the conductor 2. It is recognized that the conductor parent is wrong, and so on. The adjacent layers of the eight hidden bodies of the early pillars share a conductive reed-reel-in / output terminal. In 9, the daggers are also between similar types of terminals: the input terminal Zhao 'sharing occurs only in the conductive layer ， • Out terminal is shared with other in-out terminals. The advantage of the body example is that this means that each: =: conductor layer. Such a mother conductor layer is unambiguously a lose

Page 40 ^ 556 V. Description of the invention (36) The output f will not be mixed like the conductor terminal and the output terminal like the conductor layer, so the peripheral circuit is simplified. The input terminal circuit and the output terminal receiver circuit need not be configured and multiplexed on the same conductor. As a result of the benefits of terminal-like sharing, the direction of the guiding element in the memory unit becomes cathode to i, then cathode down, then cathode up, and so on. To see this phenomenon, assuming that the conductor layer conductor 2 is an output layer, the cathodes of the columnar body 60 and the columnar body 61 are connected to form the conductor 2. The direction of the shape _ must be the cathode upwards, and the columnar body 61 continues. 'If the conductor 2 is an output layer', the conductor 3 is an input layer. The anodes of the columnar body 61 and the columnar body 62 are connected to the conductor 3. So the column cathode is up. The layers of the pillars must be changed alternately, cathode up, cathode down, ^, down, up, and so on '-for a specific example, see Figure 8 (b). This means that during manufacturing, the layers of the columnar sandwich will be deposited in a different order. In some columnar layers, the anode material layer is deposited before the cathode material is layered ', while in other columnar layer layers, the cathode material layer is first deposited. Therefore, the layers shown in Fig. 6 (a) are shown in an order among the spaced array layers and in the opposite order among the remaining layers. Remember, however, that it is not necessary to change the stack material interactively in some specific examples. Another consequence of the similar terminal-sharing benefits of the μ memory unit is that it allows the conductor layer to alternate between input-only terminals and output-only terminals. Because continuous conductor layers are configured east-west, then north-south, then east-west [and so on, this means that all input conductors will be configured in the same direction (such as east-west), and all output conductors will also be configured in the same direction (such as north-south). to)

Page 41 5. Description of the invention (37) Configuration. Households must set the input terminal media freely (for example, along the western edge of the memory array) or set the output terminal receiver elsewhere (for example, along the southern edge of the memory array). Yi Yi corresponds to the standard practice of traditional memory design: Yu Shan = circuit 67 is located along the western edge of the array and the output 68 is located along the southern edge of the array, as shown in Figure 9 (a) The eight. ° Traditional memory will put half of the input terminal driver: f: and place the other-half along the west edge; this is often done when the east edge is very tight. It is also placed at the same distance from the north edge; this is in the memory cell row j. Here the traditional memory of the cutting method is; flash memory (whether it is the traditional previous technology or redundant ~ the terminal driver circuit has-shorter and less tiring ^ ίΐΧ decoder "(Ca 仏 ―) The output circuit of the output terminal receiver circuit in the "reminiscence body" (whether it is the traditional previous technology or the current one) has a shorter and less expensive name called a line address decoder and a line input. / Output, (coluffln address two whr and coluifln 1 / 〇) circuit. This shorter name will be used in this section of the description of the invention to discuss the organization of the memory cell pad external arrays. It will be possible to combine column decoder circuits and The line decoder and input / output circuits are folded under the memory array. (This may be due to the memory array

42556 1 V. Description of the invention (38) The single crystal underneath it recognizes some column decoder circuits; it does not touch the substrate. ) Will not put all: because this fold will completely break the road to the bottom of the array, the line decoder and line turn into / Laoshan overlap. In a specific example, the column &amp; ^ Μ 乂 wheel-out circuit is folded to Γ of the array in the center of the memory array. Under another Λ that conflicts with the row circuit, and the central part of the column decoder is arranged below the m column in each corner. This allows the column electrical fins and other memory arrays to be shown in Figure 9 (c) As shown in these. These multiple) arrays are closely packed with one wing convex staggered, so that four (or more technical techniques try it together), as shown in Figure 9 (d). Below 1. The LP easily understands that there can be many other variants of the method of folding a part of the decoder into the array. Including 'the field programmable non-volatile memory package of the present invention-organized into many smaller times Array, not made-single simple 66 ^. Into 1 &quot; lists two important benefits: (1) they provide a secondary method for redundancy; ⑴ they increase the speed of operation; (3) they reduce the cost of operation It is very straightforward to use a sub-array to achieve redundancy. 掇? I The final product will be a memory with (for example) 8 ν bits, so it is very easy to construct nine sub-arrays each containing N bits on the cast. Simple thing. Nine = one of the arrays may be defective, but just skip the defective subarray 'the mold 8N bits that can still be configured as usable. Splitting the memory into sub-arrays also increases speed; this is because; shorter bodies reduce their resistance), and each conductor has fewer memory cells attached to it Up (reduce capacitance). Because the delay is proportional to the product of resistance and capacitance,

Page 43 1 ^^ 5 'Explanation of the invention (39) Halving the length of the conductor can make the delay one quarter. As a result, the sub-array reduces latency, which means faster speed. -, -Under array also provides lower power consumption operation. Because an important part of power consumption is the capacitive charging and discharging of the conductors in the memory array, lowering the conductor valley will reduce power consumption. Halving the pilot length halves the capacitance, which halves the capacitive charging and discharging current. -Electroelectric meter. And selection ", in a specific example of the present invention, the columns (also known as word lines) of the memory array are inputs to the memory cells, and the rows (also called" bit lines ") are Output of the memory unit. A forcing function is added to the memory input (word line) 'and for a read operation, the result at the memory cell output (bit line) is sensed. For a writing operation, the other-force function is added to the memory unit output (by which the two terminals of the unit are forced): the strong chase function used in the present invention can be electricity, current source, waveform generation = (Area impedance or low impedance), charging packets, or other driving pulses. Access to each individual memory unit ^ pairs of read and write penetration still-the circuit path is established, starting from the column line, the body ... to the row 'line. The result of this only-demand is that it cannot be aligned; this can be seen in Figure 8 (a). The columns in Fig. 8 (b) are on the conductor layers 2, 4, and 6. L and 7. A light line (bit line) system is a ^ ^ ^ ^ ^ # Jide Figure 8 shows the vertical stacking of the memory cell column; it is a wrong place. Figure 8 (b) Figure 7 &amp; 7 The first column is separated from the solid by the other. # T ^ i-i. For the convenience of inspection, it is shown that the conductors are separated by a knife, but the actual Stack them on top of each other β

V. Description of the invention (40) Suppose that all block lines are driven at the same time; for example, suppose that the conductor layers, 3, 5, and 7 are forced to a high voltage. There is no unambiguous circuit path to the circuit output (on the bit lines, ie, conductor layers 2, 4, and 6), so the contents of the memory unit cannot be determined. For example #, suppose the sensing circuit determines what conductor 2 is? This means that the memory of the conductor between conductor 1 and conductor 2 is programmed to a low impedance state. Either of these two conductable energies is established, from the source of the galvanic source (block line) to the conductor 2 ± of = road = unfortunately, it is not possible to determine which of these possibilities is actually true. The only circuit path to conductor 2 is the same for two bit lines, conductor 4 and conductor 6. Obstacles to the other: should n’t drive all the word lines at the same time; No, the path goes to the I-memory array ... Kind of _direct solution electricity Early word line does not drive all other word lines. Two driving. A train solution cries 7 η, and Li Zu members are not enabled as shown in Fig. 10 (a). And the four-layer selection signal is being selected. Whether the line is to be blocked or not. The block line should be enabled. &quot; An outer conductor layer is selected (for example, low voltage), and the layers are selected as non-selected (for example, high voltage) ^ So, only-only one of the two is not driven in the other three. The pre-set line is driven, and it is clear that the device in FIG. 10 (a) establishes a path. Assume that the word line on conductor 5 is selected by the f array. It is judged that 4 samples of Lippo φ axillary α ^ ^ 1 are assumed to be sensing circuits: 疋 疋 Conductor 4 is at south voltage. There are only two ways to press: its-is through the memory unit 71, 425561 between the gate 3 of the conductor 3 and the conductor 4 of the body 4

V. Description of the invention (41) :: is transmitted through the memory unit 72 = 5 between the conductor 4 and the conductor 5 is driven and the conductor 3 is not driven, so the only existing circuit circuit search ^ 的 word block line through Memory of Zhao Zhao between conductors 5 and 4 :) Bit lines on body 4. If the sensing conductor 4 is high voltage, then til Zhao Zaowu is stylized as a logic °; otherwise, the cost of this memory unit to t 2 7 is very high; each of the memory array * 's straight layers (Xing such as 16 layers, if there are a lot of vertical eight bit line conductors in the array, it is necessary to # 9 word line conductor layers and

W This can detract from the efficiency of the mold and cost many days. 'However, we observed an increase and a decrease in density. Two paths: the ambiguity in its traceback () originates from each bit line with-from the line immediately following it: Zhi 2: 2 :: = the word line on the conductor layer 'and we only have to ensure two A 2 Guang Shi sub-group line. To avoid ambiguity, the word lines are separated into groups: ‘only one of the paths is enabled. Just put it into this assurance. "Guide the first group" and "the second group", it's very easy to reach ... The lines on the conductor layer are '/ body 5, conductor 9, conductor 13, conductor 17, 11, conductor 15, ... and so on. In the group, conductor 3, conductor 7, and conductor observation are to drive the block lines on the body layer in the second group at the same time. It is important that other block lines are obscured ~ all block lines in the group, as long as the second group "It is absolutely safe, and vice versa (Figure 10 (b)). The director of the memory cell in the circuit column in Figure 1 {Hb) includes two switching transistors 75 and 76, and the array of vertical layers" The number is irrelevant. The first set of character lines has-

Page 46/1 2 5 F 6 V. Description of the Invention (42) Switching ^ • Crystals ”The second group of word lines has another—switching transistors. Similarly, there are two group selection ^ signs to determine which of the two block line groups is driven. The more vertical layers of memory cells in the wafer, the more 囷 10 (b) saves compared to Fig. 10 (3). Let the first group selection signal be in the selection state (high voltage) and the second group selection signal be in the non-selection state. Then on conductor 丨, conductor 5, conductor g 2: layer "block line is driven 'and conductor 3, conductor ?, conductor u, bit line on the milk: this path is from the conductor] through (only the path to the conductor The memory unit between the two reaches the conductor 2 layer: on the memory unit t between the conductor 1 and the conductor 2 between the conductor 3 and the conductor 2. The path from the conductor 3 may be blocked, because Another broken drive on the two-character conductor 2 ^ 'Conductor 3 in the line group is not a 1-way design: the effect of decoding lines, two lines, and the structure of the line group (Figure 10 (b)) is the memory of the broken selection The body unit is on it ... If the second mother line has -N) conductor layers, each selected row can simultaneously have 70 lines of elementary memory. A specific example of the present invention does / 'Or write bit, read or write in line) N bits. Other selected evening: device 4' It will reduce the number of memory cells accessed simultaneously Figure 11 shows another specific example. Each bit line is replaced with a transistor such as transistors 77 and 78. If this line is used, the connection is made as = connection-bit line to-bidirectional input / round out bus. After reading- Inter '' the bit line driver of the input / output bus. However, in the writing

^ h_A2_§_5_6J V. Description of the Invention (43) During operation, the input / output bus drives the bit line. If there are (N) -level line wires, there will be (N) switching transistors and (N) wheel-in / output-bus conductors. The input / output bus conductors are connected to peripheral circuits and include a sense amplifier (read two) and a write driver (for write). The cost of the selection circuit in this row is much higher than the cost of the selection circuit shown in Figure 0 (b). "Because each bit line must have a switching transistor, if there are more s memory cells, the layer is vertical. Stacked up 'there are more and more bit greens and more and more switching transistors. The row selection circuit consumes more silicon area than the column selection circuit, especially when multiple memory cell layers are stacked vertically. That's why I want to fold the row selection circuit under the memory array and select the column. $ Is regarded as a secondary cause 'as shown in Figure 9 (c): the row circuit is much larger &amp; in fact, a reasonable design decision will fold the row circuit to the memory array, but not even at all Try to collapse the column selection circuit below. Benefits Benefits mainly come from the folding of the row selection circuit. I charge memory is displayed in a word size, in many cases, it is very suitable to charge the stomach and the stomach before starting a read or write operation i-intermediate level-such as the supply voltage of 0.5 and all bits The 7G line is "pre-charged, to an intermediate voltage level, such as 0.4 times the voltage. Read / write edge encounters, several specific examples of the invention use the _state change to correspond to different impedance values. For example, there are two states of dielectric broken wire: very low impedance and very high impedance, the difference in J reactance

Page 48 42556 1

V. Description of the invention (44) Powers up to ten. Specific examples like this can use "current mode read" and "voltage mode or current · mode write", which will be explained later. When reading a memory cell, a current source can be selected as the strong return function to drive the block line. If the memory cell is programmed (the dielectric is broken and has a low impedance), this drive current will pass through the memory cell to the {LEV line. The selected bit line will be switched to the (bidirectional) input / output line, and the drive current will be sent to this input / output line. A current sense amplifier connected to the input / output line detects whether the driving current is sent to the wheel input / output line. If yes, then the unit being read contains a logic 1 "; if not, the unit contains a" logic 0 ". The main advantage of current mode reading is speed: by forcing and sensing current (not voltage) , Can eliminate the need to charge and discharge the high-capacitance word line and bit line of the memory array, so the word line and bit line will not swing between large voltage swings. This can speed up reading operations. Therefore, current mode reading is preferred in many specific examples of the present invention. In a specific example of writing to a memory cell, a voltage source may be selected as a forcing function to drive the block line. In addition, bidirectional input / The output bus can be driven by another voltage source. The input / output bus (borrow selection switching transistor) is connected to the bit line in the selected row, so the selected memory cell (located in the selected block) The intersection of the line and the selected bit line is driven by two voltage sources: one on the block line and the other on the input / output bus. The large voltage difference between the two voltage sources will be directly added to Both ends of the selected memory cell achieve a voltage mode

Page 49 V. Description of the invention (45) (Large voltage swing on block lines and bit lines) Write β Although voltage mode writes are more complicated because of the need to charge and discharge high-capacity word lines and bit lines Slow, but this voltage mode write is still preferred in some specific examples of the invention. If necessary, voltage mode writing can provide very high currents through the memory cells, which is advantageous in many specific examples of state changing elements such as amorphous semiconductor anti-fuse. In some specific examples of voltage mode writing, it may be desirable to limit the maximum current to a certain value. One possible benefit of limiting the maximum current is to reduce the effect of the current along the array's conductor multiplied by the voltage drop of the resistor (IR) to ensure a consistent stylized energy transfer to each memory cell, regardless of the cell's location within the array Impact. Consistent stylized energy will be important, because the properties of some state-changing component materials may be sensitive to the stylized energy ^ In some specific examples, the state is changed. The voltage required to program the variable element may exceed the surrounding transistor Voltage capability. This is especially noticeable when transistors are being reduced due to small size requirements (such as channel lengths less than 0.2 microns). In these cases, the peripheral circuits can be arranged such that during the write cycle, the column decoder operates from a + V volt power supply, while the row shredder and row input / roll out circuits and write data driver from a -V volt Power operation. This arrangement adds a voltage difference of 2xV volts to both ends of the memory cell to be written ((+ V)-(-V) = 2xV), and at most two volts across any transistor. The foregoing describes a non-volatile memory that allows vertical stacking in very high density arrays.

Page 50

Claims (1)

42556 1 — ^^, 丨 _16. Patent application scope! · A memory unit includes: a guiding element for providing enhanced current flowing through the guiding element in one direction: and a state changing element, It is used to maintain a programmed state. The state changing element is connected in series to the guiding element so that the guiding element and the state changing element provide a two-terminal unit; wherein the guiding element and the state changing element are vertically aligned with each other. 2. The unit according to item 1 of the patent application scope, wherein the guide element is made of polycrystalline stone. Element, where the polycrystalline silicon is doped, its -diode element, its source region element, its source region element, its polar body. The guiding element is a field or the drain region. The guide element is a domain or a drain region. The guide element is a unit, and the guide element is a unit, which makes the guide unit be 3. As in the second item of the scope of patent application, a diode is formed. 4. For the single metal-semiconductor Schottky (item 1 of the scope of patent application) 5. For the single-junction field effect transistor (item 丨 of the scope of patent application), its gate is connected to 6. • If the scope of patent application 1 Single field-effect transistor with its gate connected to 7 · If the PN junction of the first patent application is formed in the amorphous semiconductor II. 8. If the single zener of the patent application ) Two carcasses. 9. As a single item in the scope of patent application, burst diode. 10. As for the unit of the scope of application for patent item 丨 wherein the guide element is a Page 51 42556 1 6. Scope of patent application Tunneling diode. 11. The unit of claim 1 in which the guiding element is a four-layer diode (SCR). 1 2. The unit according to item 1 of the patent application scope, wherein the state changing element is an anti-fuse. 1 3. The unit according to item 12 of the patent application scope, wherein the anti-fuse is formed of polycrystalline silicon. 14. The unit according to item 12 of the patent application scope, wherein the anti-fuse includes silicon dioxide. Wherein the state changing element, which state changing element, which state changing element, which state changing element, which state changing element, which state changing element 1 Electricity destroys anti-fuse. 16. The unit of item 1 in the scope of patent application is a polycrystalline semiconductor anti-fuse. 1 7. If the unit in the first item of the patent application scope is an amorphous semiconductor anti-fuse. 1 8. If the unit in the scope of the patent application is item 1 is a metallic incandescent wire electronic mobile fuse □ 1 9. If the unit in the scope of the patent application is item 1 is a polycrystalline silicon resistance fuse. 2 0. The unit of item 1 in the scope of the patent application. The angle trap induces hysteresis. 21. If the unit in the first item of the patent application is a ferroelectric capacitor. Among them, the state changing element 22. As the unit of the scope of patent application No. 1 Page 52 6 'Patent Application Scope Uses the Hail effect device. 2 3 · If the unit of the scope of patent application is item 1, wherein the guiding element includes a diode and the state changing element includes an anti-fuse, and wherein the diode can carry a current sufficient to change the state of the anti-fuse . 24. The unit of claim 1 wherein the guiding element comprises a recrystallized semiconductor. 2 5. The unit according to item 1 of the patent application scope, wherein the guiding element and the state changing element include amorphous silicon. 2 6. The unit according to item 1 of the patent application scope, wherein one of the two terminals of the unit is connected to a block line. 27. If the unit under the scope of the patent application is No. 26, the other terminal of the two terminals of the unit is connected to a bit line. 2 8. A memory unit comprising:-a columnar body having a generally rectangular cross-section, and at one end of the columnar body there is a guiding element that is more conductive in one direction, and the columnar body The other end has a state changing element for recording a state. 2 9. The memory unit according to item 28 of the patent application scope, wherein the guiding element comprises a diode. 30. The memory cell according to item 29 of the patent application scope, wherein the diode includes polycrystalline silicon. 3 1. The memory unit according to item 28 of the patent application scope, wherein the state changing element includes a dielectric breakdown anti-fuse. 3 2. The memory unit according to item 31 of the patent application scope, wherein the counter-insurance Page 53 6. Scope of patent application The fuse consists of a layer of dioxide of dioxide sandwiched between two layers of polycrystalline stone. 3 3. The memory unit according to item 28 of the patent application scope has a first conductor in contact with the guiding element, and the width of the first conductor is approximately equal to one side of the rectangular cross-section. 3 4. If the memory unit of claim 33 has a second conductor in contact with the state changing element, the width of the second conductor is approximately equal to the other side of the rectangular cross section. 3 5. A memory array comprising: a plurality of first conductors spaced apart in parallel and approximately coplanar; a plurality of second conductors spaced apart in parallel and approximately coplanar, the second conductors are arranged in The first conductors are substantially vertically above and separated from the first conductors, the first conductors and the second conductors are substantially orthogonal to each other; and a plurality of first memory cells, each of which is disposed on the first conductors One of the conductors and one of the second conductors are located at the intersection of the vertical projection of the first conductor and the second conductor, and the units are vertically aligned with at least one of the conductors. 36. For an array in the scope of patent application item 35, wherein the cells are aligned with the first conductor and the second conductor. 37. In the case of an array in the scope of patent application No. 35, each of these units includes a guide element and a state change element. 3 8. A memory array comprising: a plurality of first conductors spaced apart to be parallel and substantially coplanar; a plurality of second conductors spaced apart to be parallel and substantially coplanar, the second conductors being arranged at The first conductors are substantially vertically above and separate from Page 54 Λ2556 1_ 6. The scope of the patent application is separated, the first conductors and the second conductors are substantially orthogonal to each other; many first memory cells, each of which is arranged in one of the first conductors And one of the second conductors and located at the intersection of the vertical projection of the first conductor and the second conductor; a plurality of third conductors spaced apart to be parallel and substantially coplanar, and the third conductors are arranged in the When the second conductor is substantially vertically above and separated from it, the third conductors are arranged in the same direction as the first conductors; and a plurality of second memory cells, each of which is disposed on the second conductors. One of the conductors and one of the third conductors are located at the intersection of the vertical projection of the second conductor and the third conductor. 39. The array of claim 38, wherein the first unit and the second unit are vertically aligned with each other. 40. For the array in the 38th area of the patent application, wherein the first unit and the second unit are staggered with each other. 41. In the case of the array in the 38th aspect of the patent application, each of the first unit and the second unit includes a guide element and a state change element. 4 2. The array of claim 41, wherein the guide elements of the first and second units are connected to the second conductors. 4 3. The array according to item 41 of the scope of patent application, wherein the state changing elements of the first and second units are connected to the second conductors. 44. The array of claim 38, wherein the first and second units have a generally rectangular cross section. Page 55 425561 6. Scope of patent application 45. The array of the scope of patent application item 38, wherein the first and second units include polycrystalline silicon and silicon dioxide. 4 6. The array of claim 38, wherein the first and second units include polycrystalline silicon. 47. The array of claim 38, wherein the array is fabricated on a silicon substrate. 4 8. The array of claim 47, including a first contact point, extending from one of the second conductors to a first area within the substrate. 49. The array of claim 48, including a second contact point, extending from one of the first conductors to a second area within the substrate. 50. The array of claim 38, wherein the first and second conductors include a high-marry point metal. 51. The array according to item 50 of the scope of patent application, wherein the high melting point metal is a crane. 5 2. The array of claim 38, wherein the first and second conductors are a silicide. 5 3. A kind of memory array, including: a number of conductors on the layers 1, 2, 3, 4 ..., which are parallel and separated from each other, and the conductors in the odd layers such as 1, 3 ... It is arranged in the first direction, and the conductors in the even layers such as 2, 4, ... are arranged in a second direction substantially perpendicular to the first direction, and a plurality of memory units each having an input terminal and an output terminal. Arranged between conductors in each layer 1, 2, 3, 4, etc. Page 56 6. The input range of the unit of the patent application and the output end of the unit of the output unit of the unit and the input end of the unit 54. For example, the array terminal of the 53rd range of the patent application is connected to the odd layer 1, 3 ... The conductors in the etc. are connected to the conductors in the even-numbered layers 2, 4 .... 5 5. As for the array of item 53 of the patent application, the terminals are connected to the conductors in the odd-numbered layers 1, 3, etc. The sub-connects are connected to the conductors in the even-numbered layers 2, 4, .... 56. As for the array in the scope of patent application No. 54 or 55, 1 includes a guide element / early pack element connected between an input terminal and an output terminal. Every year, the parts and status are changed. The units are large, and the units include silicon. 5. For example, the array of the patent application scope of item 3 is a rectangular cross-section. 5 8. Arrays and silicon dioxide such as those in the scope of patent application No. 53. Among the layers 1 and 59 of the layer 1 ^ The array conductors of item 53 in the scope of patent application are vertically aligned with each other. And the layer 60 * such as the array of the scope of the patent application No. 53, the combination of the τ layer 1 2 / ...-the conductors in the group are staggered in the vertical direction 61. Such as the scope of the patent application No. 53 is crystalline silicon. "Heavenly" among them are conductors. 62. For example, the array of patent application No. 53 is manufactured on a silicon substrate. ,, Τ and the array are in a 63. As in the scope of the patent application No. 62-the conductor-extending to the contact point of the substrate. From the odd-numbered layers 1, 3 64. If the array of the scope of the patent application number 62, including from the even-numbered layers 2, 4, 6, high Xu t formed straight four or five, including at least-one from the most I The contact is extended from one of the conductors in the scope of the patent application to the contact point of the substrate 6 5. As in the array of the scope of the patent application item 6 2-, the layer extends to the contact point of the substrate. 6 6. As in the case of item 62 of the scope of the patent application, a plurality of contact points are formed for each layer. 6 7. A process for manufacturing a memory array (a) forming a first layer of conductive material; including: (b) forming a plurality of second layers to define the memory cells on the & layer (c) pairs The second layer is made into a long strip; Thousands of lines are separated (d) The first layer of money is engraved to align the strip formed by the second one (e) with the insulating material interposed between the first layer; Between the strips; 4 strips and the conductor layer forming the second layer from the first, ^ '' continuation () on the given strip; the marginal material and a number of layers from the _a% -layer pi The fourth layer is used to define the second (h) to the third-largest memory unit. * ^ The four layers of Le make patterns to become many 成为 &gt; 'long strips' from each line and divided into f ! 3 The square Θ winter m arranged in the strip formed by the fourth layer of Yu Shanjiu is formed by the strip formed by the first layer; it is roughly perpendicular to the direction of &amp; (i) the remaining column _ The strip formed by the layer f The layer and the strip formed by the second layer are aligned with the sixth layer. On the strip; Λ2556 1 VI. Patent application scope ^^ The pattern of the fifth layer is made into a number of flat conductors, and the configuration of these conductors is approximately perpendicular to the fourth. '彳 ,, and set additional memory units. For the 啫 conductor, repeat step (a) to add the repeat step (a) to add a dielectric 69 if you apply for it, and step 67 (i) for the process of applying patent scope item 67. ), ^ 7〇. If the process of applying for the scope of the patent No. 69, the procedures of the scope of No. 68 range. 7 1. The processing procedure of item 67 of the scope of patent application 戽 step (i) many times. 72. For example, the procedure of item 71 of the scope of patent application shall be followed by the procedure of item 68 of the scope of patent. 73. If the processing procedure of the scope of application for item 67 of the patent is applied, its quality is added and it is in the step of -® y * and 1 level. After the layer is engraved and before the third layer is formed-grinding. The processing procedure in the scope of patent application No. 73 includes chemical mechanical polishing. Mo Qianbu 75 · The processing procedure of No. 67 of the scope of patent of Rushen, including Shen-yuan, and drawing it back to flattening, and the name of Zhuang and 'yi' are formed by the second layer between (d) and (e) Strips. This procedure is described in item 76. Such as the contention of the 67th patent procedure, the first layer and the fourth layer include a polycrystalline silicon layer and a silicon dioxide layer. 77. The process of claim 1, wherein the polycrystalline silicon is doped so that each memory cell includes a diode. I side Page 59 88. The process of claim 87, wherein the low pressure chemical vapor deposition (LPCVD) deposition method. Use 89, such as the processing procedure of the 87th patent application, which makes the silicon use 556 1 Sixth, the patent application of which the Shi Xi use where the dream uses plasma and chemical vapor deposition (PECVD) deposition. 90. The processing procedure according to item 87 of the scope of patent application Physical vapor deposition (PVD) deposition. 9> 1. As stated in the patent procedure No. 7 of the processing procedures Ultra-major chemical vapor deposition (UHVCVD) deposition. 92. — A kind of memory, including: a single-stone substrate, a column address decoder, a row address decoder, and input and output circuits formed on and in the substrate; a 5 memory array with many row conductors With the column guide, the body is formed above the substrate and is electrically connected to the decoders and input / output circuits; the array is red ^ ^ a, the layers are separated and parallel ^ th ^ th order and approximately coplanar The conductors of the face; the conductors of the face, the body; the parallel and generally coplanar conductors; the conductors are generally perpendicular to the conductors; and the remote / wrong &amp; a memory between the layers Unit, each unit 93 is one of the conductors and one of the rows of conductors. The device is in the memory of item 92 of the Ershanli range, in which the rows of decoders are folded, and the output circuits are folded below the array and connected to the lines of the guideline. In mind, the array in # is divided into multiple sub-arrays.