_07_ί 4231 Λ; 五、發明說明（） 5-1發明領域： 經濟部智慧財產局P'工消費合作社印製 本發明與一種半導體製程的方法有關，特別是一種形 成淺溝渠隔離的方法。 5-2發明背景： 在今曰的積體電路中，單一晶片上通常可以建立至少 數十萬個半導體元件，這些元件之間都必需在電性上加以 隔離，以確保操作的獨立性而不會互相影響。於是，分隔 不同元件或半導體元件之不同功能區域的隔離方法就成 為金氧半場效電晶體（M0S)製程中的一個重要技術。對於 高積集度的積體電路來說，元件之間不適當的隔離會產生 漏電流而消牦大量的功率，或是造成暫時性或永久性的電 珞損壞。 區域氧化隔離法（L0C0S)乃最為人所熟知的隔離技 術。LOCOS藉由氧化石夕基板的方式在主動式元件或功能 區域之間產生二氧化矽而提供了隔離。由於矽基板很容易 氧化成二氧化矽，所以L0C0S具有方法簡單及成本低廉 之優點，而成為超大型積體電路（VLSI)中廣泛使用的隔離 技術。然而，由於積體電路的製造趨向高積集度，使得 L 0 C 0 S遭遇到尺寸難以隨之調降的瓶頸。 溝渠隔離法（trench isolation)，或是稱為淺溝渠隔離 ---1^----------裝·-------訂---------線 (?r先閱讀背面之注意事項再填寫本頁) 夂纸張尺度:¾用中囤S家滓準（CNS)A4規格（210 X 297公坌） 4231 00 ^ !________B7 五、發明說明（） 法（shallow trench isolation, STI)，是另一種適用的隔離 技術。此方法係在半導體基板中形成溝渠區域.並將絕緣 材料填入溝渠區域中以提供主動元件間或不同的丼區之 間的絕緣隔離。一般而言，溝渠隔離法較區域氡化隔離法 更容易應用於高積集度的積體電路卞。 對於深次微米CMOS之製程來說，傳統的LOCOS隔 離遭遇到許多困難，例如烏缘效應的侧向延伸過大，平坦 性不足，區域場氧化層稀薄效應，及應力產生之基板缺陷 等=對於LOCOS調降尺寸主要的挑戰在其尺寸縮小時區 域場氡化層變薄，烏*彖結構，以及場植入侵害。對於未來 的CMOS技術而言’最有效的元件隔離方法不但要能提 供主動£域與隔離區域間的轉換’對元件特性或形態所產 生的衝擊也必須最小。所以能直接符合上述需求。 —J—^------裝--------訂. (t先閱讀背面之注意事項再填寫本頁) .經 濟 部 智 慧 財 產 局 員 工 消 费 合 杜 印 習知形成淺溝渠隔離的方法通常包含下 氧化法形成一墊氡化層於一半導體基板上； 層於此墊氧化層上；塗佈一光阻層於此氣化 影製程形成該光阻層的圖案，以定義出此半 形成溝渠之處；形成該氮化矽層以及該塾氣 以曝露出欲形成溝渠之處；藉由光阻層為罩 性蝕刻於此半導體基板中形成一溝渠；以化 (chemical vapor deposition; CVD )形成一 於此丰導體基板上，並填滿於此溝渠中；以 列步驟 形成一 矽層上 導體基 化層的 幕1以 學氣相 氧化矽 化學機 氬化矽 :以微 板上欲 圖案， 非等向 沈積法 層覆蓋 械研磨 % 本纸張义度適用中國國家捺革（CNS)A4規格（210 297公:i )_07_ί 4231 Λ; V. Description of the invention (5-1) Field of the invention: Printed by P 'Industry and Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economics The present invention relates to a method for semiconductor manufacturing, especially a method for forming shallow trench isolation. 5-2 Background of the Invention: In today's integrated circuits, at least hundreds of thousands of semiconductor components can usually be built on a single chip. These components must be electrically isolated to ensure the independence of operation. Will affect each other. Therefore, the isolation method to separate different functional areas of different elements or semiconductor elements has become an important technology in the metal-oxide-semiconductor field-effect transistor (MOS) process. For high-integration integrated circuits, improper isolation between components can cause leakage currents to dissipate a large amount of power, or cause temporary or permanent electrical damage. Regional oxidation isolation (LOC0S) is the most well-known isolation technique. LOCOS provides isolation by generating silicon dioxide between active components or functional areas by oxidizing the stone substrate. Because the silicon substrate is easily oxidized to silicon dioxide, L0C0S has the advantages of simple method and low cost, and has become an isolation technology widely used in very large scale integrated circuits (VLSI). However, as the manufacturing of integrated circuits tends to have a high degree of integration, L 0 C 0 S encounters a bottleneck that is difficult to reduce the size. Trench isolation (trench isolation), also known as shallow trench isolation --- 1 ^ ---------- equipment (? r first read the precautions on the back before filling out this page) 夂 Paper size: ¾ Use in the store S house standard (CNS) A4 size (210 X 297 public 坌) 4231 00 ^! ________ B7 V. Description of the invention () Shallow trench isolation (STI) is another suitable isolation technology. This method forms a trench region in a semiconductor substrate, and fills the trench region with an insulating material to provide insulation isolation between active devices or between different trench regions. Generally speaking, the trench isolation method is easier to apply to integrated circuits with high integration than the regionalized isolation method. For deep sub-micron CMOS processes, traditional LOCOS isolation encounters many difficulties, such as the excessive lateral extension of the Ubonus effect, insufficient flatness, the thinning effect of regional field oxide layers, and substrate defects caused by stress, etc. = For LOCOS The main challenge of downsizing is that as the size of the area is reduced, the field field thinning layer becomes thinner, the black structure, and the field invasion damage. For future CMOS technology, the most effective method of component isolation must not only provide active switching between the domain and the isolation region, but also have the least impact on the characteristics or morphology of the device. So it can directly meet the above requirements. —J — ^ ------ Equipment -------- Order. (T read the precautions on the back before filling this page). The employee ’s knowledge and consumption of the Intellectual Property Bureau of the Ministry of Economy form a shallow trench. Isolation methods generally include forming a padding layer on a semiconductor substrate by a lower oxidation method; forming a padding layer on the padding oxide layer; coating a photoresist layer on the vaporization process to form a pattern of the photoresist layer to define The half-ditch is formed; the silicon nitride layer and the tritium are exposed to expose the place where the trench is to be formed; a photoresist layer is used as a cover etch to form a trench in the semiconductor substrate; deposition (CVD) is formed on the conductor substrate and fills the trench; a curtain of a conductor-based layer on a silicon layer is formed in a series of steps 1 Patterns on the board, non-isotropic deposition method, layer overlay, mechanical grinding,% The paper's meaning is applicable to China National Leather (CNS) A4 specification (210 297 male: i)
經濟部智慧財產局員工消費合作社印製 五、發明說明（） 法（chemical mechanical polishing: CMP )研磨此氧化 5夕層, 以遠到全面性平坦化；剝除氮化矽層：最後，以稀釋氣氣 酸（DHF )作為蝕刻劑，剝除墊氡化層，至此’淺溝渠障 離的製程便告一段落。 然而，在上述的習知技術中，常常遭適的問題是： (一） 在以CMP研磨氧化矽層的步驟中，氧化矽層的研 磨速率大於氮化矽層的研磨速率，因此會形成一碟形凹陷 效應（dishing effect)。 (二） 在以CMP研磨氧化梦層的步戰中，氧化矽層與氣 化矽層的研磨選擇比僅有3至5，此無法作為有效之終點 偵測的依據。 (三） 在以濕蝕刻法剝除墊氧化層的步驟中，由於墊氧化 層以及氧化矽層分別是以CVD以及熱氡化法所形成的，所 以墊氧化層的蝕刻速率會遠小於氧化矽層，如此將會造成 STI邊角凹陷效應而導致次臨限電流（sub-threshold current)偏大，換言之’其會使後續形成電晶體在電路設 計必須關閉時卻反而導通’此會使良率降低。 5-3發明目的及概述： 鑒於在習知形成淺溝渠隔離的技術中，並無法避免碟 形凹陷效應、邊角凹陷效應，以及無法提供一有效的CMP 終點偵測。所以本發明在此提出一種形成淺溝渠隔離的方 本紙張尺度適用中!3园家螵4 (CNS)A'l現格（2]Ό ί< 297公.¾ ) — — — IMI1JIIH - i 1! I--< — 1------ -'请先閱t#背面之、在%事項角填舄衣頁} 42310 經濟部智慧財產局員工消費合作社印製 ___________B7---- 五、發明說明（） 法，並且在形成淺溝渠隔雖時避免碟形凹陷效應、邊角凹 陷效應以及提供一有效的CMP終點偵測。 本發明的步驟概述如下：形成一墊氧化層（Pad oxide ) 於半導體基板上；形成一第一氮化矽層（Si〗N4)於該墊氧 化層上；以微影製程形成该光阻層的圖案’以界定出一欲 形成溝渠的區域；以該光I?且層的圖案為蝕刻遮罩’蝕刻該 垫氧化層以及該第一氮化矽層，以形成一第—氮化矽層的 圖案，用以曝露出欲形成溝渠的區域；移除該光阻層的圖 案後，以該第一氮化矽層的圖案為蝕刻遮罩’蝕刻上述半 導體基板，以形成溝渠於半導體基板中。 溝渠形成之後，形成·-襯裡層（丨inerlayer)於該溝渠 中；形成一第二氮化矽層於該第一氮化矽層以及該襯裡層 之上；形成一多晶矽層於该第二氮化矽層上；形成一第一 氣化矽層於該多晶矽層之上’並填滿溝渠；以化學機械研 磨法研磨該第一氧化矽層以形成一氧化石夕凸起物’並使用 多晶矽研漿（poly slurry )，此多晶矽研漿使得多晶矽層的 研磨速率遠大於第一氧化石义層的研磨速率’並且’此多晶 矽研漿亦使得多晶矽層的砑磨速率遠大於第二氮化矽層的 研磨速率，如此即可避免碟形凹陷效應，並且可以第二氮 化矽層作為研磨終止層；以熱氧化法轉換部份的多晶矽層 為第二氧化矽層；移除該第一氮化矽層以及該第二氮化矽 層；形成一氮化矽層間陈壁（sPacer )於該氧化矽凸起物的 n --- l f- - - n t ^ I I I J. - I I (請先閱讀背面之注意事項再填寫本頁) 訂. 本纸張尺度透用中國國家谍4MCNS)A.l規格（210 x 297公 4231 〇〇 r _Β7_五、發明說明（） 邊角；移除該墊氧化層；最後，移除該氮化矽層間隙壁。 經濟郢智慧財產局員工消費合作社印製 明I 說 單 簡 式 圖 4 列 下 以 輔 中 字 文 明 說 之 後 往 於 將 例 施： 實述 佳闡 較的 的細 明詳 發更 本做 形 圖 於 層 化 氮 1 第 及 以 層 化 氧 墊 成 形 明 發。 本圖 為面 圖剖 一 的 第上 板 基 的 上 之 潛 化 氣 \ 第 於 層 阻 光 ί 成 形 明 發 本 為 圖 二。 第圖 面 剔 圖 面 剖 的 中 之 板 基 於 域 區 渠 溝 成 形 明 發 本 為 圖 三 第 基 於 層 矽 晶 多 及 以 層 〇 矽圖 化面 氧Αί 一 的 第層 成矽 形化 明氮 發二 本第 為蓋 圖覆 四並 第’ 上 板 面 剖 的 後 之 層 矽 化 氧 第 磨 研 ΡΜ C 以 明 發 本 為 圖 五 第 (請先閱讀背面之注意事項再填寫本頁) 裝 % 圖 圖 面 剖 的 層 矽 化 氧二 第 為 換 轉 層 矽 晶 多 將 明 發 本 為 圖 六 第 層 矽 化 氛二 第 及 以 層 矽 化 第 除 剝 明 發 本 為 圖 七 第 本紙張尺度通用中13固家標準（CNSM.l規格（210 公发） B7 五、發明說明（） 圖 面 剖 的 後 之 面 剖 的 上 之 板 基 於 層 矽 化 IL 三 第 成 形 明 發 本 為 圖 八 第 圖 圖 面 剖 的 壁 隙 間 層 矽 化 氣 成 形 明 發 本 為 圖 九 第 後 之 壁 隙 間 層 化 氣 及 層 化 氧 墊 除 剝 明 發 本 為 圖。 十圖 第面 剖 的 明 說 細 詳 明 本發明在此揭露一種形成淺溝渠隔離方法。此方法包 括一些為人所熟知的技術’例如微影、蝕刻或是化學氣相 沉積法（CVD)等等，將不予以詳述。另外，本發明利用多晶 矽研漿對不同材質的研磨選擇比以避免碟形凹陷效應 (dishing effect )，以及作為化學機械研磨的終點偵測β 此外，在剝除墊氧化層時，以氮化矽層間隙壁避免邊角效 應所之次臨限電流。 -------------- 裳--- -- ί踌先閱讀背面之注意事項填寫本頁) 訂 線 經濟部智«?財產局員工消費合作社印*!,Λ 請參閱第一圖’基板20為晶格方位〈IQP之單晶矽。 一塾氧化層22形成於此基板20的表面上，此墊氧化層22 的厚度約為1 50-300埃，以一較佳實施例而言，此墊氧化 層22可以熱氧化法形成之。接著’第—氮化矽層（） 24a形成於此墊氧化層22的表面上，以作為後續製程中蝕 本或張尺度用1f7 g國家樣準（CNS)iVi規格（210 X 297公爱了—"'1 ---------Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (chemical mechanical polishing: CMP) This oxide layer is polished to flatten as far as it will go. Stripping the silicon nitride layer: Finally, dilute the gas. Gas acid (DHF) is used as an etchant to strip the padding layer, and the process of 'shallow trench isolation' comes to an end. However, in the above-mentioned conventional techniques, the appropriate problems are often encountered: (1) In the step of polishing the silicon oxide layer by CMP, the polishing rate of the silicon oxide layer is greater than the polishing rate of the silicon nitride layer, so that a The dishing effect. (2) In the CMP polishing of the oxide oxide layer, the polishing selection ratio of the silicon oxide layer to the siliconized silicon layer is only 3 to 5, which cannot be used as a basis for effective endpoint detection. (3) In the step of stripping the pad oxide layer by a wet etching method, since the pad oxide layer and the silicon oxide layer are formed by CVD and thermal annealing, respectively, the etching rate of the pad oxide layer will be much lower than that of silicon oxide. This will cause the STI corner depression effect and cause a large sub-threshold current, in other words, 'it will cause the subsequent formation of the transistor when the circuit design must be turned off but on.' reduce. 5-3 Purpose and Summary of the Invention: In the conventional technique for forming shallow trench isolation, dishing effects, corner depression effects, and the failure to provide an effective CMP endpoint detection cannot be avoided. Therefore, the present invention proposes a standard paper for forming shallow trench isolation in the application of the scale! 3 garden furniture 4 (CNS) A'l present grid (2) Ό < 297 male. ¾) — — — IMI1JIIH-i 1 ! I-< — 1 -------'Please read the back of t # first and fill in the page in the% matter corner} 42310 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ___________ B7 ---- 5. Description of the invention () method, and avoid the dish-shaped depression effect, corner depression effect and provide an effective CMP endpoint detection when forming shallow trench isolation. The steps of the present invention are summarized as follows: forming a pad oxide layer on a semiconductor substrate; forming a first silicon nitride layer (Si} N4) on the pad oxide layer; forming the photoresist layer by a lithography process Pattern 'to define an area where a trench is to be formed; the pattern of the light I? And the layer is used as an etching mask to etch the pad oxide layer and the first silicon nitride layer to form a first silicon nitride layer Pattern to expose the area where the trench is to be formed; after removing the pattern of the photoresist layer, use the pattern of the first silicon nitride layer as an etching mask to etch the semiconductor substrate to form a trench in the semiconductor substrate . After the trench is formed, a liner layer is formed in the trench; a second silicon nitride layer is formed on the first silicon nitride layer and the liner layer; a polycrystalline silicon layer is formed on the second nitrogen layer. Forming a siliconized silicon layer; forming a first vaporized silicon layer on the polycrystalline silicon layer; and filling the trench; polishing the first silicon oxide layer with a chemical mechanical polishing method to form a stone oxide protrusion and using polycrystalline silicon Poly slurry. This polycrystalline silicon slurry enables the polishing rate of the polycrystalline silicon layer to be much higher than that of the first oxide layer. And 'This polycrystalline silicon slurry also enables the honing rate of the polycrystalline silicon layer to be much higher than that of the second silicon nitride. The polishing rate of the layer can avoid the dishing effect, and the second silicon nitride layer can be used as the polishing stop layer; a portion of the polycrystalline silicon layer is converted to a second silicon oxide layer by a thermal oxidation method; and the first nitrogen is removed. Silicon layer and the second silicon nitride layer; forming a silicon nitride interlayer wall (sPacer) on the silicon oxide bump n --- l f---nt ^ III J.-II (please first (Read the notes on the back and fill out this page). Paper size is transparently used by China National Spy 4MCNS) Al specification (210 x 297 male 4231 00_r_B7_ V. Description of the invention () Corner; remove the pad oxide layer; finally, remove the silicon nitride layer spacer The Economic and Intellectual Property Bureau employee consumer cooperative printed the statement I. Simplified form Figure 4 is listed below with the Chinese character civilization theory supplemented by the following examples: Layered Nitrogen 1 and layered oxygen pads are used to shape the hair. This picture is the top view of the upper plate base in the first section of the figure. The layered light is shown in Figure 2. The surface of the middle plate is based on the formation of the trenches in the area. The figure is based on the second layer of silicon crystals and the layer of silicon is used to pattern the surface oxygen. The first layer is siliconized and the bright nitrogen is two. The first is the cover, the fourth layer is the upper layer of the silicide oxygen, and the PMC is ground. The Mingfa version is the fifth one (please read the precautions on the back before filling this page). Sectioned layers The silicon silicide is the second conversion layer, and the silicon crystal is usually the first layer of silicon silicon in Figure 6, the second layer is silicon dioxide, and the second layer of silicon silicide is used to remove the hair, which is the 13th standard in the paper standard (CNSM. lSpecifications (210 hair) B7 V. Description of the invention () The upper plate on the back of the drawing is based on a layer of silicified IL. The third formed Mingfa is the silicified interstitial layer of the interstitial layer of the eighth figure. The formed Mingfa is shown in Figure 9 after the interlaminar gas and stratified oxygen pads are removed. The detailed description of the tenth figure and the top section The present invention discloses a method for forming a shallow trench isolation. This method includes well-known techniques such as lithography, etching, or chemical vapor deposition (CVD), etc., and will not be described in detail. In addition, the present invention uses a polycrystalline silicon slurry to select different materials for grinding to avoid dishing effects and detect end points of chemical mechanical polishing. In addition, when stripping the pad oxide layer, silicon nitride is used. Layer gap walls avoid secondary threshold currents caused by corner effects. -------------- Sang ----ί 踌 Read the notes on the back first and fill in this page) Thread of the Ministry of Economic Affairs, «? Property Bureau Employee Consumption Cooperative Seal * !, Λ Please Referring to the first figure, the substrate 20 is a single crystal silicon with a lattice orientation <IQP. An oxide layer 22 is formed on the surface of the substrate 20, and the thickness of the pad oxide layer 22 is about 150-300 angstroms. In a preferred embodiment, the pad oxide layer 22 can be formed by a thermal oxidation method. Next, a “first silicon nitride layer (24)” is formed on the surface of this pad oxide layer 22 as a subsequent etching process or a scale of 1f7 g national sample (CNS) iVi specification (210 X 297) — " '1 ---------
I 4231 0 0 B： 五、發明說明（） 刻此基板20的遮罩。此第一1化石夕層24三的厚度約為 1 5 00-2 000埃，此外，以一較佳實施例而言，此第_氣化石夕 層24a係在溫度約為650-750°C的範圍下，以：¾，堅化學氣相 沉積法（LPCVD)加以沉積。 接著請參閲第二圖’定義欲形成溝渠區域的光阻圖案 26’形成於此第一氮化矽層24a之上。接著以此光阻圈案 2 6為蝕刻罩幕，以及非等向性蝕刻法蝕刻此第一氣化石夕層 24a以及墊氧化層22，以形成具有溝渠圖案之第一氣化矽 層24a’以及曝露出半導體基板20上欲形戍此溝渠的區 域。此非等向性蝕刻法包含反應性離子蝕刻法（RIE)，其適 當之蝕刻電漿源為含氟之電漿氣體，例如CF4、CHF3、C2h 或是c3fs等等。 請參閱第三圖，在移除光阻圖案26之後，以具有溝渠 圖案之第一氮化矽層2 4 a做為蝕刻遮罩，非等向性姑刻法 蚀刻此基板20，以形成一溝渠28，此非等向性姓刻法包含 反應性離子姓刻法（RIE) ’其適當的姑刻電衆源可以是 Cl2、BCb、HBr、SF6、SiCl4的其中之一或其混合。在此非 等向性蝕刻步驟中，蝕刻此半導體基板2〇上欲形成此溝# 的區域，直到形成足以作為隔離區域的深度為止，此溝梁 28的深度約為0.35至0.5微米。接著，在約為9〇〇系U00 C的溫度下，以熱氧化法於溝渠2 8的側壁以及底部形成〆 襯裡層（丨iner layer) 25，用以修復之前此基板2〇在非等 r ----,----------裝--- (請先閱讀背面之注意事項再填寫本頁) 訂_: 經濟部智慧財產局員工消費合作社印製I 4231 0 0 B: 5. Description of the invention () The mask of the substrate 20 is engraved. The thickness of the first fossil evening layer 24 is about 15 00-2 000 Angstroms. In addition, in a preferred embodiment, the first gasified evening layer 24a is at a temperature of about 650-750 ° C. Under the range of: ¾, LPCVD is used to deposit. Then referring to the second figure, a photoresist pattern 26 'defining a trench region to be formed is formed on the first silicon nitride layer 24a. This photoresist circle 26 is used as an etching mask, and the first vaporized stone layer 24a and the pad oxide layer 22 are etched by anisotropic etching to form a first vaporized silicon layer 24a 'having a trench pattern. And the area on the semiconductor substrate 20 where the trench is to be shaped is exposed. The anisotropic etching method includes a reactive ion etching method (RIE). A suitable etching plasma source is a fluorine-containing plasma gas, such as CF4, CHF3, C2h, or c3fs. Referring to the third figure, after the photoresist pattern 26 is removed, the first silicon nitride layer 2 4 a having a trench pattern is used as an etching mask, and the substrate 20 is etched by anisotropic etching to form a substrate. Ditch 28. This anisotropic last name engraving method includes a reactive ion last name engraving method (RIE). Its suitable source of electrical current may be one of Cl2, BCb, HBr, SF6, SiCl4, or a mixture thereof. In this anisotropic etching step, a region where the trench # is to be formed on the semiconductor substrate 20 is etched until a depth sufficient as an isolation region is formed. The depth of the trench beam 28 is about 0.35 to 0.5 μm. Next, at a temperature of about 900 series U00 C, a thermal oxidation method is used to form an inner layer 25 on the sidewalls and bottom of the trench 28 to repair the substrate 20 previously. ----, ---------- Equipment --- (Please read the notes on the back before filling out this page) Order_: Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
Λ7 經濟部智慧財產局員工消費合作社印製 五、發明說明（） 向性蝕刻步驟中所遭受的損傷，同時也使溝渠的邊角圓滑 請參閱第四圖，一第二氮化矽層24b形成於第一氮化 矽層24a以及襯裡層25之上，其厚度約為200至500埃。 並且，一未摻雜的多晶矽層30接著形成於此第二氮化矽層 24b之上’其厚度約為300至800埃。隨後以第一氧化矽 層32形成於此未摻雜的多晶矽層30之上，並填滿此溝渠 28。形成此第一氧化矽層32a的適當方法包含LPCVD、 SACVD(次常壓CVD)，或是HDPCVD(高密度電漿CVD)， 形成此第一氡化矽層32a的材質包含正乙酯矽酸氧化物 (tetra-ethyl-ortho-silicate-oxide，TEOS-oxide)，硼碟矽玻璃 (BPSG)，磷矽玻璃（PSG)，硼矽玻璃（BSG)，或未摻雜的矽 玻璃（USG)等材枓》 請參閱第五圖，為達到全靣性的平坦化，以化學機械 研磨法（CMP)研磨此第一氧化矽層 32，直到約為第二氮化 矽層24b的上表面為止，值得注意的是，在此化學機械研 磨步驟中，係使用一多晶石夕研衆（poly slurry )，此多晶5夕 研漿對於多晶矽以及氡化矽的研磨選擇比遠大於1，約為 5 0比1;對於多晶矽以及氮化矽的研磨選擇比亦遠大於1 1 約大於80比1。於是，在此化學機械研磨步驟時’當研磨 至多晶矽層3 0時，此多晶矽層3 0的研磨速率會比第一氧 化矽層3 2的斫磨速率更快，因此，在多晶矽層3 0研磨终 ---r---f---- ! ^--------訂· 請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中因囤家標準（CNS)A4規格（2】〇χ2ίί7公发） 4231 0〇Λ7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () Damage suffered during the isotropic etching step, while also making the corners of the trench smooth. Please refer to the fourth figure, a second silicon nitride layer 24b is formed On the first silicon nitride layer 24a and the backing layer 25, the thickness is about 200 to 500 Angstroms. In addition, an undoped polycrystalline silicon layer 30 is then formed on the second silicon nitride layer 24b 'and has a thickness of about 300 to 800 angstroms. A first silicon oxide layer 32 is then formed on the undoped polycrystalline silicon layer 30 and fills the trench 28. Suitable methods for forming the first silicon oxide layer 32a include LPCVD, SACVD (subnormal pressure CVD), or HDPCVD (high density plasma CVD). The material for forming the first silicon oxide layer 32a includes n-ethyl silicate. Tetra-ethyl-ortho-silicate-oxide (TEOS-oxide), borosilicate glass (BPSG), phosphosilicate glass (PSG), borosilicate glass (BSG), or undoped silica glass (USG) Please refer to the fifth figure. In order to achieve full flatness, the first silicon oxide layer 32 is polished by chemical mechanical polishing (CMP) until it is about the upper surface of the second silicon nitride layer 24b. It is worth noting that, in this chemical mechanical polishing step, a polycrystalline silicon slurry (poly slurry) is used. The polycrystalline silicon slurry has a polishing selection ratio of polycrystalline silicon and tritiated silicon which is much greater than 1, about It is 50 to 1; the polishing selection ratio for polycrystalline silicon and silicon nitride is also much greater than 1 1 and greater than 80 to 1. Therefore, in this chemical mechanical polishing step, when the polycrystalline silicon layer 30 is ground, the polishing rate of the polycrystalline silicon layer 30 will be faster than the honing rate of the first silicon oxide layer 32. Therefore, in the polycrystalline silicon layer 30, Grinding end --- r --- f ----! ^ -------- Order · Please read the precautions on the back before filling out this page) This paper standard is applicable to the standard of the store (CNS) A4 specifications (2) 〇χ2ί7 public hair) 4231 0〇
五、發明說明（） 了時，此溝渠中將會形成一凸起於第二氮化矽層74b上表 面的氧化碎6起物32a ,如此即可避免碟形四陷效應 (dishingeffe⑴的產生。而且，當由多晶妙層3〇研磨至 第二氣化㈣24b時，研磨速率會有一明顯的改變，此研 磨速率明顯的改變可作為一有效的研磨終點偵測（endp〇int detection) ° 請參閱第六圖，在上述化學機械研磨步驟之後，此 渠的側壁以及底部仍有殘留的多晶矽層3〇存在，因此需 此多晶矽層3 0轉換為第二氧化矽層3 2 b，或是至少將此 摻雜之多晶矽層3 0的側壁局部轉換為第二氧化矽層3 2b 在此轉換步驟中，熱氧化法是—較佳的方法。 接著，請參閱第七圖，以熱磷酸將上述第一氮化矽層 24a以及部份第二氮化矽層24b移除。 請參閱第八圖，形成第三氮化矽層24c於此基板上， 用以覆蓋墊氧化層22、第二氮化矽層24b、氧化矽凸起物 3 2a以及第二氧化矽層32b。形成此第三氮化矽層24c的方 法則包含LPCVD。 ---r---;--------裝--- (請先閱讀背面之注意事項再填寫木頁) 訂 .泉 經濟部智慧財產局員工消費合作社印制办 請參閱第九圖，此第三氮化矽層24c形成之後，以非 等向性蝕刻法形成氬化矽層間隙壁（spacer ) 24d，此氮化 s夕層間隙壁24d大約復蓋於氧化矽凸起物32a以及第二氡 ί匕矽層32b的逢角之上。至於此非等向性蝕刻法包含反應 10 本纸張尺度適用中囷囤家浮車（CNSM〖規格（21ϋ,ΐ 297公坌） l Ο 〇 i23V. Description of the invention () When this happens, an oxide chip 32a protruding on the upper surface of the second silicon nitride layer 74b will be formed in this trench, so that the dishing-like sink effect can be avoided. In addition, when grinding from the polycrystalline layer 30 to the second gasification layer 24b, the grinding rate will change significantly. This obvious change in the grinding rate can be used as an effective end point detection. ° Please Referring to the sixth figure, after the above chemical mechanical polishing step, a polycrystalline silicon layer 30 still exists on the side wall and the bottom of the channel, so the polycrystalline silicon layer 30 needs to be converted into the second silicon oxide layer 3 2 b, or at least Partially convert the side wall of this doped polycrystalline silicon layer 30 to the second silicon oxide layer 3 2b. In this conversion step, the thermal oxidation method is a better method. Next, referring to the seventh figure, the above is described with thermal phosphoric acid. The first silicon nitride layer 24a and part of the second silicon nitride layer 24b are removed. Referring to the eighth figure, a third silicon nitride layer 24c is formed on the substrate to cover the pad oxide layer 22 and the second nitrogen. Siliconized layer 24b, silicon oxide protrusion 3 2a The second silicon oxide layer 32b. The method for forming the third silicon nitride layer 24c includes LPCVD. --- r ---; -------- install --- (Please read the precautions on the back first (Fill in the wooden pages again) Order. Printed by the Office of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, please refer to the ninth figure. After this third silicon nitride layer 24c is formed, an argon silicon layer gap is formed by anisotropic etching (Spacer) 24d. The nitride spacer layer 24d is approximately covered above the angle of incidence of the silicon oxide protrusions 32a and the second silicon layer 32b. As for the anisotropic etching method, the reaction 10 This paper size is suitable for the floating car of the Chinese manufacturer (CNSM [Specifications (21ϋ, ΐ297297) l 〇 〇i23
五、發明說明（ 性離子姓刻法（RIE)，其適當的蝕刻電漿源為含氟之電衆氣 體’例如cf4、chf3、c2f6或是c3f8等等。 請同時參閱第九圖以及第十圖，此氬化矽層間隙壁24d 形成之後，進行一剝除墊氧化層22的步驟，其較佳的方法 則是濕蝕刻法，且蝕刻劑為稀釋氫氟酸（DHF )，值得注 意的是，由於上述氡化矽凸起物32a以及第二氧化矽層32b 的邊角覆蓋著氤化矽層間隙壁24d，所以可以避免溝渠邊 角凹陷效應的產生=最後，將氮化矽層間隙壁24d剝除之 後，此淺溝渠隔離的製程便告完成·> 综上所述’本發明的確可以避免碟形凹陷效應、邊角 凹陷效應，並且可以提供一有效的CMP的终點偵測。 以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之申請專利範圍；凡其它未脫離本發明所揭示之 精神下所完成之等效改變或修飾，均應包含在下述之申請 專利範圍内。 (請先閱讀背面之注意事項再填寫本頁) 裝V. Description of the Invention (RIE), the appropriate etching plasma source is a fluorine-containing electric gas such as cf4, chf3, c2f6, or c3f8, etc. Please refer to the ninth figure and the tenth at the same time. After the formation of the silicon argon spacer 24d, a step of stripping the pad oxide layer 22 is performed. The preferred method is wet etching, and the etchant is dilute hydrofluoric acid (DHF). It is worth noting that Yes, since the corners of the siliconized silicon bumps 32a and the second silicon oxide layer 32b are covered with the siliconized silicon layer spacers 24d, it is possible to avoid the occurrence of the trench corner depression effect = Finally, the silicon nitride layer gap After the wall 24d is peeled off, this shallow trench isolation process is completed. ≫ In summary, the present invention can indeed avoid the dish-shaped depression effect and corner depression effect, and can provide an effective CMP endpoint detection The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included below Patent application Inner circle. (Please read the notes on the back of this page and then fill in) installed
-I-5J 經濟部智慧財產局員工消費合作社印製 η 本^氏張尺度適用中a S家檔進（CNS)A,,1規格（21ϋ 公呈）-I-5J Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs η The size of this sheet is applicable to the CNS A, 1 specifications (21ϋ)