TW419732B - A method for gate-stack formation including a high-k dielectric - Google Patents

A method for gate-stack formation including a high-k dielectric Download PDF

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Publication number
TW419732B
TW419732B TW088111746A TW88111746A TW419732B TW 419732 B TW419732 B TW 419732B TW 088111746 A TW088111746 A TW 088111746A TW 88111746 A TW88111746 A TW 88111746A TW 419732 B TW419732 B TW 419732B
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Taiwan
Prior art keywords
layer
dielectric
gate
plasma nitriding
silicon dioxide
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TW088111746A
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English (en)
Inventor
Sunil V Hattangady
George A Brown
Malcolm J Bevan
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Texas Instruments Inc
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Publication of TW419732B publication Critical patent/TW419732B/zh

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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
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    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
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    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
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    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
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    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
    • H01L21/02332—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
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  • Engineering & Computer Science (AREA)
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  • General Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)

Description

419732 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（1 ) 相關申諝索的交互參考 下面的共同讓與之審查中專利申請案一併做為參考用： 序號 申請日期TI編號發明人 60/019,429 6/7/96 TI-23502P Hattangady 等人 601035,375 12/5/96 TI-22980P Kraft 等人 發明領域 本發明一般係相關於MOSFET電晶體的領域而更特定 於含高介電質常數閘極介電質的閘極堆疊形成。。 發明背景 目前，有一極大需求要將半導體裝置縮小來提供在半導 體晶片上增加的裝置密度，其更快且消耗較少的電源。在側邊尺 寸上此裝置的大小需要做垂直的縮放以同樣的達到足夠的裝置效 能。這個垂直縮放需要此閘極介電質的有效電氣厚度減少，以提 供所需要的裝置效能。 一氧化妙已成為較佳的閘極介電質材料。然而，較新的 技術需要二氧化矽的有效厚度低於目前所能相信的極限(例如，< 10 埃）。因此，使用較高介電質常數(高-K)材料，例如五氧化钽及鎖_ 錯-鈦是有益的。利用較高-K值的材料可允許較大的實體厚度而取 3 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） -------- I ^ i — — — —— — ^- — — 1! {請先閱讀背面之注意事項#坟寫本頁) f 419732 A7 經濟部智慧財產局具工消费合作社印製 五、發明說明（2 ) 得較低的有效電氣厚度。 不幸的疋’大部分考慮的高《值材料含有氧氣及域在— 氧氣的周圍中形成。因此，在形成期間，二氧化石夕在高‘κ值介電 質與基質之間的基質表面上形成。這樣的二氧化石夕厚度會喪失許 多因高-κ值材料而獲得的優點。 高-Κ值介電質也評估在記憶體的應用中作為儲存電容·細 胞介電質。在先前技藝的應用中，氮化銨用來在石夕上形成氮化物 層做為高-Κ值介電質形成期間進一步氧化的屏障。此高_κ值材料 接著在此氛化物屏障層上形成。然而，此氮化物屏障層有一高界 面狀態密度，其對於閘極介電質應用是有害的α 發明概要 本發明在高-Κ值介電質形成之前利用薄二氧化矽層的些 微等離子氮化(RPN)。此RPN抑制了高-Κ值介電質形成期間的氧 化作用’產生具有較薄有效電氣厚度的閘極介電質β 本發明的優點在提供具降低有效電氣厚度的閘極介電 質。 這項及其他優點對於對本技藝具普通技巧的人在併同圖 式參考本項規格後將變得明顯。 4 本紙張尺度適用中國國家標準（CNS)A4規格⑵0 x 297公爱） ----I---- ----· I----- — — — — — I 1^, (請先閱讀背面之注意事項声亀寫本頁) 419732 ΚΙ --------- Β7 發明說明（3 ) 一 - 圖式簡述 圓式中： 圊1為具有根據本發明之間極介電質的電晶體橫切面 圖；以及 圓奶為製造囷i電晶體的不同步驟中的橫切面圓。 具«實例的烊細說明 現在本發明將併同αΐ微米MOSFET電晶體來加以說 明對於熟習本技藝的那些人而言很明顯的本發明的益處可用在 其他的電晶體’其大小上對在此說明的尺寸㈣當調整^這益處 也可以用在與下面說明不同的電晶體結構，例如那些具有突起源 極/洩極區域的電晶體Ρ 根據本發明具有一閘極堆疊104的MOSFET電晶體100 顯不在圖1。電晶體100位在半導體本體1〇2中並以絕緣區域112 與其他電晶體(未顯示)分開。如顯示的絕緣區域112為淺溝絕緣。 然而’已知的本技藝中其他絕緣機制可以替代的使用。源極/洩極 區域114及洩極擴增區域116位在閘極堆疊104對邊上的半導體 主體102中。 閘極堆疊104包含多層閘極介電質^此第一層為矽·氧氮 419732 A7 B7 經濟部智慧財產局貝工消費合作社印製 五、發明說明（4 ) 化物層106。其有15埃等級的物理厚度及大於二氧化矽(〜4)且小 於矽氮化物(〜7)的介電質常數。在石夕·氧淡化物層106之上的是高_ K介電質層108 ^高-K在此係用來參考介到電質常數大於10的介 電質材料。層108通常包含一含氧高-K值介電質材料，例如Ta2〇5、 BaTi03、Ti02、Ce02或BST。然而’層108可替代的包含高_κ值 材料，其利用一讓氧由另一個來源進入到環境中的處理來形成。 此高-Κ值層108的厚度為90埃的等級。因此，此閘極介電質的 總有效電氣厚度則是矽二氧化物的15-20埃的等級。 閘極堆疊104還包含在此高-Κ值層108之上的閘電極 11〇0當多晶矽朝向在含氧高-Κ值介電質之上形成額外的二氧化 矽層時’閘電極110最好包含金屬。選定的金屬可能需要在處理 的整合項目上匹配此介電質層1〇8而其工作的功能最終指定此裝 置的臨限電壓β例如，閘極介電質11〇可以包含鎢、鋁或銅以及 一屏障層例如TiN〇在較佳具鱧實例中，此高-κ值層108包含Ta205 而此閘電極110包含氮化鈦（TiN)層之上的鎢層(W)。 現在將說明根據本發明之一具體實例形成閘堆疊1〇4的 方法。如圖2A顯示的，二氧化矽之一薄層U8在半導體主體102 的表面上形成。層118有15埃等級的厚度。層118可以儘可能的 6 1丨丨|丨|丨丨1|丨— |4^_--— I丨丨—訂· I丨— !丨— * (請先閱讀背面之注意事項再毛寫本頁) 本紙張尺度適用中國囷家標準（CNSXA4規格（210 X297公釐） 419732 A7 B7 五、發明說明（5) 薄’而仍取付-氧化物連續層。I 118的最大厚度取決於最後閉 極介電質的所要電氣厚度。針對實務上的目的，這可以是㈣微 米技術的15-20埃。 參考圖沈’二氧化矽層II8依些微的等離子體氮化(RPN) 而定。RPN將層118由二氧化石夕轉換為氮氧化石夕層1〇6。層1〇6 的有效電氣厚度因為此材料的介電質常數改變而減少。氮氧化石夕 層106有15埃等級的實際厚度而介電質常數大於二氧化石夕的㈠） 並小於氮化矽(〜7)的。 等離子體的氮氣源可以是包含先質例如N2或NH3或其混 合物的氣氣與其他加入氣體(He、Ar等等)或氧化氣體(NO、N20、 〇2等）。此等離子體最好是高密度等離子體。此等離子體可以由幾 個來源的任何一個產生。例如，可以使用下面來源中的一個：螺 旋體；螺旋共振；電子迴旋加速器共振；或是電感連結。此基質1〇2 可以是未偏壓’該情形下此離子化本質由等離子電位加速(以2〇 伏特的等級)並接著植入二氧化矽層118表面。一偏壓可施加於此 基質102來進一步的對來自等離子體的離子加速並將之植入更深 的表面。DC或RF的偏壓可以施加於基質102。如一範例，可以 使用下面的處理情形：介於1X101C to 1X1012之間的等離子密度； 7 本紙張尺度適用中國g家標準（CNS)A4規格（210 X 297公釐〉 i ϊ (請先閱讀背面之注意事項再豸寫本頁) -S* ' 經濟部智慧財產局員工消費合作社印製 419732 A7 B7 經濟部智慧財產局貝工消费合作社印製 五、發明說明（6 ) 介於1於100 seem之間的氮氣流；1到50 m陶爾等級的壓力；範 圍在77 K到773 K (500°C)之内的溫度；範圍在〇到50伏特的基 質偏壓；以及範圍在10到60秒内的期間。 如圖2C顯示的，在RPN之，高·Κ質介電質層108在 氮氧化矽層106之上形成。層108將通常包含一含氧的高_Κ值介 電質材料’例如 Ta205、BaTi02、Ti02、Ce02 或 BST » 然而，層 108 可替代的包含高-K值材料，其利用一讓氧由另一個來源進入到環 境中的處理來形成。形成高-K值介電質層1〇8的方法將隨著所使 用材料而變化。用來沈澱許多這些材料的改善方法目前正在發展 中。 在本發明的較佳具體實例中，Ta205被用來做層108。可 以用下面利用LPCVD處理的方式形成。在RPN之後，此裝置被 載入到一低溫(例如〜300°C)的熔爐中。此晶圓最好放置在端點具側 邊模擬晶圓的環形碟片的交錯槽中。此碟片及側邊模擬晶圓應塗 層至少100埃的Ta05，其他的一致厚度可能會有問題。 載入後，此熔爐泵被清洗而溫度升高到沈澱溫度(也就 是，在410·450°〇並在活性氣體引入前穩定化》N2或NH3可以在 加熱階段用做載體氣體。NH3可以確保表面維持氮化。 8 本紙張尺度適用_國國家標準（CNS)A4規格（210 X 297公釐） !裝 ---if--訂--- ------線 (請先閱讀背面之注意事項再瑣寫本頁) 419732 A7 B7 五、發明説明（ 接著引入金屬有機源在一低壓下與氧氣化學反應以便沈 澱。金屬有機源包含钽五氧化合物(^το)或鈕四氧化合物 (TATDMAE)。此钽源為黏滯液體並可以載體氣體例如透過載負鉅 到熔爐之發泡Νζ的發泡器中供應。然而，此發泡器可能必須操作 在120-150°C而長期性的穩定性可能有問題…較佳的放出技術是 要用正置換或CVD泵。此鈕源接著分配到加熱喷霧器並與載體氣 體例如M2混合，接著送到溶爐中。替代的，此组源可以藉由液體 MFC (大量氣體控制器)來提供，其注入來源液體到加熱的喷霧器 中 請 閲‘ 讀 背 面 ί 事 項 再 填 本衣 頁 訂 示範性的沈澱情形有： 壓力： 〇·1到1陶爾（典型的0.2-0.3陶爾） ΤΑΕΤΟ 流動：0.1 到 l.〇cc/min(典型的 0.2-0.4 毫升/分） 〇2 流動： 500-1000 seem (典型的 1〇〇〇 seem) N2 載體流動：500-1000 seem (典型的 750 seem) 經濟部中央標準局員工消費合作社印裝 溫度：
Time :
410-4500C 10分鐘的等級，成長率為10-15埃/分 在沈澱後，此熔爐管週期性的清洗來在冷下到卸載溫度 前去除任何的TAETO，並讓此腔回到大氣壓力。這個過程大約要 本紙張尺度適用中國國家棣率（CNS ) A4规格（2丨OX297公釐） 419732 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（8 ) 花3-4小時。替代的，RTP處理可以用在400-500°C及較短的期 間内。 高-K值層108的形成之後可以是選項的悶火來減少洩漏 並提供強健的介面。例如，此裝置可以在800°C等級溫度的氮氣中 悶火兩分鐘等級的期間，在一 RTA系統中或在溶爐中30分鐘的 等級。 參考圖2D，閘電極材料110沈澱在高·Κ值層1〇8之上。 閘電極110最好包含有金屬β此選定的金屬需要匹配介電質層 108。例如，閘電極11〇可以包含一個堆疊的鶴、銘或銅以及屏障 TiN層。在一較佳的具體實例中，閘電極no包含在具2⑻埃厚 度等級氮化鈦(TiN)層之上的一層具有800埃厚度等級的的鎢(W)。 最後’如圖2A顯示的，閘電極材料110、高_κ值層1〇8 及氮氧化矽層106被圖樣並姓刻來形成閘極堆疊1〇4 β電晶體1〇〇 的製造矽藉由植入洩極擴充區域116、沈澱並餘刻介電質來形成側 壁隔間117 ’及植入源極/洩極區域114來完成。 雖然本發明已藉由參考到說明性的具體實例加以說明， 此說明並非企圖要架構限制。此說明性具體實例的不同修改及組 合，與本發明的其他具體實例一樣的，對於熟習本技藝的人在參 10 # (請先閱讀背面之注意事項再4寫本頁) ί ^° Τ -矣- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 經濟部智慧財產局員工消費合作社印製 419732 _B7_ 五、發明說明（9 ) 考說明後可變得明顯。因此後附的申請專利範圍企圖要包含任何 這樣的修改或具體實例。 -----------i I * I I I I--—訂- — — — — I — I — - (請先閱讀背面之注意事項异4寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）

Claims (1)

  1. 419732 A8 £S C8 D8 ☆、申請專利範園 ΐ· 一種製造積體電路的方法，包含的步驟有： 在一半導體主體上形成一二氧化矽層； 提供該二氧化矽層到些微的等離子體氮化來將該二氧化碎層轉 換為氮氧化矽層； 在該氮氧化矽層之上形成一高-k值介電質層，該高-K值介電 質層的介電質常數大於10 ; 在該高·Κ值介電質層之上形成金屬層；以及 圖樣並蚀刻該金屬層，該高-Κ值介電質層，而該氮氧化石夕層 形成一閘極堆疊。 2. 如申請專利範圍第1項的方法，其中該二氡化石夕 層的厚度小於20埃。 3- 如申請專利範圍第1項的方法，其中該高-Κ值介 電質層包含從包含Ta205、BaTi〇3、Ti〇2、Ce02及BST的群組中選 出的一材料。 4. 如申請專利範圍第1項的方法，其中該金屬層包 含在氮化鈦層之上的鎢層。 5. 如申請專利範園第1項的方法，其中該些微等離 子體氮化利用包含自例如N2或NH3或其混合物的氮氣與其他加入 氣體或氧化氣體選出的先質之氮氣。 6. 如申請專利範圍第1項的方法，其中該些微的等 離子體氮化發生在範圍1到50毫陶爾的壓力下。 12 本紙張尺度適用中圃國家標準（CNS ) A4規格（210X297公釐） ---------------ir------^ * (請先閱讀背面之注^'項再墳寫本頁) 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 D8 419732 六、申請專利範圍 7. 如申請專利範圍第1項的方法，其中該些微的等 離子體氮化包含範圍在1χ1〇10到1X1012内的些微密度。 8_ 如申請專利範圍第1項的方法，其中該些微的等 離子體氮化包含範圍在1到1〇〇sccm的氮氣流動。 9· 一種MOSFET電晶體，其包含： 一在一半導體本體上的多層閘極介電質，該多層的閘極介電質 包含一層的氮氧化矽及一層的含氧的高介電質常數材料； 在該多層閘極介電質之上的金屬閘電極； 在該閘電極的第一邊上的源極區域；以及 在該閘電極的第二邊上的洩極區域。 10. 如申請專利範圍第9項的電晶體，其中該氮氧化 矽層的厚度小於20埃。 H· 如申請專利範圍第9項的電晶體，其中高介電質 常數層包含從含Ta#5、BaTi〇3、Ti〇2、Ce〇2及BST的群組中選出 的材料。 11 n I I n n n 1 I n * {請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 國 國 I中 用I料 -紙 本 準 3 I釐 公
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