TW415040B - Method for fabricating CMOS devices in integrated circuit - Google Patents

Abstract

A method for fabricating CMOS devices in integrated circuit. A P-well, a N-well and a field oxide layer are formed within a substrate. A gate oxide layer and a first silicon film are formed on the substrate. A gate is formed on the NMOS region and ion implantation is utilized to form a LDD. A sidewall is formed beside the gate and a source/drain region is formed in the NMOS region. After formation of the hard mask layer, a gate is formed on the PMOS region by photolithography and the hard mask layer on the NMOS region is remained. Then, ion implantation is employed on the PMOS region to form a LDD, and a spacer is formed on the gate in the PMOS region. Finally, a source/drain region in the PMOS region is formed by ion implantation.

Description

415040 A? B7 Printing policy of the Central Biaolangma Employee Consumer Cooperative of the Ministry of Economic Affairs 5. Description of the invention (/) Detailed description: TECHNICAL FIELD The present invention relates to a method for forming complementary metal-oxide-semiconductor field-effect transistors in integrated circuits.焉 Complementary metal-oxide-semiconductor (CMOS) is the most basic * most important component in integrated circuits. The traditional process of forming complementary metal-oxide-semiconductor transistors in integrated circuits usually requires the following five lithography steps: 1. Define the gates of the P-type metal-oxide-semiconductor region and the N-type metal-oxide-semiconductor region. pole. 2. Define the P-type metal-oxide semiconductor region (or N-type metal-oxide semiconductor region) where low-concentration ion doping is performed. 3. Define the region where low-concentration ion doping is performed in the N-type metal-oxide semiconductor region (or P-type metal-oxide semiconductor region). 4. Define the P-type metal-oxide semiconductor region (or N-type metal-oxide semiconductor region) where high-concentration ion doping is performed. 5. Define the P-type metal-oxide-semiconductor region (or P-type metal-oxide-semiconductor region) where high-concentration ion doping is performed. Each lithography step must include procedures such as Dehydration Bake, Priming, Photoresist, Soft Bake, Exposure, Development, Hard Bake, and Photoresist . As mentioned above, the traditional technique requires five lithographic steps to complete the process of complementary metal-oxide-semiconductor crystals. The cost is quite high and takes a lot of time, which seriously affects the production of products. 2-* ί -------! — -----I ..... .. ^ τ (Please read the precautions on the back before filling in the page) This paper size applies Chinese national standards ( CNS) Α4 wash (2! 0 × 297 mm) 415040 B7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention () Especially when the semiconductor process enters the sub-micron or even deep sub-micron process, different lithography steps Misalignment will be more difficult to overcome. Because of the inherent limitations of machine precision, the best way to solve the alignment problem is to minimize the lithography step. Brief description The main purpose of this month is to provide a method for forming complementary metal-oxide-semiconductor half field effect transistors in integrated circuits. Another object of the present invention is to provide a method for manufacturing a complementary metal-oxide-semiconductor field-effect transistor with low manufacturing cost and high yield, which requires only two lithographic processes. The present invention achieves the above-mentioned object by the following process: First, a P-well region, an N-well region, and a field oxide layer are formed on a silicon semiconductor substrate. After that, a gate oxide layer and a first silicon film are successively formed on the entire surface of the semiconductor substrate, and a photoresist is applied. The first silicon thin film and the gate oxide layer are etched using lithography and etching technology, and after the gate β is formed in the NMOS region, the NMOS region is doped with low-concentration ions by ion implantation technology to form the NMOS region. Lightly doped drain. After removing the photoresist, sidewalls are formed on both sides of the gate of the NMOS region. Then, using the ion implantation technique, high concentration ion doping is performed on the NMOS region to form a drain / source of the NMOS region. After forming a hard shield 'on the entire surface of the semiconductor substrate, a photoresist is applied. The lithography and etching techniques are used again to etch the hard shield of the PMOS region and the first silicon film to form a gate 'in the PMOS region, while retaining the hard shield of the NMOS region. Then, using the ion implantation technique, low-concentration ion doping is performed on the PMOS region to form a lightly doped drain electrode of the PMOS region. Copy 3 papers to the Chinese National Standard (CNS) A4 size (210 '乂 297 mm) (please read the precautions on the back before filling this page).

1T 415040 A 7 B7 V. Description of the Invention (After the photoresist is removed, sidewalls are formed on both sides of the gate of the PMOS region. Then, the ion implantation technique is used to dope the PMOS region with a high concentration of ions to form a PMOS region. The method of forming a complementary metal-oxide-semiconductor half-field-effect transistor in an integrated circuit according to the present invention is completed in a single step. Schematic illustration FIG. 1 shows the formation of a gate oxide layer and a first sand film in the present invention. Figure 2 is a schematic cross-sectional view of the manufacturing process of the first photoresist. "Figure 2 is a schematic cross-sectional view of the process of forming a gate and a lightly doped drain in the N-type metal-oxide-semiconductor field-effect transistor region. A schematic cross-sectional view of a process for forming a sidewall and a drain / source in an N-type metal-oxide-semiconductor field-effect transistor region. Figure 4 is a schematic cross-sectional view of a process for forming a hard shield and a second photoresist in the present invention. In the figure, a schematic cross-sectional view of the process of forming a gate electrode and a lightly doped drain electrode in a P-type metal-oxide-semiconductor half-field-effect transistor region is shown in FIG. 6. -^^ 1 In.:---. I-I--ΐ- j— < 1- _ {Please read the precautions on the back before filling this page)% Schematic diagram of the cross-section of Feizi and Si / Source process diagrams "Figure No. Description: 10-Si semiconductor substrate 20- 30- N well area 40-50 50-gate oxide layer 60- 60a- N-type metal-oxide-semiconductor half-effect transistor region gate 70-first photoresist 80- N-type metal-oxide-semiconductor half-effect transistor region P well field oxide layer first silicon thin film This paper is in accordance with Chinese national standards ( CNS) A4 specification (2! 0X 297 mm) 415040 A7 B7 Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (4) 90-P type metal oxide half field effect transistor 110-N type metal oxide Low-concentration ion doping in the half field effect transistor region Lightly doped 120- N type metal oxide half field effect transistor region Lightly doped 130- N type metal oxide half field effect transistor gate side wall 140- N type metal oxide half field effect Transistor region high concentration ion doped 15 _ NM source / drain of MOS half field effect transistor 160- hard cover 170- second photoresist 1 80- P type MOS half field effect transistor gate 190 · N-type metal-oxide-semiconductor field-effect transistor region with low concentration of ions 200- N type metal-oxide-semiconductor field-effect transistor region The source / drain of a high-concentration ion-doped 230-N-type metal-oxide-semiconductor half-field-effect transistor region In the method of complementary metal-oxide-semiconductor half-field-effect transistor, the manufacturing process described in the following embodiment will first perform the process of N-type metal-oxide-semiconductor half-effect transistor region, and then the process of P-type metal-oxide-semiconductor half-effect transistor region. Those who are familiar with integrated circuit technology can easily think that as long as the N-type metal-oxide-semiconductor field-effect transistor region and the P-type metal-oxide-semiconductor field-effect transistor region described in this embodiment are reversed, the method disclosed in the present invention can also be used. It is completely suitable for the process of firstly performing the P-type metal-oxide-semiconductor half-field-effect transistor region, and then the process of performing the N-type metal-oxide-semiconductor half-field-effect transistor region. Please refer to Figure 1. First, using ion implantation technology and high-temperature diffusion drive technology, 5 P-type silicon semiconductor substrates 10 in the lattice direction (100) are formed. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 0 乂 297mm). ^ 7 I In · m —n. * T < Please read the notes on the back before filling out this page) Printed by the Central Bureau of Standards of the Ministry of Economic Affairs and Industry and Consumer Cooperatives 415040__b7__ 5. Description of the invention (f) P well area 20 (P-well) and N-well 30 (N-well). A field oxide layer 40 is formed on the surface of the silicon semiconductor substrate 10 between the P-well region 20 and the N-well region 30. Thereafter, a gate oxide 50 and a first silicon film 60 are successively formed on the entire surface of the semiconductor substrate, and a first photoresist 70 is applied. The field oxide layer is usually formed by thermally oxidizing the silicon semiconductor wafer. Its thickness is between 3,500 angstroms and 9,000 angstroms, and is used for isolating metal-oxygen half field effect transistors. The gate oxide layer is formed by a thermal oxidation method, and the first sand film is usually a double-crystal silicon / sanded metal double-layer structure. Referring to FIG. 2, the first silicon thin film and the gate oxide layer are etched by using lithography and etching techniques to form a gate 60 a in an N-type metal-oxide-semiconductor field-effect transistor (NM0S) region 80, and a P-type metal-oxygen half-field The first silicon thin film of the PMOS region 90 is retained. Then, using the ion implantation technology, low-concentration ion doping 110 is performed on the NMOS region 80 to form a lightly doped drain (LDDD) 120 of the NMOS region. It is performed with P31 ions, its ion energy is between 20KeV and 50KeV, and its doping concentration is between 1E13 ions / cm 2 to 1E14 ions / cm 2. Referring to FIG. 3, after removing the photoresist, a side wall spacer (Sidewall SpaCer) 130 is formed on both sides of the gate 60a in the NMOS region. Then, using the ion implantation technique, the NMOS region 80 is doped with high concentration ions 140 to form the drain / source 150 of the NMOS region. The sidewalls 130 are formed by depositing a layer of silicon oxide and then performing an etch-back step on the silicon oxide. The silicon oxide is formed by using low pressure chemical vapor deposition (LPCVD) with TE0S as the reaction gas. 6 The paper size is applicable to China National Standard (CNS) A4 specification (210X 297 mm) (Please read the note on the back first) Please fill in this page for further information) Printed by the Central Consumers Bureau of the Ministry of Online Economics and Labor and Consumer Cooperatives 415040 5. Description of the invention (?) The silicon oxide layer formed; it can also be a plasma enhanced chemical vapor deposition (PECVD) A layer of silicon oxide formed. The high-concentration ion doping is performed using As75 ions, whose ion energy is between 40 KeV and 60 KeV, and its doping concentration is between 1E15 ions / cm 2 to 5E15 ions / cm 2. Please refer to FIG. 4, a layer of a hard mask 160 is formed on the entire surface of the semiconductor substrate, and then a second photoresist is coated. The hard shield is formed by a chemical vapor deposition method, and a composition material thereof may be silicon nitride (Nitride), oxide cut (Oxide), or oxynitride (Oxynitride). The function of the hard shield is to serve as a protective layer to protect all the elements in the NMOS region from being affected by the subsequent doping of low-concentration ions and high-concentration ions in the PMOS region and destroying its original doping concentration. Therefore, the thickness of the hard shield must be adjusted according to the energy of subsequent low-concentration ion doping and high-concentration ion doping in the PMOS region. Generally, the thickness is between 150 and 1500 angstroms. Please refer to FIG. 5, the lithography and etching techniques are used to etch the hard cover 160 and the first silicon film 60 of the PMOS region 90 again to form a gate 180 in the P-type metal-oxide-semiconductor field-effect transistor (PM0S) region 80, and The hard shield 160 of the N-type metal-oxide-semiconductor field-effect transistor (NMOS) region 90 is retained. Then, by using ion implantation technology, low-concentration ion doping 190 is performed on the PMOS region to form a lightly doped drain (LDD) 200 of the PMOS region. The low-concentration ion doping is performed with boron B11 ions, whose ion energy is between 15 KeV and 30 KeV, and its doping concentration is between 1E13 ions / cm 2 to 1E14 ions / cm 2. _7_ '^ The paper size is applicable to China National Standard Car (CNS) A4 specification (210X 297 mm) (Please read the precautions on the back before filling in the page)

415040 Printed by the Central Government Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative A7 B7 V. Description of the invention (7) Please refer to Figure 6. After removing the photoresist, side walls 210 are formed on both sides of the gate 180 in the PMOS area. Then, the ion implantation technology is used to perform high-concentration ion doping 220 on the PMOS region to form a drain / source 230 of the PMOS region. The method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in an integrated circuit according to the present invention is completed. The sidewall 210 is formed by depositing a layer of silicon oxide and then performing an etch-back step. The silicon oxide is a silicon oxide layer formed by using a low pressure chemical vapor deposition method (LPCVD) and TEOS as a reaction gas; it may also be a silicon oxide layer formed by a plasma enhanced chemical vapor deposition method (PECVD). . The high-concentration ion doping is performed with boron difluoride 8 ions, and its ion energy is between 60 KeV and 80 KeV, and its doping concentration is between 1E15 ions / cm 2 to 5E15 ions / cm 2. At this time, because there is a layer of hard shield 160 above the gate 180, the width of the side wall 210 formed is relatively large, and the lightly doped drain of the formed transistor is therefore wider, which can further reduce the formed electricity. The hot electron effect of the crystal improves the quality and reliability of the product. The above is a description of the present invention with the best embodiment, rather than limiting the present invention, and those who are familiar with the semiconductor technology will understand that making slight changes and adjustments appropriately will still not lose the essence of the present invention. Without departing from the spirit and scope of the invention. -1!---Ί ----—,! I— — I .....- I 、 1T I (Please read the precautions on the reverse side before filling out this page) 8 This paper is applicable to the countries in Central China Standard (CNS) A4 specification (210X297 mm)

Claims (1)

415040 A8B8C8D8 irr'vi. · F year ΛΎ- f VI. Application for Patent Range Amendment No. 0861-1746 (Application for Patent Range Amendment) > ί 1. In an integrated circuit A method for forming a complementary metal-oxide-semiconductor field-effect transistor. The manufacturing process includes the following steps: u a. Forming a P-well region, an N-well region, and a field oxide layer on the substrate; b. Forming a gate oxide layer on the entire substrate surface And the first silicon film; c. Forming a gate electrode in the N-type metal-oxide-semiconductor field-effect transistor region; d. Forming a lightly doped drain electrode in the N-type metal-oxide-semiconductor field-effect transistor region; e. Sidewalls are formed on both sides of the gate of the transistor region; f. Forms the source / drain of the N-type metal-oxide-semiconductor field-effect transistor region; g. Forms a hard shield on the entire surface of the semiconductor substrate; h. P-type metal-oxide The gate is formed in the half field effect transistor region; i. A lightly doped drain is formed in the P-type metal oxide half field effect transistor region; j. Sidewalls are formed on both sides of the gate of the P type metal oxide half field effect transistor region; k. Forms the source / drain of a P-type metal-oxide-semiconductor half field effect transistor region. 2. According to the method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in the integrated circuit described in item 1 of the scope of the patent application, the formation of the gate electrode in the N-type metal-oxide-semiconductor half-field effect transistor region uses lithography and etching The technology is formed by etching the first silicon film and the gate oxide layer. 3. According to the method for forming a complementary metal-oxide-semiconductor field-effect transistor in the integrated circuit described in item 1 of the scope of the patent application, the lightly doped drain in the N-type metal-oxide-semiconductor field-effect transistor region is formed by ions. The implantation technology is formed by doping the N-type metal-oxygen half field effect transistor region with low concentration ions. This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) (please read the notes on the back, and then fill out this page) Order ——.-- I——line 丨 Ministry of Economics Intellectual Property Printed by the Bureau ’s Consumer Cooperatives 415040 A8B8C8D8 irr'vi. · F year ΛΎ- f VI. Application for Patent Scope Case No. 0866-1167 4666 (Amended Patent Application Scope) > ί 1 A method for forming a complementary metal-oxide-semiconductor field-effect transistor in an integrated circuit, the process of which includes the following steps: u a. Forming a P-well region, an N-well region, and a field oxide layer on a substrate; b. The entire substrate A gate oxide layer and a first silicon film are successively formed on the surface; c. A gate electrode is formed in the N-type metal-oxide-semiconductor field-effect transistor region; d. A lightly doped drain electrode is formed in the N-type metal-oxide-semiconductor field-effect transistor region; e. N-type metal-oxide-semiconductor half-effect transistor regions form sidewalls on both sides of the gate; f. Tong-source N-type metal-oxide-semiconductor half-effect transistor region source / drain electrodes; g. Form a layer of hard shield on the entire semiconductor substrate surface; h Forming gates in the P-type metal-oxide half field-effect transistor region; i. Forming P-type metal-oxide Light FET doped drain region;. J sidewall spacers are formed on both sides of the P-type electrode metal oxide semiconductor field effect transistor gate regions;. K P type forming a source metal oxide semiconductor field effect transistor region / drain. 2. According to the method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in the integrated circuit described in item 1 of the scope of the patent application, the formation of the gate electrode in the N-type metal-oxide-semiconductor half-field effect transistor region uses lithography and etching The technology is formed by etching the first silicon film and the gate oxide layer. 3. According to the method for forming a complementary metal-oxide-semiconductor field-effect transistor in the integrated circuit described in item 1 of the scope of the patent application, the lightly doped drain in the N-type metal-oxide-semiconductor field-effect transistor region is formed by ions. The implantation technology is formed by doping the N-type metal-oxygen half field effect transistor region with low concentration ions. This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) (please read the notes on the back, and then fill out this page) Order ——.-- I——line 丨 Ministry of Economics Intellectual Property Printed by the Bureau ’s Consumer Cooperatives Printed by the Ministry of Economic Affairs ’Intellectual Property Bureau ’s Consumer Cooperatives’ printed 415040 | __ D8 VI. Patent Application Scope 4. The complementary metal-oxide-semiconductor half-effect transistor is formed in the integrated circuit described in item 3 of the patent application scope In the method, the low-concentration ion doping is performed with P31 ions. 5. According to the method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in the integrated circuit described in item 3 of the patent application scope, the ion energy doped by the low-concentration ion is between 20 KeV and 50 KeV. 6. The method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in the integrated circuit described in item 3 of the scope of patent application, wherein the doping concentration of the low-concentration ion doping is between 1E13 ions / cm 2 to 1E14 ions / Between square centimeters. 7. According to the method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in the integrated circuit described in item 1 of the scope of the patent application, the formation of sidewalls on both sides of the gate of the N-type metal-oxide-semiconductor half-effect transistor region is to first A layer of silicon oxide is deposited and then etched back. 8. The method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in an integrated circuit as described in item 7 of the scope of patent application, wherein the silicon oxide is an oxide formed by using a low-pressure chemical vapor deposition method with TEOS as a reaction gas. Silicon layer. 9. The method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in an integrated circuit as described in item 7 of the scope of the patent application, wherein the silicon oxide is a silicon oxide layer formed by a plasma enhanced chemical vapor deposition method. 10. According to the method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in the integrated circuit described in item 1 of the scope of the patent application, the source / drain of the N-type metal-oxide-semiconductor half-field effect transistor region is formed by an ion cloth. It is formed by doping the N-type metal-oxygen half field-effect transistor region with high concentration ions. _____10_ This paper size is applicable to Zhongguanjia Standard (CNS) A4 specification (210 X 297 Gongchu) ~~ '1 !!! ^ in — —! — ^ -N —.--- t (Please read the back first (Please note this page and fill in this page again) A8 B8 C8 415040 VI. Application for Patent Scope 11. The method of forming complementary metal-oxide-semiconductor half-field-effect transistor in integrated circuit as described in item 10 of the scope of patent application, where The concentration ion doping was performed with As75 ions. 12. According to the method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in an integrated circuit as described in item 10 of the scope of patent application, the doping concentration of the high-concentration ion doping is between 1E15 ions / cm 2 to 5E15 ions. / Cm2. 13. The method for forming a complementary metal-oxide-semiconductor half field-effect transistor in a integrated circuit as described in item 10 of the scope of the patent application, wherein the ion energy doped by the high-concentration ion is between 40KeV and 60KeV. 14. The method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in the integrated circuit described in item 1 of the patent application scope, wherein the hard shield is a silicon nitride layer. 15. The method for forming a complementary metal-oxide-semiconductor half field-effect transistor in the integrated circuit described in item 1 of the patent application scope, wherein the hard shield is a silicon oxide layer. 16. The method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in the integrated circuit described in item 1 of the patent application scope, wherein the hard shield is a silicon oxynitride layer. Π. According to the method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in the integrated circuit described in item 1 of the scope of the patent application, the thickness of the hard shield must correspond to the low-concentration ion doping in the subsequent P-type metal-oxide half-effect transistor region. Doped and high-concentration ion doped energy. 18. According to the method for forming a complementary metal-oxide-semiconductor half field-effect transistor in the integrated circuit described in item 1 of the scope of patent application, the thickness of the hard shield is between 150 Angstroms and 1500 Angstroms. 19. According to the method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in the integrated circuit described in item 1 of the scope of the patent application, the P-type metal-oxide-semiconductor half-field-effect transistor 1 !!! --- _ IIII Order II 1 — —-< Please read the notes on the back before filling out this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Employee Cooperatives This paper is printed in accordance with China National Standard (CNS) A4 (210x297 mm) A8 B8 C8 D8 415040 6. The gate is formed in the patent application area, which is formed by etching the hard cover of the P-type metal-oxide-semiconductor field-effect transistor region and the first silicon thin film by using lithography and etching technology. 20. According to the method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in the integrated circuit described in item 1 of the scope of the patent application, the lightly doped drain electrode forming the P-type metal-oxide-semiconductor half-field effect transistor region is an ion The implantation technology is formed by doping low-concentration ions in the P-type metal-oxygen half field effect transistor region. 21. According to the method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in the integrated circuit described in item 20 of the patent application scope, the low-concentration ion doping is performed with boron ions. 22. According to the method for forming a complementary metal-oxide-semiconductor field-effect transistor in the integrated circuit described in item 20 of the scope of the patent application, the ion energy doped by the low-concentration ion is between 15 KeV and 30 KeV. 23. According to the method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in an integrated circuit described in item 20 of the scope of patent application, the doping concentration of the low-concentration ion doping is between 1E13 ions / cm 2 to 1E14 ions / Between square centimeters. 24. According to the method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in the integrated circuit described in item 1 of the scope of the patent application, the formation of sidewalls on both sides of the gate of the P-type metal-oxide-semiconductor half-field effect transistor region is to first A layer of silicon oxide is deposited and then etched back. 25. The method for forming a complementary metal-oxygen half field-effect transistor in an integrated circuit as described in item 24 of the scope of patent application, wherein the silicon oxide is an oxide formed by using a low-pressure chemical vapor deposition method with TEOS as a reactive gas. Silicon layer. This paper size applies to China National Standard (CNS) A4 specification (210 x 297 mm) ----------------- (Please read the precautions on the back before filling this page) Statement Γ Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 415040 § ___ VI. Application for a patent 26. The method for forming a complementary metal-oxide-semiconductor half-effect transistor in the integrated circuit described in item 24 of the patent application, Silicon oxide is a silicon oxide layer formed by plasma enhanced chemical vapor deposition. 27. According to the method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in the integrated circuit described in item 1 of the scope of the patent application, the source / drain of the P-type metal-oxide-semiconductor half-field effect transistor region is formed by an ion cloth. It is formed by implanting high-concentration ion doping in the P-type metal-oxygen half field effect transistor region. 28. According to the method for forming a complementary metal-oxide-semiconductor half field-effect transistor in an integrated circuit as described in item 27 of the scope of the patent application, the high-concentration ion doping is performed with boron difluoride ions. 29. The method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in an integrated circuit as described in item 27 of the scope of patent application, wherein the doping concentration of the high-concentration ion doping is between 1E15 ions / cm 2 to 5E15 ions / Between square centimeters ° 30. According to the method for forming a complementary metal-oxide-semiconductor field-effect transistor in the integrated circuit described in item 27 of the scope of the patent application, the ion energy doped by the high-concentration ion is between 60KeV and 80KeV . 31. —A method for forming a complementary metal-oxide-semiconductor field-effect transistor in an integrated circuit 'The process includes the following steps: a. Forming a P-well region, an N-well region, and a field oxide layer on a substrate; b. On the entire substrate surface A gate oxide layer and a first silicon film are successively formed; c. A gate electrode is formed in the P-type metal-oxide-semiconductor field-effect transistor region; d. A lightly doped drain electrode is formed in the P-type metal-oxide-semiconductor field-effect transistor region; e. Side walls are formed on both sides of the gate of the metal oxide semiconductor field-effect transistor region; f. The source / drain of the P-type metal oxide semiconductor field-effect transistor region is formed; ___________ 13 __-____ This paper is in accordance with China National Standard (CNS) A4 specification ( 210 X 297 mm) ------- I ----- k -------- Order ------ I--line (Please read the precautions on the back before filling in this Page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed 415040 as Do C8 ----- --- 2! ____ VI. Application for patents g. On the surface of the entire semiconductor substrate Form a layer of hard shield; h. Form the gate in the N-type metal-oxide-semiconductor field-effect transistor region; 1. Form the N-type metal-oxide-semiconductor field-effect transistor region Lightly doped drain; j. Forming sidewalls on both sides of the gate of the N-type MOSFET; k. Forming the source / drain of the N-type MOSFET. 32. According to the method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in the integrated circuit described in item 31 of the scope of the patent application, the formation of the gate electrode in the P-type metal-oxide-semiconductor half-field effect transistor region uses lithography and etching The technology is formed by etching the first silicon film and the gate oxide layer. 33. According to the method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in the integrated circuit described in item 31 of the scope of the patent application, the lightly doped drain in the P-type metal-oxide-semiconductor half-field effect transistor region is formed by ions. The implantation technology is formed by doping the N-type metal-oxygen half field effect transistor region with low concentration ions. 34. According to the method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in an integrated circuit described in item 33 of the scope of the patent application, the low-concentration ion doping is performed with boron ions. 35. The method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in a integrated circuit as described in item 33 of the scope of the patent application, wherein the ion energy doped by the low-concentration ion is between 15 KeV and 30 KeV. 36. The method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in an integrated circuit described in item 33 of the scope of patent application, wherein the doping concentration of the low-concentration ion doping is between 1E13 and f / cm² to 5E13 / Cm2. 37. According to the method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in the integrated circuit described in item 31 of the scope of the patent application, the P-type metal-oxide-semiconductor half-field-effect transistor __14 I -------- ---- L ^ i— —--— Order --------- line-(Please read the notes on the back before filling out this page) The paper size applies to China National Standard (CNS) A4 specifications ( (210 X 297 mm) A8B8C8D8 415040 6. The sidewalls on both sides of the electrode in the patent application area are formed by depositing a layer of oxide sand and then performing an etch-back step. 38. According to the method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in an integrated circuit as described in item 37 of the scope of the patent application, the silicon oxide is an oxide formed by using a low-pressure chemical vapor deposition method with TEOS as a reactive gas. Silicon layer. 39. According to the method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in an integrated circuit as described in item 37 of the scope of patent application, the silicon oxide is a silicon oxide layer formed by a plasma enhanced chemical vapor deposition method. 40. According to the method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in the integrated circuit described in item 31 of the scope of the patent application, the source / drain of the P-type metal-oxide-semiconductor half-field effect transistor region is an ionic cloth It is formed by implanting high-concentration ion doping in the P-type metal-oxygen half field-effect transistor region. 41. According to the method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in an integrated circuit described in item 40 of the scope of the patent application, the high-concentration ion doping is performed with boron difluoride ions. 42. The method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in an integrated circuit as described in item 40 of the scope of patent application, wherein the doping concentration of the high-concentration ion doping is between 1E15 ions / cm 2 to 5E15 ions / Between square centimeters. 43. According to the method for forming a complementary metal-oxide-semiconductor field-effect transistor in an integrated circuit described in item 40 of the scope of the patent application, the ion energy doped by the high-concentration ion is between 60 KeV and 80 KeV. 44. According to the method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in the integrated circuit described in item 31 of the scope of the patent application, the hard shield is a silicon nitride layer. This paper size applies to China National Standard (CNS) A4 specifications (210 x 4 7 male f) -------------- -------- order --------- --Line- (Please read the notes on the back before filling out this page) Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employees' Cooperatives of the Ministry of Economic Affairs ’Intellectual Property Bureau printed 415040 6. Scope of patent application 45. If you apply for a patent scope In the method for forming a complementary metal-oxide-semiconductor field-effect transistor in the integrated circuit according to item 31, the hard shield is a silicon oxide layer. 46. The method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in the integrated circuit described in item 31 of the scope of patent application, wherein the hard shield is a silicon oxynitride layer. 47. According to the method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in the integrated circuit described in item 31 of the scope of the patent application, the thickness of the hard shield must correspond to the low-concentration ion doping in the subsequent P-type metal-oxide half-effect transistor region. Doped and high-concentration ion doped energy. 48. According to the method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in the integrated circuit described in item 31 of the scope of patent application, the thickness of the hard shield is between 150 Angstroms and 1500 Angstroms. 49. According to the method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in the integrated circuit described in item 31 of the scope of application for patent, the formation of a gate electrode in the N-type metal-oxide-semiconductor half-field effect transistor region uses lithography and etching The technology is formed by etching the hard cover of the N-type metal-oxide-semiconductor half field effect transistor region and the first silicon film. 50. According to the method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in the integrated circuit described in item 31 of the scope of the patent application, the lightly doped drain electrode for forming the N-type metal-oxide-semiconductor half-field effect transistor region is an ion The implantation technology is formed by doping the N-type metal-oxygen half field effect transistor region with low concentration ions. 51. The method for forming a complementary metal-oxide-semiconductor half field-effect transistor in an integrated circuit as described in item 50 of the scope of the patent application, wherein the low-concentration ion doping is performed using P31 ions. This paper size applies to China National Standard (CNS) A4 specifications (2〗 0 X 297 Gongchu) -------------- ^ -------- Order ----- !! !! Line (please read the note on the back before filling this page) A8 B8 C8 D8 415040 VI. Application for patent scope 52. Form a complementary metal-oxide-semiconductor half field effect transistor in the integrated circuit described in item 50 of the patent scope Method, the ion energy of the low-concentration ion doping is between 20 KeV and 50 KeV. 53. According to the method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in an integrated circuit described in item 50 of the scope of patent application, the doping concentration of the low-concentration ion doping is between 1E13 ions / cm 2 to 5E13 ions / Between square centimeters. 54. According to the method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in the integrated circuit described in item 31 of the scope of application for a patent, the formation of sidewalls on both sides of the gate of the N-type metal-oxide-semiconductor half-field effect transistor region is to first A layer of silicon oxide is deposited and then etched back. 55. The method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in an integrated circuit described in item 54 of the scope of patent application, wherein the silicon oxide is an oxide formed by using a low-pressure chemical vapor deposition method with TEOS as a reactive gas. Silicon layer. 56. According to the method for forming a complementary metal-oxide-semiconductor field-effect transistor in an integrated circuit as described in item 54 of the scope of the patent application, the silicon oxide is a silicon oxide layer formed by a plasma enhanced chemical vapor deposition method. 57. According to the method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in the integrated circuit described in item 31 of the scope of application for a patent, the source / drain of the N-type metal-oxide-semiconductor half-field effect transistor region is formed by an ion cloth. It is formed by doping the N-type metal-oxygen half field-effect transistor region with high concentration ions. 58. The method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in an integrated circuit as described in item 57 of the scope of patent application, wherein the high-concentration ion doping is performed with As75 ions. ———— I ——-———— .. Pu Yi [1 Ϊ i III _ιδι'111 — I 111 f I (Please read the precautions on the back before filling this page) Printed by a member of the Intellectual Property Bureau of the Ministry of Economic Affairs and a Consumer Cooperative The paper size of the paper is in accordance with the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 00800 59 ABCD 415040 6. Scope of patent application 59. Complementary metal oxide is formed in the integrated circuit described in item 57 of the scope of patent application In the half field effect transistor method, the doping concentration of the high-concentration ion doping is between 1E15 ions / cm 2 and 5E15 ions / cm 2. 60. According to the method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in an integrated circuit described in item 57 of the scope of the patent application, the ion energy doped by the high-concentration ion is between 20 KeV and 60 KeV. ------------- h -------- Order --------- Line II (Please read the notes on the back before filling out this page) Ministry of Economy Wisdom The paper size printed by the Property Cooperative Consumer Cooperative is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm)