415040 A? B7 經濟部中央標浪馬員工消費合作社印策 五、發明説明(/) 詳細說明: 技術領域 本發明是關於在積體電路中形成互補式金氧半場效電晶 體的方法β 發明背焉 互補式金氧半電晶體(CMOS)是積體電路中最基本*最 重要的元件。傳統在積體電路中形成互補式金氧半電晶體的 製程,通常需要如下所列五次微影步驟: 1. 定義P型金氧半電晶體區和N型金氧半電晶體區的閘 極。 2. 定義P型金氧半電晶體區(或N型金氧半電晶體區)中 進行低濃度離子摻雜的區域。 3. 定義N型金氧半電晶體區(或P型金氧半電晶體區)中 進行低濃度離子摻雜的區域。 4. 定義P型金氧半電晶體區(或N型金氧半電晶體區)中 進行高濃度離子摻雜的區域。 5. 定義P型金氧半電晶體區(或P型金氧半電晶體區)中 進行高濃度離子摻雜的區域。 每一道微影步驟都必須包含去水烘烤(Dehydration Bake)、塗底(Priming)、上光阻、軟烤(Soft Bake)、曝 光、顯影、硬烤(Hard Bake)和去光阻等程序。如上所述,傳 統技藝需要五道微影步驟才能完成互補式金氧半電晶體的製 程,其成本相當高且耗費許多時間,嚴重影響產品的產量。 2 -* ί ------ - ! — --- - - I..... ..^τ (請先閱讀背面之注意事項再填寫太頁) 本纸張尺度適用中國國家標準(CNS ) Α4洗格(2!0Χ 297公釐) 415040 B7 經濟部中央標準局員工消費合作社印製 五、發明説明() 尤其當半導體的製程進入次微米甚至深次微米製程以 後,不同微影步驟之間對準不良(Misalignment)的問題將更 不易克服。因爲機台精密程度的先天限制,要解決對準問題 最好的方法便是盡量減少微影步驟。 簡要說明 本發ΐ月之主要目的是提供一種在積體電路中形成互補式 金氧半場效電晶體的方法。 本發明之另一個目的是提供一種具有低製造成本、高產 量,只需兩道微影製程之互補式金氧半場效電晶體的製造方 法。 本發明是以如下製程而達成上述的目的:首先,在矽半 導體基板上形成Ρ井區、Ν井區和場氧化層。之後在整個半 導體基板表面陸續形成閘氧化層和第一矽薄膜,並塗佈上光 阻。利用微影及蝕刻技術對所述第一矽薄膜和閘氧化層進行 蝕刻,在NMOS區形成閘極β之後以離子佈植技術,對所述 NMOS區進行低濃度離子摻雜,以形成NMOS區的淡摻雜汲 極。將光阻去除後,在NMOS區閘極兩側形成側壁子。接著 以離子佈植技術,對所述NMOS區進行高濃度離子摻雜’以 形成NMOS區的汲/源極。 在整個半導體基板表面形成一層硬式護罩’之後再塗佈 上光阻。再次利用微影及蝕刻技術對PMOS區的硬式護罩及 第一矽薄膜進行蝕刻,在PMOS區形成閘極’而NMOS區的 硬式護罩則與予保留。之後以離子佈植技術,對所述PMOS 區進行低濃度離子摻雜,以形成PMOS區的淡摻雜汲極。將 3 本紙張尺度適肉中國國家標準(CNS ) A4规格(210'乂297公釐) (請先閱讀背面之注意事項再填寫本頁) .丨裝-415040 A? B7 Printing policy of the Central Biaolangma Employee Consumer Cooperative of the Ministry of Economic Affairs 5. Description of the invention (/) Detailed description: TECHNICAL FIELD The present invention relates to a method for forming complementary metal-oxide-semiconductor field-effect transistors in integrated circuits.焉 Complementary metal-oxide-semiconductor (CMOS) is the most basic * most important component in integrated circuits. The traditional process of forming complementary metal-oxide-semiconductor transistors in integrated circuits usually requires the following five lithography steps: 1. Define the gates of the P-type metal-oxide-semiconductor region and the N-type metal-oxide-semiconductor region. pole. 2. Define the P-type metal-oxide semiconductor region (or N-type metal-oxide semiconductor region) where low-concentration ion doping is performed. 3. Define the region where low-concentration ion doping is performed in the N-type metal-oxide semiconductor region (or P-type metal-oxide semiconductor region). 4. Define the P-type metal-oxide semiconductor region (or N-type metal-oxide semiconductor region) where high-concentration ion doping is performed. 5. Define the P-type metal-oxide-semiconductor region (or P-type metal-oxide-semiconductor region) where high-concentration ion doping is performed. Each lithography step must include procedures such as Dehydration Bake, Priming, Photoresist, Soft Bake, Exposure, Development, Hard Bake, and Photoresist . As mentioned above, the traditional technique requires five lithographic steps to complete the process of complementary metal-oxide-semiconductor crystals. The cost is quite high and takes a lot of time, which seriously affects the production of products. 2-* ί -------! — -----I ..... .. ^ τ (Please read the precautions on the back before filling in the page) This paper size applies Chinese national standards ( CNS) Α4 wash (2! 0 × 297 mm) 415040 B7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention () Especially when the semiconductor process enters the sub-micron or even deep sub-micron process, different lithography steps Misalignment will be more difficult to overcome. Because of the inherent limitations of machine precision, the best way to solve the alignment problem is to minimize the lithography step. Brief description The main purpose of this month is to provide a method for forming complementary metal-oxide-semiconductor half field effect transistors in integrated circuits. Another object of the present invention is to provide a method for manufacturing a complementary metal-oxide-semiconductor field-effect transistor with low manufacturing cost and high yield, which requires only two lithographic processes. The present invention achieves the above-mentioned object by the following process: First, a P-well region, an N-well region, and a field oxide layer are formed on a silicon semiconductor substrate. After that, a gate oxide layer and a first silicon film are successively formed on the entire surface of the semiconductor substrate, and a photoresist is applied. The first silicon thin film and the gate oxide layer are etched using lithography and etching technology, and after the gate β is formed in the NMOS region, the NMOS region is doped with low-concentration ions by ion implantation technology to form the NMOS region. Lightly doped drain. After removing the photoresist, sidewalls are formed on both sides of the gate of the NMOS region. Then, using the ion implantation technique, high concentration ion doping is performed on the NMOS region to form a drain / source of the NMOS region. After forming a hard shield 'on the entire surface of the semiconductor substrate, a photoresist is applied. The lithography and etching techniques are used again to etch the hard shield of the PMOS region and the first silicon film to form a gate 'in the PMOS region, while retaining the hard shield of the NMOS region. Then, using the ion implantation technique, low-concentration ion doping is performed on the PMOS region to form a lightly doped drain electrode of the PMOS region. Copy 3 papers to the Chinese National Standard (CNS) A4 size (210 '乂 297 mm) (please read the precautions on the back before filling this page).
,1T 415040 A 7 B7 五、發明説明( 光阻去除後,在PMOS區閘極兩側形成側壁子。接著以離子 佈植技術,對所述PMOS區進行高濃度離子摻雜,以形成 PMOS區的汲/源極。本發明所述在積體電路中形成互補式金 氧半場效電晶體的方法於焉完成。 圖式說明 圖一是本發明中,形成閘氧化層、第一砂薄膜,並塗佈 上第一光阻的製程剖面示意圖》 圖二是本發明中,在N型金氧半場效電晶體區形成閘極 和淡摻雜汲極的製程剖面示意圖9 圖三是本發明中,在N型金氧半場效電晶體區形成側壁 子和汲/源極的製程剖面示意圖。 圖四是本發明中,形成硬式護罩及第二光阻的製程剖面 示意圖。 圖五是本發明中,在P型金氧半場效電晶體區形成閘極 和淡摻雜汲極的製程剖面示意圖。 圖六是本發明中,在P型金氧半場效電晶體區形成側壁 ~H - r II -- ^^1 In . :- - - . I - I - - ΐ- j—< 1-_ {請先閱讀背面之注意事項再填寫本頁) % 費 子和汲/源極的製程剖面示意圖》 圖號說明: 10-矽半導體基板 20- 30- N 井區 40- 50-閘氧化層 60- 60a- N型金氧半場效電晶體區閘極 70-第一光阻 80- N型金氧半場效電晶體區 P井區 場氧化層 第一矽薄膜 本紙張尺度適用中國國家標準(CNS ) A4規格(2!0X 297公釐) 415040 A7 B7 經濟部中央標準局貝工消费合作社印製 五、發明説明(4) 90- P型金氧半場效電晶體區 110- N型金氧半場效電晶體區低濃度離子摻雜 120- N型金氧半場效電晶體區的淡摻雜汲極 130- N型金氧半場效電晶體區閘極側壁子 140- N型金氧半場效電晶體區高濃度離子摻雜 15〇_ NM金氧半場效電晶體區的源/汲極 160-硬式護罩 170-第二光阻 1 80- P型金氧半場效電晶體區閘極 190· N型金氧半場效電晶體區低濃度離子慘雜 200- N型金氧半場效電晶體區的淡摻雜汲極 210- N型金氧半場效電晶體區閘極側壁子 220- N型金氧半場效電晶體區高濃度離子摻雜 230- N型金氧半場效電晶體區的源/汲極 本發明是有關在積體電路中形成互補式金氧半場效電晶 體的方法,以下實施例所描述的製程,將先進行N型金氧半 場效電晶體區的製程,後進行P型金氧半場效電晶體區的製 程。熟悉積體電路技藝之人士皆能輕易思及,只要將本實施 例所描述之N型金氧半場效電晶體區和P型金氧半場效電晶 體區對調,本發明所揭露之方法亦能完全適用於先進行P型 金氧半場效電晶體區的製程,後進行N型金氧半場效電晶體 區的製程。 現在請參考圖一。首先,利用離子佈植技術與高溫擴散 驅入技術,在晶格方向(100)之P型矽半導體基板10上形成 5 本紙張尺度適用中國國家標準(CNS ) A4規格(2丨0乂 297公^7 I In· m —n . *T <請先閲讀背面之注意事項再填寫本頁) 經涛部中央標隼局—工消費合作社印製 415040__b7__ 五、發明説明(f) P井區20 (P-well)和N井區30 (N-well)。接著在所述P井 區20與N井區30之間的矽半導體基板10表面形成場氧化層40 (Field Oxide)。之後在整個半導體基板表面陸續形成閛氧 化層(Gate Oxide)50和第一矽薄膜60,並塗佈上第一光阻 70 ° 所述場氧化層通常是熱氧化所述矽半導體晶圓而形成, 其厚度介於3500埃到9000埃之間,作爲隔離金氧半場效電晶 體之用。所述閘氧化層是利用熱氧化法所形成,所述第一砂 薄膜通常是複晶矽/砂化金屬雙層結構。 請參考圖二,利用微影及蝕刻技術對所述第一矽薄膜和 閘氧化層進行蝕刻,在N型金氧半場效電晶體(NM0S)區80 形成閘極60a,而P型金氧半場效電晶體(PM0S)區90的第一 矽薄膜則與予保留。之後以離子佈植技術,對所述NM0S區 80進行低濃度離子摻雜110,以形成NM0S區的淡摻雜汲極 (Light丨y Doped Drain; LDD)120 »其中所述低濃度離子摻雜係 以P31離子進行,其離子能量介於20KeV到50KeV之間,其 摻雜濃度介於1E13離子/平方公分到1E14離子/平方公分之 間。 請參考圖三,將光阻去除後,在NM0S區閘極60a兩側 形成側壁子(Sidewall SpaCer)130。接著以離子佈植技術,對 所述NM0S區80進行高濃度離子摻雜140,以形成NM0S區 的汲/源極150。形成所述側壁子130,是先沉積一層氧化 矽,再對該氧化矽進行回蝕刻步驟所形成。所述氧化矽是利 用低壓化學氣相沉積法(LPCVD),以TE0S爲反應氣體所形 6 本紙張尺度適用中國囷家標準(CNS ) A4規格(210X 297公釐) (請先閱讀背面之注意事項再填寫本頁) 線 經濟部中央螵拿局㈣工消費合作社印顰 415040 五、發明説明(么) 成的氧化矽層;也可以是利用電漿增強式化學氣相沉積法 (PECVD)所形成的氧化矽層。其中所述高濃度離子摻雜係利 用As75離子進行,其離子能量介於40KeV到60KeV之間,其 摻雜濃度介於1E15離子/平方公分到5E15離子/平方公分之 間。 請参考圖四,在整個半導體基板表面形成一層硬式護罩 (Hard Mask)160,之後再塗佈上第二光阻ΠΟ。所述硬式護 罩是利用化學氣相沉積法所形成,其組成材質可以爲氮化矽 (Nitride)、氧化砍(Oxide)或氮氧化砂(Oxynitride)。該硬式護 罩的功能是做爲保護層以保護NM0S區的所有元件,免於受 後續PM0S區的低濃度離子摻雜和高濃度離子摻雜的影響而 破壞其原有的摻雜濃度。因此該硬式護罩的厚度必須因應後 續PM0S區的低濃度離子摻雜和高濃度離子摻雜的能量而調 整,一般厚度介於150埃至1500埃之間。 請參考圖五,再次利用微影及蝕刻技術對PMOS區90的 硬式護罩160及第一矽薄膜60進行蝕刻,在Ρ型金氧半場效電 晶體(PM0S)區80形成閘極180,而Ν型金氧半場效電晶體 (NM0S)區90的硬式護罩160則與予保留。之後以離子佈植技 術,對所述PMOS區進行低濃度離子摻雜190,以形成PM0S 區的淡慘雜汲極(Lightly Doped Drain; LDD)200。所述低濃度 離子摻雜係以硼B11離子進行,其離子能量介於15KeV到 30KeV之間,其摻雜濃度介於1E13離子/平方公分到1E14離 子/平方公分之間。 _7_ ' ^紙張尺度適用中國國家標车(CNS ) A4規格(210X 297公釐) (請先閱讀背面之注意事項再填寫太頁)1T 415040 A 7 B7 V. Description of the Invention (After the photoresist is removed, sidewalls are formed on both sides of the gate of the PMOS region. Then, the ion implantation technique is used to dope the PMOS region with a high concentration of ions to form a PMOS region. The method of forming a complementary metal-oxide-semiconductor half-field-effect transistor in an integrated circuit according to the present invention is completed in a single step. Schematic illustration FIG. 1 shows the formation of a gate oxide layer and a first sand film in the present invention. Figure 2 is a schematic cross-sectional view of the manufacturing process of the first photoresist. "Figure 2 is a schematic cross-sectional view of the process of forming a gate and a lightly doped drain in the N-type metal-oxide-semiconductor field-effect transistor region. A schematic cross-sectional view of a process for forming a sidewall and a drain / source in an N-type metal-oxide-semiconductor field-effect transistor region. Figure 4 is a schematic cross-sectional view of a process for forming a hard shield and a second photoresist in the present invention. In the figure, a schematic cross-sectional view of the process of forming a gate electrode and a lightly doped drain electrode in a P-type metal-oxide-semiconductor half-field-effect transistor region is shown in FIG. 6. -^^ 1 In.:---. I-I--ΐ- j— < 1- _ {Please read the precautions on the back before filling this page)% Schematic diagram of the cross-section of Feizi and Si / Source process diagrams "Figure No. Description: 10-Si semiconductor substrate 20- 30- N well area 40-50 50-gate oxide layer 60- 60a- N-type metal-oxide-semiconductor half-effect transistor region gate 70-first photoresist 80- N-type metal-oxide-semiconductor half-effect transistor region P well field oxide layer first silicon thin film This paper is in accordance with Chinese national standards ( CNS) A4 specification (2! 0X 297 mm) 415040 A7 B7 Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (4) 90-P type metal oxide half field effect transistor 110-N type metal oxide Low-concentration ion doping in the half field effect transistor region Lightly doped 120- N type metal oxide half field effect transistor region Lightly doped 130- N type metal oxide half field effect transistor gate side wall 140- N type metal oxide half field effect Transistor region high concentration ion doped 15 _ NM source / drain of MOS half field effect transistor 160- hard cover 170- second photoresist 1 80- P type MOS half field effect transistor gate 190 · N-type metal-oxide-semiconductor field-effect transistor region with low concentration of ions 200- N type metal-oxide-semiconductor field-effect transistor region The source / drain of a high-concentration ion-doped 230-N-type metal-oxide-semiconductor half-field-effect transistor region In the method of complementary metal-oxide-semiconductor half-field-effect transistor, the manufacturing process described in the following embodiment will first perform the process of N-type metal-oxide-semiconductor half-effect transistor region, and then the process of P-type metal-oxide-semiconductor half-effect transistor region. Those who are familiar with integrated circuit technology can easily think that as long as the N-type metal-oxide-semiconductor field-effect transistor region and the P-type metal-oxide-semiconductor field-effect transistor region described in this embodiment are reversed, the method disclosed in the present invention can also be used. It is completely suitable for the process of firstly performing the P-type metal-oxide-semiconductor half-field-effect transistor region, and then the process of performing the N-type metal-oxide-semiconductor half-field-effect transistor region. Please refer to Figure 1. First, using ion implantation technology and high-temperature diffusion drive technology, 5 P-type silicon semiconductor substrates 10 in the lattice direction (100) are formed. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 0 乂 297mm). ^ 7 I In · m —n. * T < Please read the notes on the back before filling out this page) Printed by the Central Bureau of Standards of the Ministry of Economic Affairs and Industry and Consumer Cooperatives 415040__b7__ 5. Description of the invention (f) P well area 20 (P-well) and N-well 30 (N-well). A field oxide layer 40 is formed on the surface of the silicon semiconductor substrate 10 between the P-well region 20 and the N-well region 30. Thereafter, a gate oxide 50 and a first silicon film 60 are successively formed on the entire surface of the semiconductor substrate, and a first photoresist 70 is applied. The field oxide layer is usually formed by thermally oxidizing the silicon semiconductor wafer. Its thickness is between 3,500 angstroms and 9,000 angstroms, and is used for isolating metal-oxygen half field effect transistors. The gate oxide layer is formed by a thermal oxidation method, and the first sand film is usually a double-crystal silicon / sanded metal double-layer structure. Referring to FIG. 2, the first silicon thin film and the gate oxide layer are etched by using lithography and etching techniques to form a gate 60 a in an N-type metal-oxide-semiconductor field-effect transistor (NM0S) region 80, and a P-type metal-oxygen half-field The first silicon thin film of the PMOS region 90 is retained. Then, using the ion implantation technology, low-concentration ion doping 110 is performed on the NMOS region 80 to form a lightly doped drain (LDDD) 120 of the NMOS region. It is performed with P31 ions, its ion energy is between 20KeV and 50KeV, and its doping concentration is between 1E13 ions / cm 2 to 1E14 ions / cm 2. Referring to FIG. 3, after removing the photoresist, a side wall spacer (Sidewall SpaCer) 130 is formed on both sides of the gate 60a in the NMOS region. Then, using the ion implantation technique, the NMOS region 80 is doped with high concentration ions 140 to form the drain / source 150 of the NMOS region. The sidewalls 130 are formed by depositing a layer of silicon oxide and then performing an etch-back step on the silicon oxide. The silicon oxide is formed by using low pressure chemical vapor deposition (LPCVD) with TE0S as the reaction gas. 6 The paper size is applicable to China National Standard (CNS) A4 specification (210X 297 mm) (Please read the note on the back first) Please fill in this page for further information) Printed by the Central Consumers Bureau of the Ministry of Online Economics and Labor and Consumer Cooperatives 415040 5. Description of the invention (?) The silicon oxide layer formed; it can also be a plasma enhanced chemical vapor deposition (PECVD) A layer of silicon oxide formed. The high-concentration ion doping is performed using As75 ions, whose ion energy is between 40 KeV and 60 KeV, and its doping concentration is between 1E15 ions / cm 2 to 5E15 ions / cm 2. Please refer to FIG. 4, a layer of a hard mask 160 is formed on the entire surface of the semiconductor substrate, and then a second photoresist is coated. The hard shield is formed by a chemical vapor deposition method, and a composition material thereof may be silicon nitride (Nitride), oxide cut (Oxide), or oxynitride (Oxynitride). The function of the hard shield is to serve as a protective layer to protect all the elements in the NMOS region from being affected by the subsequent doping of low-concentration ions and high-concentration ions in the PMOS region and destroying its original doping concentration. Therefore, the thickness of the hard shield must be adjusted according to the energy of subsequent low-concentration ion doping and high-concentration ion doping in the PMOS region. Generally, the thickness is between 150 and 1500 angstroms. Please refer to FIG. 5, the lithography and etching techniques are used to etch the hard cover 160 and the first silicon film 60 of the PMOS region 90 again to form a gate 180 in the P-type metal-oxide-semiconductor field-effect transistor (PM0S) region 80, and The hard shield 160 of the N-type metal-oxide-semiconductor field-effect transistor (NMOS) region 90 is retained. Then, by using ion implantation technology, low-concentration ion doping 190 is performed on the PMOS region to form a lightly doped drain (LDD) 200 of the PMOS region. The low-concentration ion doping is performed with boron B11 ions, whose ion energy is between 15 KeV and 30 KeV, and its doping concentration is between 1E13 ions / cm 2 to 1E14 ions / cm 2. _7_ '^ The paper size is applicable to China National Standard Car (CNS) A4 specification (210X 297 mm) (Please read the precautions on the back before filling in the page)
415040 經濟部中央揉準局貝工消费合作社印製 A7 B7 五、發明説明(7) 請參考圖六,將光阻去除後,在PMOS區閘極180兩側 形成側壁子(Sidewall Spacer)210。接著以離子佈植技術,對 所述PMOS區進行高濃度離子摻雜220,以形成PMOS區的汲 /源極230。本發明所述在積體電路中形成互補式金氧半場效 電晶體的方法於焉完成。 形成所述側壁子210,是先沉積一層氧化矽,再進行回 蝕刻步驟所形成。所述氧化矽是利用低壓化學氣相沉積法 (LPCVD),以TEOS爲反應氣體所形成的氧化矽層;也可以 是利用電漿增強式化學氣相沉積法(PECVD)所形成的氧化矽 層。所述高濃度離子摻雜係以二氟化硼8匕離子進行,其離 子能量介於60KeV到80KeV之間,其摻雜濃度介於1E15離子 /平方公分到5E15離子/平方公分之間。 此時因在閘極180的上方還有一層硬式護罩160,因此所 形成側壁子210之寬度較大,所形成電晶體的淡摻雜汲極也 因此較寬,可更進一步減低所形成電晶體的熱電子效應(Hot Electron Effect),增進產品的品質和可靠度。 以上係以最佳實施例來閫述本發明,而非限制本發明, 並且,熟知半導體技藝之人士皆能明瞭,適當而作些微的改 變及調整,仍將不失本發明之要義所在,亦不脫離本發明之 精神和範圍。 -1 ! - - - ί ----—, ! I— — I .....- I 、1T I (請先閎讀背面之注意事項再填寫本頁) 8 本紙張尺度適用中圉國家標準(CNS ) A4規格(210X297公釐)415040 Printed by the Central Government Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative A7 B7 V. Description of the invention (7) Please refer to Figure 6. After removing the photoresist, side walls 210 are formed on both sides of the gate 180 in the PMOS area. Then, the ion implantation technology is used to perform high-concentration ion doping 220 on the PMOS region to form a drain / source 230 of the PMOS region. The method for forming a complementary metal-oxide-semiconductor half-field-effect transistor in an integrated circuit according to the present invention is completed. The sidewall 210 is formed by depositing a layer of silicon oxide and then performing an etch-back step. The silicon oxide is a silicon oxide layer formed by using a low pressure chemical vapor deposition method (LPCVD) and TEOS as a reaction gas; it may also be a silicon oxide layer formed by a plasma enhanced chemical vapor deposition method (PECVD). . The high-concentration ion doping is performed with boron difluoride 8 ions, and its ion energy is between 60 KeV and 80 KeV, and its doping concentration is between 1E15 ions / cm 2 to 5E15 ions / cm 2. At this time, because there is a layer of hard shield 160 above the gate 180, the width of the side wall 210 formed is relatively large, and the lightly doped drain of the formed transistor is therefore wider, which can further reduce the formed electricity. The hot electron effect of the crystal improves the quality and reliability of the product. The above is a description of the present invention with the best embodiment, rather than limiting the present invention, and those who are familiar with the semiconductor technology will understand that making slight changes and adjustments appropriately will still not lose the essence of the present invention. Without departing from the spirit and scope of the invention. -1!---Ί ----—,! I— — I .....- I 、 1T I (Please read the precautions on the reverse side before filling out this page) 8 This paper is applicable to the countries in Central China Standard (CNS) A4 specification (210X297 mm)