TW412860B - Semiconductor device - Google Patents

Abstract

In a semiconductor device having at least one memory cell array region in which a plurality of memory cells are arranged in an array form, at least one edge portion is placed at an outermost edge portion of the memory cell array region. A gate is arranged at the edge portion , and a capacitor contact portion is placed adjacent to the gate. The gate is deviated to an outside direction of the memory cell array region with a predetermined distance in order to prevent short between the gate and the capacitor contact protion.

Description

412860

m_ 87121599 V. Description of the invention (1) Background of the invention The present invention relates to a semiconducting hip device, in particular to 2 semiconducting ideas for preventing a short circuit between an outermost contact area located in a memory cell array area and a gate. Device.的 电 备 In the conventional semi-conducting device, # is formed by repeating the arrangement list-memory list ^: ashamed single r train. However, the shape of the element located at the repeated portion in the memory cell array region is different from the element shape located at the outermost edge of the memory cell array region. As a result, a short circuit easily occurs between the capacitive contact area trapped in the outermost edge portion and the gate. In particular, the results after a short circuit are β −

When the element isolation region (element insulation region) is formed in the memory cell array region, in comparison, the formed element isolation region located at the outermost edge portion of the memory cell array region is inevitably more than the element located in the memory cell array region The isolation region is thicker. In this case, when a gate is formed in the memory cell region, a gate located at the outermost edge portion of the memory cell array region is formed at a position higher than the gate located inside the memory cell array region. pole. In the next step, after depositing an interlayer insulating film, the capacitor contact area is opened at the outermost edge portion and the inner position of the memory cell array area, respectively. In this case, when the etched capacitor contact area is gradually tapered, there is no limit between the capacitor contact area and the gate electrode located at the outermost edge portion. Therefore, a short circuit easily occurs. As a result, production yields have fallen significantly. In this case, when the gate located at the outermost

D: \ income \ pl289.ptc

412860 V. Description of the invention (2) When the repeating pitch in the memory cell array area is arranged at the same pitch, the capacitor contact area located at the outermost edge portion and the gate are prone to short circuit. Further, during the manufacturing process, the outermost edge portion is used to suppress or limit the limit related to the misalignment between the capacitive contact area and the gate electrode located at the outermost edge portion. In order to solve the above short-circuit problem, there have been two improvements to this conventional technique. In the first conventional technique, a redundant virtual pattern is inserted into the outermost edge portion of the memory cell array area. In particular, in the outermost edge portion, a component isolation area, a diffusion area, a Gate, ·-Capacitive contact area and polycrystalline area for storing electricity. In the second conventional technique, a sidewall barrier film is formed in the capacitor contact area. This process can be referred to as a sidewall contact process. In this case, even when the gate is exposed by opening the capacitor contact area, the gate can be protected by the side wall barrier film. As a result, a short circuit between the gate and the capacitor contact area can be avoided. However, in the first conventional technique, a redundant virtual pattern is placed on the outermost edge portion of the memory cell array region. As a result, the discarded area is boosted, and therefore, the wafer size inevitably becomes large. On the other hand, in the second conventional technology, since the CVD growth of the oxide film and the dry cashback process need to be completed, an additional process must be added. Therefore, the production period of the product becomes longer, and further, the productivity decreases. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a memory cell array.

412860 __ Case No. 87121592 gj ^ ζ b yu a V. Description of the invention (3) A semiconductor device which is not prone to short circuit between a capacitive contact area and a gate electrode in the outermost edge portion of the area. Another object of the present invention is to provide a semiconductor device capable of manufacturing a certain boundary and improving the production yield. Yet another object of the present invention is to provide a method for preventing a short circuit between a capacitor contact region and a gate electrode located in an outermost edge portion of a memory cell array region without the need to increase the size of a wafer by providing a dummy chip. Semiconductor device. According to the present invention, a semiconductor device has at least one memory cell array region. A plurality of memory cells are arranged in an array in the area of the billion-cell array. In this structure, at least the outer edge portion of the memory cell array region is provided with an edge portion β. Further, the first gate electrode is repeatedly disposed at an inner portion of the memory cell array region at a predetermined first pitch. Further, a second gate is provided at the edge portion at a second pitch. Under this condition, in the present invention, the first pitch is different from the second pitch. In particular, this second pitch is wider than the first pitch. That is, the second gate is deviated from the memory cell array region by a predetermined distance. For example, this predetermined distance ranges from 0, 02 to 0_lum. Furthermore, a capacitive contact region is formed between a first gate electrode and the second gate electrode. In this case, the second gate is deviated outward to prevent the second gate from contacting the capacitor contact area. In this example, the capacitor contact area is formed into a tapered shape.

D: \ income \ pl289.ptc Page 7 2⑽05 · 24. 007 412860 V. Description of the Invention (4) Furthermore, some of the first gate electrodes are formed on the isolation region of the first element, and the second gate electrode It is disposed on the second element isolation region. In this case, the thickness of the second element isolation region is thicker than that of the first element isolation region. As a result, the height of the second gate is higher than the height of the first gate. Under this condition, even when the capacitive contact area is formed in a push shape, a short circuit is unlikely to occur between the capacitive contact area located at the outermost edge portion of the memory cell array area and the second gate. Further, even when the misalignment occurs at the step of forming the capacitive contact area, the manufacturing limitation does not depend on the outermost edge portion. As described above, the second gate electrode is shifted outward from the outermost edge portion by 0, 0 2 to 0. lum compared with the repeated pitch at the inner portion of the memory cell array region. Thereby, the green guard has a boundary between the capacitor contact area of the outermost edge portion and the second gate to prevent a short circuit. Further, it is possible to avoid a short circuit between the capacitive contact area of the outermost edge portion and the second gate electrode without wastefully increasing the size of the wafer by providing a dummy pattern. Furthermore, the product production period is shortened and productivity is increased because no additional steps such as C V D growth and etch-back treatment of the oxide film are required. Brief Description of the Drawings FIG. 1 is a schematic sectional view showing a problem of a conventional semiconductor device, and FIG. 2 is a sectional view showing a semiconductor device according to a first conventional technology;

412860 V. Description of the invention (5) FIG. 3 is a view; FIG. 4 is a view; and FIG. 5 is a front view. DESCRIPTION OF SYMBOLS 1 1, 1 2 1 3, 14 1 6 '1 7 indicates a cross section of a semiconductor device according to a second conventional technology, and a flat display of a semiconductor device according to an embodiment of the present invention. Section element isolation (insulation) area Gate capacitance contact area 1 8: Virtual pattern 19: Side wall barrier film 2 2: Memory cell array area 2 3: Outermost edge portion 2 4: Sense signal amplification portion 2 5: Line decoder For a detailed description of some preferred embodiments, refer to FIGS. 1 to 3. In order to better understand the present invention, a conventional semiconductor device is described first. This semiconductor device is the same as the conventional semiconductor device mentioned in the preamble of this specification. First, as shown in FIG. 1, a plurality of gates 13 and 14 are disposed in a memory cell array region. In this case, capacitive contact regions 16 and 17 are formed between the element formation region and the element isolation (insulation) regions 1 1 and 12. When element isolation regions 1 1 and 1 2 are formed in the memory cell array region

412860 _ Case number 87121592? Moon Heart

/ 7 Revised pottery: iJ 5. In the description of the invention (6), compared with the element isolation region 11 formed inside the memory cell array region, the comparison of the element isolation region 12 located at the outermost edge portion of the memory cell array region is unavoidable. thick. This is because the width of the element isolation region 11 formed inside the memory cell array region is narrow, so that the growth of the isolation oxide film is suppressed compared to the element isolation region 12 located at the outermost edge portion. In this case, when the gates 13 and 14 are formed in the memory cell array region, the gates 14 formed at the outermost edge portion in the memory cell array region are formed more than the gates located inside the memory cell array region. Is higher. In the next step, after depositing an interlayer insulating film, the capacitor contact regions 16 and 17 are opened at the outermost edge portion and the inner (internal) position of the memory cell array region, respectively. In this case, when the etched capacitor contact region 17 has a tapered shape as shown in Fig. 1, there is no boundary between the capacitor contact region 17 and the gate electrode 14 at the outermost edge portion. As a result, a short circuit easily occurs. In this case, when the gate electrode 1 4 located at the outermost edge portion is provided so as to have a pitch as large as the repeating pitch located inside the memory cell array region, the capacitor contact area located at the outermost edge portion 7 and the gate Short-circuits easily occur between poles 丨 4. Further, 'the limit associated with the alignment deviation between the capacitive contact area 17 and the gate electrode 14 located at the outermost edge portion is suppressed or limited by the outermost edge portion. With reference to FIG. 2, the first conventional technology will be described. ΙΗΗΗΙ \\ Server \ specVPU2 \ pl289.ptc Page 10 '412860 V. Description of the invention (7) In the first conventional technology, a redundant virtual pattern 18 Insert into the memory cell array area 2 2. In particular, in the outermost edge portion of the memory cell array region 22, an element isolation region 1 2, a diffusion region, a gate 13, a capacitor contact region 16 and 17 are placed in a straight line and used for storage Polycrystalline region of charge. More specifically, the virtual pattern area 18 is inserted into the outermost edge portion of the memory cell array area 22 on the right-hand side according to the dotted line illustrated in FIG. 2. In this way, the dummy pattern 18 is inserted into the outermost edge portion of the memory cell array region 22, as illustrated in FIG. In this structure, even when a short circuit occurs between the capacitive contact area 17 and the gate electrode 14 of the outermost edge portion, since the short circuit is between the dummy patterns, the product is not damaged. Thereby, the element isolation region (oxide film) 12 and the gate electrode 14 located at the outermost edge portion are formed so as to have substantially the same shape as those of the element isolation region and the gate electrode located inside the memory cell array region 22 . As a result, in the first conventional technique, defects caused by short circuits are not easy to occur. Next, a second conventional technique will be described with reference to FIG. 3. As shown in FIG. 3, after the capacitor contact regions 16 and 17 are opened, an oxide film is deposited by using a conventional CVD process, and the oxide film is etched back by dry etching. Thereby, a side wall barrier film 19 is left on the inner side walls of the capacitor contact areas 16 and 17. In this case, even when the gate electrode 14 is exposed by opening the capacitor contact area 17, the gate electrode may be protected by a side wall barrier film 19 composed of an oxide film.

412860 V. Description of Invention (8) 14. As a result, a short circuit can be prevented from occurring. However, in the first conventional technique, the redundant dummy pattern 18 is provided on the outermost edge portion 22 of the memory cell array region. As a result, the waste area is greatly increased, and as a result, the wafer size is inevitably increased. On the other hand, in the second conventional technique, since the C V D growth and dry etch-back treatment of the oxide film need to be completed, an additional process must be added. As a result, the product production period becomes longer and the productivity is further reduced. In view of the above problems, the present invention provides a semiconductor device capable of preventing a short circuit between a capacitive contact region and a gate electrode located at an outermost edge portion of a memory cell array region. 4 to 5, a semiconductor device according to an embodiment of the present invention will be described. As shown in FIG. 4, a semiconductor device (a memory device) includes a plurality of memory cell array regions 2 2, a sensing signal amplifying section 24, and a row decoder section 25. Here, it should be noted that the reference numeral 2 3 represents the outermost edge portion of the memory cell array region 22. This outermost edge portion 23 corresponds to an area inserted into the above-mentioned dummy pattern 18 as illustrated in FIG. 2. Thus, the semiconductor device has a memory cell array region 22, and in the memory cell array region 22, a plurality of memory cells are arranged in an array manner. In this case, a gap is set at the gates 14 of the outermost edge portion 23 of the memory cell array region 22, and this gap is wider than the gap between the gates 13 of the inner cell 22 of the memory cell array region. As shown in Figure 5. In particular, the gates 1 4 provided on the outermost edge portion 2 3 of the memory cell array region 2 2 are intentionally located on the outer side indicated by the arrow in FIG. 5 1IIR 11 (11 in 1 page 12

412860 --- # ‘q Year ST Month W a ^ _ V. Description of Invention (9) Deviation from a predetermined distance upward. Therefore, the material part in Figure 5 represents the outward gate 1 4. The blank part is used to show the relative position relationship of the gate after the deviation] 4 fill. 02 ~ 0. Lum。 More specifically, compared with the gates 1 3 repeated at the same pitch in the memory cell array region 22, the gates 1 4 located at the outermost edge portion 23 are deviated from the outer direction 0. 02 ~ 0. Lum. In this embodiment, the element isolation region 12 formed at the outermost edge portion 23 is thicker than the element isolation region 11 located inside the memory cell array region 22. Further, even when the formed capacitive contact regions] 6 and 7 are pushed shapes, a short circuit between the capacitive contact region 17 and the gate 14 of the outermost edge portion 23 of the memory cell array region 22 can be avoided. Furthermore, during the formation of the capacitive contact region 17, the limit of the alignment deviation is not determined by the outermost edge portion 23 of the memory cell array region 22. In addition, compared with the case of inserting the dummy file 18 as described in "2", the size of the wafer area in the semiconductor device does not increase. That is, when the dummy pattern 18 is provided on the outer edge portion 23 of each memory cell array region 22, the increase of one edge of the chip is calculated according to the following formula: the size of the dummy circle 18 and the number of repetitions of the edges. Assume that the size of the virtual circle 18 shown in Figure 2 is 4um, and the number of repetitions of the edge of the 16-cell group is 32. In this case, one edge of the chip is equal to 32 X 4 = 1 28uin 'so it becomes very Big. Conversely, if one edge of the wafer becomes larger, the amount of repetition of the edge in the embodiment of the present invention is offset by the gate. In this case, it is assumed that the deviation of the gate 14 of the outermost edge portion 23 in the display is equal to 0.1 lum, and the side

D: \ income \ pl289.ptc Page 13 2000. 05. 24.013 Case No. 87121592 Γ 月 冷月 5. Description of the invention (10) The repetition number of the fate is 32. Under this condition, one side of the wafer is equal to 32 X 0.1 = 3.2um, which becomes very small compared to the conventional example described above. It can be made clearer by comparing the magnitude of the dummy pattern 18 shown in FIG. 2 and the deviation amount of the gate electrodes 14 shown in FIG. 5. In this case, when the memory device has a large capacity and the number of divisions increases, the difference changes greatly. Η D: \ income \ pl289.ptc Page 14 2000. 05. 24. 014

Claims (1)

412860 ^ M > Va Amend J ^ 87121592 6. Patent application scope 1it single-species: "device 'has at least ~ memory cell array area formed by a plurality of devices configured in an array including 疋; this semiconductor edge portion :; edge portion' ^ An electric closed electrode is formed between any one of the first gate electrode and the second gate electrode located at the outermost area of the shame cell array area. The two gates are divided according to the points. The aforementioned first distance is different from the above. 2. If the scope of the patent application is the first, the aforementioned second distance is longer than the first interval. ^ &Quot; ^ 4 · If the scope of the patent application is 3rd, the range of the predetermined distance is 0.02. 5 · If the scope of the patent application is the 3rd contact area. The second gate is in contact with the capacitor contact area on the outer side. For example, in the fifth aspect of the patent application, the capacitor contact area is repeatedly arranged at the first pitch and the second pitch is disposed at the second pitch of the edge. The semiconductor device of the item, wherein: Wide. The semiconductor device of the item, wherein; the semiconductor device of which the outer direction of the cell array region deviates from the item, wherein: to 0. lum. The semiconductor device of the item, wherein: the capacitance direction is deviated from to prevent the second gate from the item A semiconductor device in which the shape becomes gradually tapered. The D: \ income \ pl289.ptc Page 15 2_. 05.24, 〇15 7. The semiconducting device according to item 1 of the patent application scope, wherein: some of the first gates are formed on a first element isolation area and the first gate is disposed on a second element isolation Above the area, The thickness of the first element isolation region is greater than the height of the first element isolation region of the semi-ship device according to item 7 of claim 7, wherein: the height of the second gate is higher than the height of the first gate. 9. A semi-conducting ship device having at least a single shame unit configured in the form of an array of plural Λ It cells. The semiconductor device includes:-at least one edge portion and edge portion; 'disposed on the shame cell array The outermost area of the area is at least-the gate electrode is disposed at the edge portion; and the capacitive contact area is disposed at a position close to the gate electrode; In order to prevent a short between the gate and the capacitor contact area. For example, the semiconductor device according to item 9 of the patent scope, wherein: the range of the predetermined distance is fixed between 0.02 and 0.1 lum. 11. The semiconductor device according to item 9 of the patent application, wherein: the capacitor contact area is formed into a tapered shape. 12. The semiconductor device as claimed in claim g, wherein: the gate is formed above the element isolation region.