KR100307992B1 - Semiconductor device - Google Patents

Abstract

In a semiconductor device having at least one memory cell array region in which a plurality of memory cells are arranged in an array form, at least one edge portion is positioned at the outermost edge portion of the memory cell array region. A gate is arranged at the edge portion, and a capacitor contact is located adjacent to the gate. To prevent a short between the gate and capacitor contacts, the gate is out of a predetermined distance in the outward direction of the memory cell array region.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device for preventing a short circuit between a capacitor contact portion and a gate at an outermost edge portion of a memory cell array region.

In a conventional semiconductor device, a single memory cell is repeatedly arranged to form a memory cell array. However, the device shape at the repeating portion inside the memory cell array area is different from the device shape at the outermost edge of the memory cell array area. As a result, a short circuit between the capacitor contact and the gate is likely to occur at the outermost edge portion.

In particular, the above short circuit occurs as follows.

When forming a device isolation region (device isolation region) in the memory cell array region, the device isolation region in the outermost edge portion of the memory cell array region is inevitably formed thicker than the device isolation region in the memory cell array region.

Under such a situation, when forming a gate in the memory cell region, the gate of the outermost portion of the memory cell array region is formed at a position higher than the gate inside the memory cell array region.

In the next step, after depositing the interlayer insulating film, the capacitor contacts are opened at the inner portion and the outermost edge portion of the memory cell array region, respectively.

In this case, if the capacitor contact is etched in a tapered shape, there is no margin between the capacitor contact and the gate at the outermost edge, and a short circuit easily occurs. As a result, the production yield is drastically reduced.

At this time, if the gate is arranged at the outermost edge portion at the same interval as the repetition interval inside the memory cell array region, a short circuit is likely to occur between the capacitor contact portion and the gate at the outermost edge portion.

In addition, the margin for misalignment between the capacitor contacts and the gate at the outermost edge portion is limited by the outermost edge portion during the manufacturing process.

In order to solve the above short circuit phenomenon, two prior arts have been proposed.

In the first conventional technique, the redundant dummy pattern is inserted into the outermost edge portion of the memory cell array region. In particular, device isolation regions, diffusion regions, gates, capacitor contacts, and charge accumulation polysilicon are located in a row of the outermost edge portions.

In the second prior art, a sidewall insulating film is formed inside the capacitor contact portion. This process is called sidewall contact process. In this case, even if the gate is exposed by opening the capacitor contact, the gate is protected by the sidewall insulating film. As a result, a short circuit between the gate and the capacitor contact can be prevented.

However, in the first conventional technology, since the redundant dummy pattern is arranged at the outermost edge portion of the memory cell array region, the wasted area is increased, and as a result, the size of the chip is unavoidably large.

On the other hand, in the second prior art, since the CVD growth and dry etchback processes of the oxide film have to be performed, additional manufacturing processes increase. Therefore, working time becomes long and productivity falls.

Accordingly, it is an object of the present invention to provide a semiconductor device in which a short circuit between the capacitor contact portion and the gate does not easily occur at the outermost edge portion of the memory cell array region.

Another object of the present invention is to provide a semiconductor device capable of securing a manufacturing margin and improving a manufacturing yield.

It is another object of the present invention to provide a semiconductor device capable of preventing a short circuit between the capacitor contact and the gate at the outermost edge portion of the memory cell array region without an unnecessary increase in chip size due to the arrangement of the dummy pattern.

According to the present invention, a semiconductor device has one or more memory cell array regions, in which a plurality of memory cells are arranged in an array form.

In such a structure, at least one edge portion is located at the outermost edge portion of the memory cell array region.

First gates are repeatedly arranged at predetermined first intervals within the memory cell array region. Also, second gates are arranged at the edge portions at second intervals. In this condition of the present invention, the first interval is different from the second interval.

In particular, the second interval is wider than the first interval. That is, the second gate deviates by a predetermined distance in the outward direction of the memory cell array region. For example, the preselected distance is in the range of 0.02 to 0.1 μm.

In addition, a capacitor contact is formed between one of the first gates and the second gate. At this time, in order to prevent the second gate from contacting the capacitor contact, the second gate is deviated outwardly. In this case, the capacitor contacts are formed in a tapered shape.

Also, some of the first gates are formed on the first device isolation region, and the second gate is arranged on the second device isolation region. In this case, the thickness of the second device isolation region is thicker than the thickness of the first device isolation region. As a result, the height of the second gate is higher than the height of the first gate.

Under these conditions, even if the capacitor contacts are tapered, a short circuit between the capacitor contacts and the second gate at the outermost edge of the memory cell array region is unlikely to occur.

Moreover, even if an alignment error occurs in forming the capacitor contact, the manufacturing limit does not depend on the outermost edge portion.

As described above, the second gate at the outermost edge portion is 0.02 to 0.1 μm outward from the repetitive interval inside the memory cell array region, thereby ensuring a margin between the capacitor contact portion and the second gate at the outermost edge portion. Short circuit is prevented.

In addition, a short circuit between the capacitor contact at the outermost edge and the second gate is avoided without unnecessary increase in chip size due to the arrangement of the dummy pattern.

Moreover, since additional steps such as CVD growth and etch back processes of the oxide film are unnecessary, the working time is shortened and the productivity is improved.

1 is a schematic sectional view illustrating a problem of a conventional semiconductor device.

2 is a cross-sectional view showing a semiconductor device according to the first prior art.

3 is a cross-sectional view showing a semiconductor device according to the second prior art.

4 is a plan view showing a semiconductor device according to an embodiment of the present invention.

5 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawing

11, 12: device isolation region 13, 14: gate

15: interlayer insulating film 16, 17: capacitor contact portion

18 dummy pattern 19 sidewall insulating film

22: memory cell array region 23: outermost edge portion

24: sense amplifier 25: column decoder

In order to better understand the present invention, a conventional semiconductor device will be described first with reference to FIGS. The semiconductor device corresponds to the conventional semiconductor device mentioned in the preamble of the present specification.

First, as shown in FIG. 1, a plurality of gates 13 and 14 are arranged in a memory cell array region. In this case, the capacitor contacts 16 and 17 are formed between the device formation region 18 and the device isolation (isolation) regions 11 and 12.

When device isolation regions 11 and 12 are formed in the memory cell array region, the device isolation portion 12 at the outermost edge of the memory cell array region is thicker than the device isolation region 11 inside the memory cell array region. Is formed.

This is because the width for forming the device isolation region 11 is narrow in the memory cell array region, and the growth of the isolation oxide film is suppressed as compared with the device isolation region 12 of the outermost edge portion.

Under these circumstances, when the gates 13 and 14 are formed in the memory cell array region, the gate 14 of the outermost edge portion in the memory cell array region is formed at a position higher than the gate 13 in the memory cell array region. .

In a next step, after the interlayer insulating film (not shown) is deposited, the capacitor contacts 16 and 17 are opened in each of the inner and outermost edge portions of the memory cell array region. In this case, as shown in FIG. 1, when the capacitor contact portion 17 is etched in a tapered shape, there is no margin between the capacitor contact portion 17 and the gate 14 of the outermost edge portion, and thus a short circuit occurs easily. .

In this case, if the gates 14 of the outermost edge portion are arranged at the same interval as the repetition interval in the memory cell array region, a short circuit is likely to occur between the capacitor contact portion 17 and the gate 14 of the outermost edge portion.

Also, during manufacture, the margin for misalignment between the capacitor contacts 17 and the gate 14 is limited by the outermost edge portion.

The first prior art will be described with reference to FIG. 2.

In the first prior art, a redundant dummy pattern 18 is inserted into the memory cell array section 22. In particular, device isolation regions 12, diffusion regions, gates 13, capacitor contacts 16 and 17, and polysilicon for charge accumulation are located in the outermost edge of the memory cell array region 22. In FIG.

More specifically, the dummy pattern region 18 is set at the outermost edge portion of the memory cell array region 22 on the right side based on the dotted line A of FIG. 2.

Thus, as shown in FIG. 2, the dummy pattern 18 is inserted into the outermost edge portion of the memory cell array region 22. In such a structure, even if a short circuit between the capacitor contact portion 17 and the gate 14 occurs at the outermost edge portion, the product is not defective because it is a short circuit between the dummy patterns.

Therefore, the device isolation region (oxide film) 12 and the gate 14 of the outermost edge portion are formed in substantially the same shape as those in the memory cell array region 22. As a result, in the first prior art, defects due to short circuits are unlikely to occur.

Next, a second prior art will be described with reference to FIG. 3.

As shown in Fig. 3, after the capacitor contacts 16 and 17 are opened, an oxide film is deposited by a known CVD process, and the deposited oxide film is dry etched back, whereby the interior of the sidewalls of the capacitor contacts 16 and 17 are A sidewall insulating film 19 is formed in the film.

In this case, even if the gate 14 is exposed by opening the capacitor contact 17, the gate 14 is protected by the sidewall insulating film 19 of the oxide film. As a result, the possibility of a short circuit can be avoided.

However, in the first conventional technology, since the redundant dummy pattern 18 is arranged at the outermost edge portion of the memory cell array region 22, the waste area is greatly increased, and consequently the chip size is inevitably large.

On the other hand, in the second prior art, additional manufacturing processes are increased by performing CVD growth and dry etchback processes of the oxide film. As a result, the working time is longer and the productivity is lowered.

In view of the above-described problems, the present invention provides a semiconductor device in which a short circuit between the capacitor contact portion and the gate does not easily occur at the outermost edge portion of the memory cell array region.

A semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 4 and 5.

As shown in FIG. 4, the semiconductor device (memory device) includes a plurality of memory cell array regions 22, a sense amplification portion 24, and a column decoder 25. Here, reference numeral 23 denotes the outermost edge portion of the memory cell array region 22. This outermost edge portion 23 corresponds to a region into which the above-described dummy pattern shown in FIG. 2 is inserted.

Thus, the semiconductor device has a memory cell array region 22 in which a plurality of memory cells are arranged in an array form. In this case, as shown in FIG. 5, the gate 14 of the outermost edge portion 23 in the memory cell array region 22 is spaced between the gates 13 in the memory cell array region 22. Arranged at wider intervals.

In particular, the gate 14 in the memory cell array region 22 located at the outermost edge portion 23 intentionally deviates by a predetermined distance in the outward direction indicated by the arrow A in FIG.

More specifically, the gate 14 located at the outermost edge portion 23 is 0.02 to 0.1 mu m outward in the outward direction compared to the gate 13 which is repeated at equal intervals in the memory cell array region 22. .

In the present embodiment, the device isolation region 12 of the outermost edge portion 23 is formed thicker than the device isolation region 11 in the memory cell array region 22.

In addition, even when the capacitor contacts 16 and 17 are tapered, a short circuit between the capacitor contact 17 and the gate 14 at the outermost edge portion 23 of the memory cell array region 22 is prevented.

Moreover, the limit of alignment error during the formation of the capacitor contacts 17 is not determined by the outermost edge 23 of the memory cell array region 22.

In addition, compared with the case where the dummy pattern 18 shown in FIG. 2 is inserted, the chip size does not increase in area. That is, when the dummy pattern 18 is arranged in the outermost edge portion 23 of each memory cell array region 22, one side of the chip is increased by the size x the number of the edges of the dummy pattern 18.

In the case where the size of the dummy pattern 18 shown in Fig. 2 is 4 m and the number of repetitions in the 16 cell group is assumed to be 32, one side of the chip is extremely large at 32 x 4 = 128 m.

On the other hand, in the present invention, one side of the chip is increased by the amount of edges deviated by the gate number. In FIG. 5, assuming that the amount of the gate 14 deviating from the outermost edge portion 23 is 0.1 μm and the number of edges is 32, one side of the chip is 32 × 0.1 = 3.2 μm, which is extremely compared with the case described above. It is a small amount.

This fact becomes apparent when comparing the size of the dummy pattern 18 shown in FIG. 2 with the amount of deviation of the gate 14 shown in FIG. 5. In this case, when the memory device has a large capacity and the number of divisions increases, the difference becomes more significant.

Therefore, according to the present invention, at the outermost edge portion of the memory cell array region, a short circuit between the capacitor contact portion and the gate does not easily occur,

Can secure manufacturing margins, improve manufacturing yield,

It is possible to provide a semiconductor device capable of preventing a short circuit between a capacitor contact portion and a gate at the outermost edge portion of a memory cell array region without unnecessary increase in chip size due to the arrangement of dummy patterns.

Claims (11)

A semiconductor device having one or more memory cell array regions in which a plurality of memory cells are arranged in an array form. At least one edge portion located at the outermost edge portion of the memory cell array region, First gates repeatedly arranged at predetermined first intervals in the memory cell array region, and And at least one second gate arranged at the edge portion at a second interval, wherein the second interval is wider than the first interval. The method of claim 1, And the second gate deviates by a predetermined distance in an outward direction of the memory cell array region. The method of claim 2, And said predetermined distance is in the range of 0.02 to 0.1 mu m. The method of claim 2. A capacitor contact is formed between one of the first gates and the second gate, And the second gate is deviated outwardly to prevent the second gate and the capacitor contact from contacting each other. The method of claim 4, wherein And the capacitor contact portion is formed in a tapered shape. The method of claim 1, Some of the first gates are formed on a first device isolation region and the second gate is formed on a second device isolation region, And the thickness of the second device isolation region is thicker than the thickness of the first device isolation region. The method of claim 6, And the height of the second gate is higher than the height of the first gate. A semiconductor device having one or more memory cell array regions in which a plurality of memory cells are arranged in an array form. At least one edge portion located at the outermost edge portion of the memory cell array region, At least one gate arranged at said edge portion, and A capacitor contact located adjacent said gate, And the gate deviates by a predetermined distance outwardly of the memory cell array region to prevent a short circuit between the gate and the capacitor contact portion. The method of claim 8, And said predetermined distance is in the range of 0.02 to 0.1 mu m. The method of claim 8, And the capacitor contact portion is formed in a tapered shape. The method of claim 8, And the gate is formed on the device isolation region.