TW412849B - Method for manufacturing embedded dynamic random access memory - Google Patents

Abstract

A method for manufacturing embedded dynamic random access memory is disclosed. It utilizes the variance of the etching selectivity of the insulating layers made by different materials and the sequence for executing dry etching and wet etching process depending on the actual requirement so as to enlarge the top opening of the plug contact window. Therefore, it is able to generate a plug with a top portion wider than the bottom portion, thereby increasing the tolerance in the subsequent process, and thus solving the formation problem of deep contact windows.

Description

412849 it V. Description of Invention (1) " '~ Species

The present invention relates to a semiconductor device, and in particular, to a method for manufacturing an embedded dynamic random access memory D. In traditional semiconductor design, most of the logic device and the memory device are formed on different chips, and then are arranged on the same board. on. Since the logic device and the memory device are located on different chips, the high speed cannot be ensured. Because =, most of the devices that use memory devices and logic devices on the same chip today are also called embedded dynamic random access memory. As the integration degree of the integrated circuit increases, the aspect ratio of the contact window becomes larger and larger, which causes difficulties in the manufacturing process. In order to solve the problem that the deep contact window is not easy to form, a two-stage etching contact window method is generally used. The manufacturing process will be outlined below. First, please refer to FIG. 1 to distinguish the embedded dynamic random access memory into a memory cell area and a logic circuit area. The semiconductor substrate 10 includes a shallow trench isolation region STI (shallow trench isolation), gates G1, G2, G3, G4, G5, and source / drain regions 12a, 12b, and 12c. After that, the insulating layer 14 is completely formed. Then, a bit line 16 is formed in the insulating layer 14 of the memory cell region to be in contact with the source / drain region 12b. Then, an insulating layer 18 is formed to completely cover each layer on the substrate 10. Next, a capacitor C 'is formed in the memory cell region in contact with the source / drain regions 12a, which includes a lower electrode 20, a dielectric layer 22, and an upper electrode 24. After the capacitor is formed in the memory cell area, a two-stage contact window process is performed. First, an insulating layer 26 is formed so as to completely cover each layer on the substrate 10. Then use lithography and etching to form the logic circuit area.

412849 A. V. Description of the invention (2) The __ touch window 27 which is in communication with the source /; and the electrode region 12c is filled with a metal substance to form a touch window 27. Thereafter, the first access 4 metal inserting chamber 98 is provided. Next, the insulating layer 30 is deposited by a full: f28 mechanical polishing method to form the above-mentioned substrate, and it is applied to the logic circuit area = surface by an etching technique and an etching method. Then, the second contact window 31 of the micro communication is used. However, due to the error that the contact window 31 connected to the first contact window 27 is not aligned with the first contact window 27, it often occurs that the metal layer 32 in the second 31 cannot be filled with the metal plug 8 ^ Damaged contact window. The bracelet drag plug 28 is turned on, so that the properties of the component are therefore solved. In order to solve the above-mentioned problem, a method for manufacturing a state random access memory ^ provides an embedded dynamic creation of the above-mentioned memory, the above-mentioned memory includes a half = circuit area on the substrate 'The above-mentioned manufacturing method includes the following steps: the element region and the logic circuit region are transformed, and a transistor including a gate electrode, a source electrode, and a non-electrode electrode is formed on the upper electrode; and sequentially on the memory cell region; Forming a bit line and a capacitor connected to the source / drain of the disk; sequentially forming a first insulating layer and a second insulating layer of different materials on the ^ substrate; defining the above-mentioned insulating layer in the above-mentioned logic circuit area, and forming A first-contact window that is in communication with the source / drain and has a wider top than the bottom; a first-metal plug is formed in the first J-contact window; a third insulating layer is formed on the semiconductor substrate; Forming a second contact window in the third insulating layer of the logic circuit area in communication with the first contact window; and forming a contact with the first metal plug in the two contact windows Another proposed - kind of embedded dynamic random mechanism

l ^ fll Page 5_ 412849_ Five 'Description of the invention (3) Manufacturing method, suitable for manufacturing the above-mentioned memory on a semiconductor substrate, suitable for manufacturing the above-mentioned memory on a semiconductor substrate, the above-mentioned memory includes a memory cell Zhuoyuan region And a logic circuit region, the above-mentioned manufacturing method includes the following ^. On the above-mentioned memory cell region and the above-mentioned logic circuit region, two shapes are formed respectively-a transistor including a gate electrode and a source / drain electrode; A bit line and a capacitor connected to the source / drain are sequentially formed, and a first insulating layer, a second insulating layer, and a protective layer are sequentially formed on the semiconductor substrate, wherein the material of the first insulating layer is different from that of the first An insulation layer and the protection layer; defining the insulation layer and the protection layer in the logic circuit area to form a first contact window communicating with the source / drain and having a wider top than a bottom; formed in the first contact window -A first metal pad; a third insulating layer is formed on the semiconductor substrate in a comprehensive manner-a third insulating layer formed in the third insulating layer of the logic circuit area and the first insulating layer A first contact window in common contact window; and forming a second metal contact pads of the first pad in said third contact. In the above method, a metal plug with a wider top than a bottom can be manufactured. Since the metal plug has a wider top, the tolerance of subsequent process errors can be improved, so the problem of forming a deep contact window can be solved. In order to make the objects, features, and advantages of the present invention more obvious and easy, the following is a detailed description of a preferred embodiment and the accompanying drawings' as follows: Brief description of the drawings Figure 1 is a schematic cross-sectional view. To explain the manufacturing results of the conventional embedded dynamic random access memory. Figures 2A to 2G are schematic cross-sectional views for explaining the present invention.

Page 6 412849 V. Description of the Invention (4)-A preferred embodiment of the manufacturing process of the embedded dynamic random access memory. 3A to 3E are schematic cross-sectional views for explaining a manufacturing process of an embedded dynamic random access memory according to another preferred embodiment of the present invention. Explanation of symbols 10 & 40 ~ semiconductor substrate; G ~ gate; 16 & 48 ~ bit line; 20 & 52 ~ lower electrode; 22 & 54 ~ dielectric layer; 24 & 56 ~ upper electrode; 14, 18 , 26, 30, 44, 50, 58, 60 & 6 Bu insulation layer; 27, 65 & 74 ~ first contact window; 28, 68 & 82 ~ metal pad; 31, 72 & 80 ~ second contact window; 32 & 74 Metal Zhan ;. EXAMPLES Example 1 The following will describe the first embodiment of the present invention using FIG. 2A to FIG. 2G. First, the embedded dynamic random access memory is divided into a memory cell region and a logic circuit region. FIG. 2A shows that the semiconductor substrate 40 has a shallow groove isolation region STI, gates G1 ′, G2, and G3 ′. , G4,, G5, and source / drain regions 42a, 4 2b, 42c. The contact window 46 in contact with the drain region 42b is obtained by selectively etching the insulating layer 44. The insulating layer 44 may be a non-doped silicon oxide (non-doped silicon oxide) glass layer. Next, a bit line 48 is formed in the memory cell region. First, a conductive layer is formed on the surface of the insulating layer 44 by a sputtering method or a chemical disorder deposition method, and the conductive layer is filled into the contact window 46. The conductive layer can be doped with polycrystalline silicon or metal tungsten. Next, the lithography technology and etching method are used to determine

412849 V. Description of the invention (5) The above conductive layer is defined to form a bit line 48. Next, referring to FIG. 2B, a step of forming a capacitor C 'in a memory cell region is shown. First, an insulating layer 50 is formed so as to completely cover the substrate 40 shown in FIG. 2A. The insulating layer 50 may be undoped silicon oxide. Next, a lower electrode 52 is formed in contact with the source region 42a. The material of the lower electrode 52 can be conductively doped polycrystalline silicon. Then, in the form of a dielectric layer 54 in the shape of 2, a material having a high dielectric constant such as oxygen cutting / gasification (ONOwxide / nitride / oxide), an oxide button (Ta205), silicon nitride, or silicon nitride can be used. Insulation. An upper electrode 56 is formed on the dielectric layer 54. The material of the upper electrode 56 can be conductively doped polycrystalline silicon. Therefore, the lower electrode 52, the dielectric layer 54 and the upper electrode 56 together constitute a capacitor c. Thereafter, referring to FIG. 2C, an insulating layer 58 is sequentially formed on the semiconductor substrate 40 in this order. Then, an insulating layer 60 is formed on the insulating layer 58 with a material different from that of the insulating layers 44: 50 and 58. In this example, the insulating layers 44 and 50 and "the undoped silicon oxide is used, and the insulating layer 60 is doped silicon oxide (doped si 1 iCon oxlde) are taken as examples. The impurity of the insulating layer 60 may be or Phosphorous ions. Next, referring to FIG. 2D, a photoresist layer 62 having an opening 64 is formed on the insulating layer 62. Referring to FIG. 2E, a communication with the source / = c is formed in the insulating layer. And the first contact window having a wider opening at the top than the opening at the bottom, using the photoresist layer 62 as a cover, first performs a dry etching on the above-mentioned insulating layer: engraving 'extends the opening 64 to the source " and electrode 42c surfaces, and then executes A pair of insulating layers 60 has a higher selectivity than the wet layers of insulating layers 44, 50, and 58

412849 ~ _________ V. Description of the invention (6) The money engraving method etches the insulating layer 60 horizontally through the opening 64 to complete the first contact window 66. If the insulating layer 60 is doped silicon oxide and the insulating layer 44,

5 0 and 5 8 are non-doped silicon oxide. The above isotropic wet etching method can be used. Hydrofluoric acid (HF) can be used. One of buffer oxide etching solution (BOE) and diluted hydrofluoric acid (DHF). In order to etch liquid D, the first contact window 66 may be manufactured by changing the etching order. For example, with the photoresist layer 62 as a cover, the above-mentioned wet etching method is used to etch the insulating layer 60 through the opening 64 to extend the opening laterally, and then the dry etching method is used to etch the above-mentioned insulating layer to the source through the opening 64. / Drain 42c surface. After that, the photoresist layer 62 is removed. Next, referring to FIG. 2F, a metal substance is filled in the first contact window 66 to form a metal plug 68 in the logic circuit area. The above-mentioned metal substance may be metallic tungsten, for example, a tungsten layer is deposited on the insulating layer 60, the tungsten layer is filled in the first contact window 66, and then the tungsten layer is etched back until the surface of the insulating layer 60 is exposed. Next, referring to FIG. 2G, an insulating layer 69 is formed on the insulating layer 60, and the insulating layer 69 is polished by chemical mechanical polishing to make it a flat surface that completely covers the substrate 40 described above. Then, the insulating layer 69 is selectively etched in the logic circuit region by using a lithography technique and an etching method to form a second contact window 72 exposing the metal plug 68 described above. Finally, a metal plug 74 filled in the second contact window 72 is formed. The metal plug 74 may be metal tungsten. In the second embodiment, before the metal layer is deposited in the first contact window, in order to improve the metal layer deposition effect, an etching step before metal deposition is performed (pre-metai IHH Bim, page 9, 41284d. V. Description of the invention (7) dip) To process the first contact window. However, since the above-mentioned etching step often damages the insulating layer, the properties of the device are damaged. To avoid the above problems, the present invention proposes a second embodiment. The following describes the manufacturing process for forming the embedded dynamic random access memory according to the method of the second embodiment. The pre-steps in the second embodiment (the steps of forming a bit line and a capacitor in the memory cell region) are the same as those in FIGS. 2A to 2C of the first embodiment. Start to summarize the manufacturing process of the second embodiment. First, please refer to FIG. 3A, which is a continuation of the semiconductor structure shown in FIG. 2C. A protective layer different from the material of the insulating layer 60 is added to the insulating layer 60. If the insulating layer 60 is doped silicon oxide, the protective layer π is undoped silicon oxide. The results are shown in Figure 3A. After that, a photoresist layer 70 having an opening 72 is formed on the 3B figure. With reference to Figure 3C, the source / 74 is formed in the above-mentioned insulating layer. If the top / contact opening is wider than the bottom opening, the layer 7G is used as a cover, and then the above insulating layer is dried. Method, extending the opening 72 to the source / drain 42c surface—the etching selectivity to the insulating layer 60 is greater than the wet m of the layer 61, and then the insulation through the opening 82 = 50, 58 and the protection-complete contact window 74. Its; if the line is horizontal, the insulation layer 61 is used as the etching solution (B_, / release \ carved fluoric acid can be touched with gas acid (HF), buffer oxides. In addition, you can also change the order of money engraving. Making the first contact window? 4. Example

_ 412849 V. Description of the invention (8) If the photoresist layer 70 shown in FIG. 3B is used as a cover, through the opening 72, a dry-etching method is used to etch the insulating layer 61 to the insulating layer 60, and then the above isotropic wet is performed. The etch method etches the insulating layer 60 through the opening 72 so as to extend the opening laterally, and finally performs a dry etching method to etch the above-mentioned insulating layer to the surface of the source / inverter 42c through the opening 7 2 ′. After that, the photoresist layer 70 is removed. Next, referring to FIG. 3D, a metal substance is filled in the first contact window 74 to form a metal plug 76 in the logic circuit area. The above-mentioned metal substance may be metallic tungsten ', for example, a tungsten layer is deposited on the protective layer 61, the ballast layer is filled in the first contact window 74', and then the tungsten layer is etched back until the surface of the insulating layer 61 is exposed. Next, referring to FIG. 3E, an insulating layer 78 is formed on the insulating layer 61, and the insulating layer 78 is polished by a chemical mechanical polishing method so that it becomes a flat surface completely covering the substrate 40 described above. Then, the surface of the insulating layer 78 and the protective layer 61 to the insulating layer 60 are selectively etched in the logic circuit area by using a photolithography technique and an etching method to form a second contact window gQ exposing the metal plug M described above. Finally, a metal layer 82 filled in the second contact window 80 is formed. The metal layer 82 can be made of a metal tungsten material. Because the present invention mainly uses the difference in the selection ratio of insulating layers made of different materials at the remaining time, 'the implementation order of the isotropic etching method and the anisotropic implementation method can be changed according to actual needs, so that the top opening of the metal pad contact window is changed. Big 'can make a metal pad with a wider top than a bottom. Since the above-mentioned metal pad has a relatively wide top portion, the tolerance of subsequent process errors can be improved, and the problem of forming a deep contact window can be solved. & At the same time, those skilled in the art should understand that the material materials usable in the present invention

412849_ Five 'invention description (9) material is not limited to the traditional dynamic random access memory cited in the embodiment, but also applicable to embedded dynamic random access memory, and can be formed from substances and It is replaced by the method, and the structure space of the present invention is not limited to the dimensions cited in the embodiments. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.

Page 12

Claims (1)

-412849 1. A method for manufacturing an internal memory type cancer random access memory, which is suitable for manufacturing the above-mentioned memory on a semiconductor substrate. The above-mentioned memory includes a memory cell region and a logic circuit region. The above-mentioned manufacturing method includes the following steps: j Steps are formed on the memory cell region and the logic circuit region to form a transistor including a gate electrode and a source / drain electrode; a knife is sequentially formed on the memory cell region to communicate with the source / non-electrode. Bit lines and capacitors; sequentially forming first-insulating layers and second insulating layers of different materials on the semiconductor substrate; defining the above-mentioned insulating layer in the above-mentioned logic circuit area, forming a top and a top electrode which are in communication with the source / non-electrode A first contact window wider than the bottom; a first metal plug is formed in the first contact window; a third insulating layer is comprehensively formed on the semiconductor substrate; and a third insulating layer is formed in the logic circuit area A second contact window in communication with the first contact window; and forming a second metal in contact with the first metal plug in the second contact window Plug. 2. The method as described in item 1 of the scope of patent application, wherein the step of forming the yth contact window further includes the following steps: ^ performing a dry etching method to form and etch in the above-mentioned insulating layer of the logic circuit area The source / drain region contacts one of the openings; the etching selectivity of the second insulating layer is greater than that of the first insulating layer by the wet surface engraving method, and a part of the second insulating layer is removed through the opening. Page 412849 " 'Please request the scope of patent 3. As described in the second scope of the patent application, the soil ^ ^ = edge layer is made of undoped oxide material in two ways' where the first- Made of miscellaneous silicon oxide. The first insulating layer is made by the method described in item 3 of the scope of patent application, and the impurity of the double-edge layer may be boron or phosphorus ions. It first method 2 The method described in item 4 of the range of π η, ... The method described above makes the above-mentioned step of forming the first contact window further include the following steps: Try "forming a photoresist layer with an opening on the second insulating layer ', wherein the above-mentioned opening is located at the above-mentioned source / The etching selectivity of the second insulating layer above the drain region is greater than that of the first insulating layer. The wet etching method etches a portion of the second insulating layer to the first insulating layer through the openings. Λ 乾 # 刻 法 'Carved the material layer to the above source / and electrode region through the above-mentioned open σ surname. 7, The method as described in item 6 of the scope of patent application, wherein the above-mentioned first == unreplaced oxidation 'Composition and the above-mentioned second insulating layer are composed of mixed silicon oxide. 8. Impurities of the insulating layer as described in item 7 of the scope of patent application may be boron or phosphorus ions. Rside first page 14 412849 VI' Patent application scope 9. If the patent application scope item 8m +, Engraving method uses hydrofluoric acid (HF), buffering κ method, in which one of the above-mentioned wet etching gas hydrofluoric acid (DHF) is an etching liquid. Chemical etching solution (B0E), dilution 10.-a kind of embedded dynamics The manufacturing method for manufacturing the above-mentioned memory device on a semiconductor substrate randomly includes a memory cell unit region and a logic circuit. The memory device includes the following steps: a circuit & field. The above-mentioned manufacturing method includes the following methods described above. § Membrane year region and p 7 are + -formed-γ crystals including closed electrode, source / and electrode ^^ are formed on the above-mentioned memory cell region in sequence on the above-mentioned memory cell region, which are in communication with the above-mentioned source Bit lines and capacitors; the first insulating layer, the second layer, and the protective layer are sequentially formed on the semiconductor substrate; the materials of the second insulating layer are different from the first insulating layer and the protective layer; In the above logic circuit area, the above-mentioned insulating layer and the above-mentioned protective layer are defined to form a first contact window which is in communication with the source / drain and has a wider top than a bottom, and a first metal pad is formed in the first contact window. above A third insulating layer is formed on the semiconductor substrate in a comprehensive manner; a second contact window communicating with the first contact window is formed in the third insulating layer in the logic circuit region; and a first metal is formed in the third contact window The second metal pad in contact with the pad. 11. The method according to item 10 of the scope of patent application, wherein the above-mentioned shape Page 412, 849, "The step of applying for a patent to become the first contact window further includes the following steps: Implementing a dry money engraving method, engraving the protective layer and the insulating layer above the source / immortal electrode in the above-mentioned logic circuit area" Forming an opening in communication with the source electrode and the electrode; performing a wet etching method for the second insulating layer with an etching selectivity greater than that of the first insulating layer, and etching the second insulating layer through the opening. 12. The method as described in item Η of the scope of patent application, wherein the first insulating layer is composed of undoped silicon oxide, the second insulating layer is composed of doped silicon oxide, and the protective layer is composed of Made of doped silicon oxide. 13. The method according to item 12 of the scope of patent application, wherein the impurity of the second insulating layer may be boron or phosphorus ions. 14. The method as described in item 13 of the scope of patent application, wherein the above wet-removing method uses one of hydrofluoric acid (HF) 'buffered oxide etching solution (B0E) and diluted hydrofluoric acid (DHF) for etching liquid. The method according to item 10 of the scope of the patent application, wherein the step of forming the first contact window further includes the following steps: performing a dry etching method to form an opening in the protective layer of the logic circuit region; The etching selectivity of the second insulating layer is greater than the wet etching method of the first insulating layer, and the second insulating layer is etched through the opening; a dry etching method is performed to etch the insulating layer to the source / drain region through the opening Top surface. 16. The method according to item 15 of the scope of patent application, wherein the above-mentioned 412849 VI. Scope of patent application An insulating layer is composed of undoped silicon oxide, the second insulating layer is composed of doped silicon oxide, and the protective layer is composed of undoped silicon oxide. 17. The method according to item 16 of the scope of patent application, wherein the impurity of the second insulating layer may be boron or phosphorus ions. 18. The method according to item 17 in the scope of patent application, wherein the wet etching method uses one of hydrofluoric acid (HF), buffer oxide etching solution (BOE), and diluted hydrogen I acid (DHF) as the money engraving. liquid.